The widespread application of direct-sequence spread-spectrum code division multiple access (DS/SS-CDMA) to wireless communication systems asks for el er faster and more reliable real-time signal processing operations...
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The widespread application of direct-sequence spread-spectrum code division multiple access (DS/SS-CDMA) to wireless communication systems asks for el er faster and more reliable real-time signal processing operations to be performed by highly integrated and low-power consumption digital receivers. One of the most critical signal processing tasks to be performed by the DS/SS-CDMA receiver is signal presence detection and code epoch estimation. This paper deals with the design and realization of an application-specific integrated circuit (ASIC) for fast signal recognition and code acquisition (SR/CA) in packet DS/SS-CDMA receivers operating in a satellite or terrestrial radio network, In particular, we show how a parallel acquisition circuit can be effectively implemented on a single-chip with a 1.0-mu m CMOS technology according to the specifications of the ARCANET Ku-band CDMA VSAT satellite network sponsored by the European Space Agency (ESA). It is shown that the ASIC performance closely follows analytical predictions.
Feature extraction and tracking is a fundamental operation used in many geoscience applications. In this paper, we present a scalable method for computing and tracking features on distributed memory machines for large...
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ISBN:
(纸本)9781509033324
Feature extraction and tracking is a fundamental operation used in many geoscience applications. In this paper, we present a scalable method for computing and tracking features on distributed memory machines for large-scale geospatial data. We carefully apply new communication schemes to minimize the data exchanged among the computing nodes in building and updating the global connectivity information of features. We present a theoretical complexity analysis, and show that our method can significantly reduce the communication cost compared to the traditional method.
A volunteer node can join and leave a volunteer computing system freely. However existing volunteer computing systems suffer from interruptions of job execution, delays of execution time, and increases of total execut...
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ISBN:
(纸本)0769524346
A volunteer node can join and leave a volunteer computing system freely. However existing volunteer computing systems suffer from interruptions of job execution, delays of execution time, and increases of total execution time, since they do not consider dynamic scheduling properties (i.e. volatilities), such as leave, join, and suspension. Therefore, dynamic execution properties of volunteer node should be considered in scheduling schemes, in order to design a stable and reliable volunteer computing system. This paper proposes a new scheduling scheme based on the Dedication Rate (DR), which reflects the dynamic properties of a volunteer. The scheduling scheme improves the completeness and reliability of execution, while also decreasing delay and total execution time. In addition, cut implementation of the proposed scheduling scheme on top of Korea @ Home is described, as well as performance evaluation.
In studying or designing parallel and distributed systems one should have available a robust analytical model that includes the major parameters that determine the system performance. Jackson networks have been very s...
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ISBN:
(纸本)0769521320
In studying or designing parallel and distributed systems one should have available a robust analytical model that includes the major parameters that determine the system performance. Jackson networks have been very successful in modeling parallel and distributed systems. However, they have their limitations. In particular, the product-form solution of Jackson networks assumes steady state and exponential service centers or certain specialized queueing disciplines. In this paper, we use a transient model studying distributed systems with finite workload (no new arrivals). Using some nonexponential distributions we show to what extent the exponential distribution can be used to approximate other distributions. When the number of tasks to be executed is large enough, the model approaches the product-form solution in those cases where the Jackson networks can be applied. We also study some cases where Jackson networks can't be applied (the nonexponential servers have queueing). The model can be used for reliability analysis of systems that allow failures without repair (fail-stop).
In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implemen...
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ISBN:
(纸本)9781424453092
In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implementation in an embedded processor. We demonstrate the superiority of our proposed architecture in terms of performance (by a factor 12), power and energy dissipation (by a factor of 15). We also include the hardware resource requirements in the comparison. Furthermore, the proposed hardware architecture is parameterized and easily scalable. The data processing word size has been successfully extended up to 1024 bits and fitted within the chosen FPGA hardware platform.
Large graph processing is now a critical component of many data analytics. Graph processing is used from social networking web sites that provide context-aware services from user connectivity data to medical informati...
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ISBN:
(纸本)9781479964536
Large graph processing is now a critical component of many data analytics. Graph processing is used from social networking web sites that provide context-aware services from user connectivity data to medical informatics that diagnose a disease from a given set of symptoms. Graph processing has several inherently parallel computation steps interspersed with synchronization needs. Graphics processing units (GPUs) are being proposed as a power-efficient choice for exploiting the inherent parallelism. There have been several efforts to efficiently map graph applications to GPUs. However, there have not been many characterization studies that provide an in-depth understanding of the interaction between the GPGPU hardware components and graph applications that are mapped to execute on GPUs. In this study, we compiled 12 graph applications and collected the performance and utilization statistics of the core components of GPU while running the applications on both a cycle accurate simulator and a real GPU card. We present detailed application execution characteristics on GPUs. Then, we discuss and suggest several approaches to optimize GPU hardware for enhancing the graph application performance.
This paper presents a parallel hybrid exact multi-objective approach which combines two metaheuristics - a genetic algorithm (GA) and a memetic algorithm (MA), with an exact method - a branch and bound (B&B) algor...
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Mobile software agents are software components that are able to move in a network. They are often considered as an attractive technology in electronic commerce applications. Although security concerns prevail. In this...
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ISBN:
(纸本)0769510655
Mobile software agents are software components that are able to move in a network. They are often considered as an attractive technology in electronic commerce applications. Although security concerns prevail. In this paper we describe the architecture and concepts of the SeMoA server - a runtime environment for Java-based mobile agents. Its architecture has a focus on security and easy extendability, and offers a framework for transparent content inspection of agents by means of filters. We implemented filters that handle agent signing and authentication as well as selective encryption of agent contents. Filters are applied transparently such that agents need not be aware of the security services provided by the server.
This paper presents a new power management technique integrated into a multithreaded microcontroller with built-in real-time scheduling schemes. Power management is done by hardware based on the Guaranteed Percentage ...
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ISBN:
(纸本)0769520693
This paper presents a new power management technique integrated into a multithreaded microcontroller with built-in real-time scheduling schemes. Power management is done by hardware based on the Guaranteed Percentage scheduling scheme. The applied power saving mechanisms are frequency reduction, dynamic voltage scaling and pipeline gating. Our evaluation showed that for a given workload with an average processor utilization of 22.6% and a frequent change of utilization in the range of 0% to 58% energy consumption could be reduced to 12.7% of the energy required by a system running at top speed.
In massively parallel computer systems for embedded real-time applications there are normally very high bandwidth demands on the interconnection network. Other important properties are time-deterministic latency and s...
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ISBN:
(纸本)0818675918
In massively parallel computer systems for embedded real-time applications there are normally very high bandwidth demands on the interconnection network. Other important properties are time-deterministic latency and services to guarantee that deadlines are met. In this paper we analyze how these properties vary with the design parameters for a passive optical star network, specifically when used in a massively parallel radar signal processing system. The aggregated bandwidth and computational power of the radar system are approximately 45 Gb/s and 100 GOPS, respectively. The analysis is focused on the medium access control protocol, called TD-TWDMA, for the time and wavelength multiplexed network. It is concluded that the proposed network is very well suited to this kind of signal-processingapplications. We also present a new distributed slot-allocation algorithm with real-time properties.
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