Reconfigurable computing systems have developed the capability of changing the configuration of the reconfigurable coprocessor multiple times during the course of a program. However, in most systems the reconfigurable...
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Obsolete hardware can be effectively reused through intelligent software optimization, which is possible only when source code is available. Virtual Distro Dispatcher (VDD) is a system that produces virtual machines o...
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ISBN:
(纸本)9783540747413
Obsolete hardware can be effectively reused through intelligent software optimization, which is possible only when source code is available. Virtual Distro Dispatcher (VDD) is a system that produces virtual machines on a central server and projects them on a number of costless physical terminals. VDD is the result of an extreme software optimisation based on virtualization and terminal servers. VDD creates and projects Linux distros that are completely customizable and different from each other. They are virtual desktop machines that can be used for testing or developing and are completely controllable directly from each terminal. Memory consumption has been strongly reduced without sacrificing performances. Test results are encouraging to proceed with the research towards clustering.
In this paper, we present a novel approach for parallel sorting on stream processing architectures. It is based on adaptive bitonic sorting. For sorting n values utilizing p stream processor units, this approach achie...
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Due to the rapid improvement in resolution and codec, the number of video sensing device grows fast in the recent years. Tremendous data need to be stored and processed. To meet such a need, we developed a video hosti...
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ISBN:
(纸本)9781479959679
Due to the rapid improvement in resolution and codec, the number of video sensing device grows fast in the recent years. Tremendous data need to be stored and processed. To meet such a need, we developed a video hosting and processing platform for near-realtime applications. An intelligent device can obtain connection-less upload function from our client-side SDK. Video data are sliced into pieces, distributed over cloud-of-clouds and can be processed in parallel once stored. Various video processing algorithms can be mounted together and processed by multiple CPU cores. Performance evaluations show that our platform has the ability to host and process large-scale video data.
In this paper, we first study the interaction between MPI applications and TCP on grids. Then, we propose MPI5000, a transparent applicative layer between MPI and TCP, using proxies to improve the execution of MPI app...
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The paper presents a partitioning and parallelizing programming environment for a novel parallel architecture. This universal embedded accelerator is based on a reconfigurable datapath hardware. The partitioning and p...
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The paper presents a partitioning and parallelizing programming environment for a novel parallel architecture. This universal embedded accelerator is based on a reconfigurable datapath hardware. The partitioning and parallelizing programming environment accepts C-programs and carries out both, a profiling-driven host/ accelerator partitioning for performance optimization in a first step, and in a second step a resource-driven sequential/ structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable resources.
The inter-processor all-to-all communication patterns can be found in many important parallel algorithms. This paper presents new algorithms for all-to-all personalized exchange for circuit switched or wormhole routed...
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The inter-processor all-to-all communication patterns can be found in many important parallel algorithms. This paper presents new algorithms for all-to-all personalized exchange for circuit switched or wormhole routed 2D and 3D torus connected multiprocessors. The algorithms use message combining to minimize message startups at the expense of larger message sizes. The unique feature of these algorithms is that they are the first algorithms that we know of that operate in a bottom-up fashion rather than a recursive top-down manner.
The software crisis within scientific computing has been that application codes become larger and more complex. The only conceivable solution is to make application codes smaller and less complex. We know of no way to...
Computational fluid dynamics (CFD) simulations require a lot of computing resources in terms of CPU time and memory in order to compute with a reasonable physical accuracy. If only uniformly refined domains are applie...
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ISBN:
(纸本)9781479930357
Computational fluid dynamics (CFD) simulations require a lot of computing resources in terms of CPU time and memory in order to compute with a reasonable physical accuracy. If only uniformly refined domains are applied, the amount of computing cells is growing rather fast if a certain small resolution is physically required. This can be remedied by applying adaptively refined grids. Unfortunately, due to the adaptive refinement procedures, errors are introduced which have to be taken into account. This paper is focussing on implementation details of the applied adaptive data structure management and a qualitative analysis of the introduced errors by analysing a Poisson problem on the given data structure, which has to be solved in every time step of a CFD analysis. Furthermore an adaptive CFD benchmark example is computed, showing the benefits of an adaptive refinement as well as measurements of parallel data distribution and performance.
Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal processing (DSP) slices. We propose modifyi...
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ISBN:
(纸本)9781665483322
Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal processing (DSP) slices. We propose modifying BRAMs to convert them to CoMeFa (Compute-In-Memory Blocks for FPGAs) RAMs. These RAMs provide highly-parallel compute-in-memory by combining computation and storage capabilities in one block. CoMeFa RAMs utilize the true dual port nature of FPGA BRAMs and contain multiple programmable single-bit bit-serial processing elements. CoMeFa RAMs can be used to compute in any precision, which is extremely important for evolving applications like Deep Learning. Adding CoMeFa RAMs to FPGAs significantly increases their compute density. We explore and propose two architectures of these RAMs: CoMeFa-D (optimized for delay) and CoMeFa-A (optimized for area). Compared to existing proposals, CoMeFa RAMs do not require changing the underlying SRAM technology like simultaneously activating multiple rows on the same port, and are practical to implement. CoMeFa RAMs are versatile blocks that find applications in numerous diverse parallelapplications like Deep Learning, signal processing, databases, etc. By augmenting an Intel Arria-10-like FPGA with CoMeFa-D (CoMeFa-A) RAMs at the cost of 3.8% (1.2%) area, and with algorithmic improvements and efficient mapping, we observe a geomean speedup of 2.55x (1.85x), across several representative benchmarks. Replacing all or some BRAMs with CoMeFa RAMs in FPGAs can make them better accelerators of modern compute-intensive workloads.
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