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parallel and distributed processing and applications - 5th international symposium, ISPA 2007, Proceedings

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5th international symposium on parallel and distributed processing and applications, ISPA 2007

ISBN: (纸本)3540747419

The proceedings contain 86 papers. The topics discussed include: self-stabilizing distributed algorithms for networks;feature extraction and coverage problems in distributed sensor networks;a self-stabilizing algorithm for 3-edge-connectivity;architecture-based optimization for mapping scientific applications to imagine;implementation and optimization of sparse matrix-vector multiplication on imagine stream processor;a mutual exclusion algorithm for mobile agents-based applications;a distributed metaheuristic for solving a real-world scheduling-routing-loading problem;key-attributes based optimistic data consistency maintenance method;parallelization strategies for the points of interests algorithm on the cell processor;and RWA algorithm for scheduled lightpath demands in WDM networks.

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HSMU-SpGEMM: Achieving High Shared Memory Utilization for parallel Sparse General Matrix-Matrix Multiplication on Modern GPUs

HSMU-SpGEMM: Achieving High Shared Memory Utilization for Pa...

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ieee symposium on High-Performance Computer Architecture

作者： Min Wu Huizhang Luo Fenfang Li Yiran Zhang Zhuo Tang Kenli Li Jeff Zhang Chubo Liu Hunan University Changsha China Arizona State University Tempe United States

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Sparse general matrix-matrix multiplication (SpGEMM) is a core primitive for numerous scientific applications. Traditional hash-based approaches fail to strike a balance between reducing hash collisions and efficiently utilizing fast shared memory, which significantly undermines the performance of executing SpGEMM on GPUs. To address this issue, this paper introduces a novel accumulator design that achieves high shared memory utilization on modern GPUs. For the proposed high shared memory utilization algorithm, i.e., HSMU-SpGEMM 1 , we further optimize different symbolic stages. Our evaluations with four state-of-the-art hash-based SpGEMM libraries (Nsparse, spECK, OpSparse, and NVIDIA’s cuSPARSE) on three NVIDIA GPUs (Ampere, Ada Lovelace, Turing) demonstrate significant performance benefits from HSMU-SpGEMM. 1 HSMU-SpGEMM is available at https://***/wuminqaq/HSMUSpGEMM

关键词： Memory management Graphics processing units Libraries Sparse matrices

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UniNDP: A Unified Compilation and Simulation Tool for Near DRAM processing Architectures

UniNDP: A Unified Compilation and Simulation Tool for Near D...

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ieee symposium on High-Performance Computer Architecture

作者： Tongxin Xie Zhenhua Zhu Bing Li Yukai He Cong Li Guangyu Sun Huazhong Yang Yuan Xie Yu Wang Dept. of EE BNRist Tsinghua University HKUST Institute of Microelectronics Chinese Academy of Sciences Capital Normal University Peking University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Near DRAM processing (NDP) architectures have emerged to be a promising solution for commercializing in-memory computing and addressing the “memory wall” problem, especially for the memory-intensive machine learning (ML) workloads. In NDP architectures, the processing Units (PUs) are distributed next to different memory units to exploit the high internal bandwidth. Therefore, in order to fully utilize the bandwidth advantage of NDP architectures for ML applications, meticulous evaluations and optimizations of data placement in DRAM and workload scheduling among different PUs are required. However, existing simulation and compilation tools face two insuperable obstacles to achieving these targets. On the one hand, tools for traditional von Neumann architectures only focus on the data access behaviors between the host and DRAM and treat DRAM as a whole part, which cannot support NDP architectures with multiple independent processing and memory units working simultaneously. On the other hand, existing NDP simulators and compilers are designed for specific DRAM technology and NDP architecture, lacking compatibility for various NDP architectures. In order to overcome these challenges and optimize data mapping and workload scheduling for different NDP architectures, we propose UniNDP, a unified NDP compilation and simulation tool for ML applications. Firstly, we propose a unified tree-based NDP hardware abstraction and the corresponding instruction set, enabling the support for various NDP architectures based on different DRAM technologies. Secondly, we design a cycle-accurate and instruction-driven NDP simulator to evaluate hardware performance by accurately tracking the working status of memory elements and PUs. The accurate simulation can provide effective guidance for compilation. Thirdly, we design an NDP compiler that optimizes data partition, mapping, and workload scheduling in different DRAM hierarchies. Furthermore, to enhance the compilation efficiency, we propo

关键词： Hands Instruction sets Random access memory Computer architecture Bandwidth Machine learning In-memory computing Hardware Timing Optimization

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PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIM

PIMnet: A Domain-Specific Network for Efficient Collective C...

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ieee symposium on High-Performance Computer Architecture

作者： Hyojun Son Gilbert Jonatan Xiangyu Wu Haeyoon Cho Kaustubh Shivdikar José L. Abellán Ajay Joshi David Kaeli John Kim KAIST Northeastern University Universidad de Murcia Boston University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

processing-in-memory (PIM), where compute is moved closer to memory or data, has been explored to accelerate emerging workloads. Different PIM-based systems have been announced, each offering a unique microarchitectural organization of their compute units, ranging from fixed functional units to programmable general-purpose compute cores near memory. However, one fundamental limitation of PIM is that each compute unit can only access its local memory; access to “remote” memory must occur through the host CPU - potentially limiting application performance scalability. In this work, we first characterize the scalability of real PIM architectures using the UPMEM PIM system. We analyze how the overhead of communicating through the host (instead of providing direct communication between the PIM compute units) can become a bottleneck for collective communications that are commonly used in many workloads. To overcome this inter-PIM bank communication, we propose PIMnet - a PIM interconnection network for PIM banks that provides direct connectivity between compute units and removes the overhead of communicating through the host. PIMnet exploits bandwidth parallelism where communication across the different PIM bank/chips can occur in parallel to maximize communication performance. PIMnet also matches the DRAM packaging hierarchy with a multi-tier network architecture. Unlike traditional interconnection networks, PIMnet is a PIMcontrolled network where communication is managed by the PIM logic, optimizing collective communications and minimizing the hardware overhead of PIMnet. Our evaluation of PIMnet shows that it provides up to $85 \times$ speedup on collective communications and achieves a $11.8 \times$ improvement on real applications compared to the baseline PIM.

关键词： Schedules Microarchitecture Multiprocessor interconnection Scalability Random access memory Organizations Packaging parallel processing Network architecture Logic

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parallel and distributed processing and applications - Third international symposium, ISPA 2005, Proceedings

Parallel and Distributed Processing and Applications - Third...

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3rd international symposium on parallel and distributed processing and applications, ISPA 2005

ISBN: (纸本)3540297693

The proceedings contain 111 papers. The topics discussed include: data structures and algorithms for packet forwarding and classification;towards peta-bit photonic networks;modeling and analysis of a parallel nested loop join on cluster architectures;scheduling efficiently for irregular load distributions in a large-scale cluster;on service-oriented network measurement architecture with mobile agent;design and evaluation of network-bandwidth-based parallel replication algorithm;replicating multithreaded web services;cache management for discrete processor architectures;aggressive loop fusion for improving locality and parallelism;adaptive parallel ant colony optimization;a fast and scalable conflict detection algorithm for packet classifiers;and a new data fusion model of intrusion detection-IDSFP.

关键词： distributed database systems

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Frequency-Domain Guided Multiple parallel Kernels Network for Low-Light Remote Sensing Image Enhancement

Frequency-Domain Guided Multiple Parallel Kernels Network fo...

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international Conference on Acoustics, Speech, and Signal processing (ICASSP)

作者： Jingxuan Zhou Hao Li Jinlong Wang Xiongxin Tang Fanjiang Xu Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

Due to dark environments, optical aberrations, etc, the remote sensing images are often submerged under low contrast degradation, which greatly hinders their practical applications for agricultural management and other related tasks. The surface features of remote sensing images are often continuously distributed in space, thus, the sizes of the network’s receptive fields and its ability to learn long-range dependencies are crucial for restoring low-light remote sensing images. Existing methods based on CNN provide limited receptive fields, while Transformer-based methods are constrained by their quadratic computational complexity. To cope with these issues, we propose a novel low-light remote sensing image enhancement network that combines multi-scale receptive fields with frequency-domain attention. Specifically, this network employs multiple parallel kernels of varying sizes to learn multi-scale local features in the spatial domain and complements frequency-domain information to learn global long-range correlations, which achieves local-global feature extraction and further facilitates subsequent degraded images enhancement. We have conducted extensive experiments to demonstrate that our network outperforms existing methods quantitatively and achieves exceptional visual performance, which fully highlights the effectiveness and superiority of our method in enhancing low-light remote sensing images.

关键词： Visualization Frequency-domain analysis Transforms Speech enhancement Feature extraction Transformers Image restoration Kernel Remote sensing Image enhancement

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international symposium on parallel and distributed processing and applications, ISPA 2003

International Symposium on Parallel and Distributed Processi...

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international symposium on parallel and distributed processing and applications, ISPA 2003

ISBN: (纸本)9783540376194

The proceedings contain 43 papers. The special focus in this conference is on applications on Web-Based, Intranet Systems, Optimization Techniques, Performance Evaluation of parallel Systems and Wireless Communication. The topics include: Localized algorithms and their applications in ad hoc wireless networks;towards a single system image for high-performance java;reliability of a distributed search engine for fresh information retrieval in large-scale intranet;a web-based graphical interface for general-purpose high-performance computing clusters;a compressed diagonals remapping technique for dynamic data redistribution on banded sparse matrix;scheduling parallel tasks onto NUMA multiprocessors with inter-processor communication overhead;an efficient algorithm for irregular redistributions in parallelizing compilers;balancing traffic in meshes by dynamic channel selection;an ad hoc on-demand routing protocol with alternate routes;design of a viable fault-tolerant routing strategy for optical-based grids;direct execution simulation of mobile agent algorithms;mpi-2 support in heterogeneous computing environment using an score cluster system;internet traffic congestion modelling and parallel distributed analysis;a comparative investigation into optimum-time synchronization protocols for a large scale of one-dimensional cellular automata;impact from mobile spam mail on mobile internet services;solving the set-splitting problem in sticker-based model and the Adleman-Lipton model;parallel MCGLS and ICGLS methods for least squares problems on distributed memory architectures;effective admission control for real-time anycast flow;a comprehensive software distributed shared memory system and a scheme of interactive data mining support system in parallel and distributed environment.

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HILP: Accounting for Workload-Level parallelism in System-on-Chip Design Space Exploration

HILP: Accounting for Workload-Level Parallelism in System-on...

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ieee symposium on High-Performance Computer Architecture

作者： Joseph Rogers Lieven Eeckhout Magnus Jahre Norwegian University of Science and Technology (NTNU) Ghent University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

High-performance System-on-Chip (SoC) architectures are becoming increasingly complex and heterogeneous, and the days when a single application could utilize all of an SoC’s hardware resources are all but over. The SoC’s workload, i.e., the set of independent applications that the SoC typically executes, therefore has a significant impact on its efficiency. Accounting for Workload-Level parallelism (WLP) in early-stage design space exploration is thus critical as later-stage analysis steps must focus on favorable design points to yield optimal results. Unfortunately, state-of-the-art MultiAmdahl and Gables fall short because they only model the extremes of minimal and maximal WLP. We hence propose HILP, the first early-stage design space exploration approach for heterogeneous SoCs that fully accounts for WLP. Our key observation is that scheduling a workload of independent multi-phase applications on a heterogeneous SoC is an instance of the classic job-shop scheduling optimization problem and thus can be solved using integer linear programming. HILP therefore uses a high-performance integer linear programming solver to find a near-optimal schedule that minimizes the overall execution time of the workload, i.e., it schedules the dependent phases of all applications in the workload on the cores and accelerators of the target SoC to maximize performance while respecting power consumption and memory bandwidth constraints. We validate HILP by demonstrating that it captures the performance effects of Amdahl’s law, the memory wall, and dark silicon, and then use it to explore the impact of WLP across a large SoC design space, yielding multiple insights. The key takeaway is that modeling WLP is necessary to ensure that more detailed, later-stage design tasks focus on the most favorable parts of the vast design space of heterogeneous SoCs.

关键词： Schedules Power demand Memory management parallel processing Integer linear programming Market research Silicon Space exploration System-on-chip Optimization

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FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption applications

FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully...

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ieee symposium on High-Performance Computer Architecture

作者： Yongmo Park Aporva Amarnath Subhankar Pal Karthik Swaminathan Alper Buyuktosunoglu Hayim Shaul Ehud Aharoni Nir Drucker Wei D. Lu Omri Soceanu Pradip Bose IBM T. J. Watson Research Center NY USA IBM Research Israel University of Michigan MI USA

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Fully homomorphic encryption (FHE) is a powerful cryptographic technique that enables computation on encrypted data without needing to decrypt it. It has broad applications in scenarios where sensitive data needs to be processed in the cloud or in other untrusted environments. FHE applications are both compute- and memory-intensive, owing to expensive operations on large data. While prior works address the challenges of efficient compute using dedicated hardware, expensive memory transfers still remain a major limiting factor. In this work, we propose a hierarchical near-DRAM processing (NDP) solution for FHE applications, called FHENDI, that harnesses the massive DRAM bank bandwidth. We observe various data access patterns in FHE that reveal distinct levels of parallelism: element-wise, limb-wise, coefficient-wise, and ciphertext-wise. FHENDI exploits these levels of parallelism to map FHE operations and data onto different hierarchies of our design, while addressing three major challenges with NDP for FHE: (i) the lack of bank-to-bank communication support, (ii) limited die-to-die bandwidth, and (iii) large memory access latencies. We resolve the first problem through a novel, conflict-free mapping algorithm built atop localized permutation networks that enables efficient element-wise and butterfly operations in FHE. The second problem is addressed by pipelining the execution of parallel bootstrap operations observed in compiled FHE workloads. Finally, we hide the memory access latency behind computation latency by exploiting a dual-banking scheme and subarray-level parallelism (SLP) of the DRAM banks. We evaluate FHENDI using representative workloads in the domains of privacy-preserving machine learning inference on CNNs and Transformers, database range query, and sorting, that are obtained using a compiler framework called HElayers. We compare FHENDI with a server-class CPU and GPU running the state-of-the-art HEaaN library, and an FHE accelerator ASIC, and repo

关键词： Memory management Random access memory Bandwidth Machine learning Transformers Libraries Cryptography Homomorphic encryption Sorting Pipeline processing

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Reuse-Aware Compilation for Zoned Quantum Architectures Based on Neutral Atoms

Reuse-Aware Compilation for Zoned Quantum Architectures Base...

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ieee symposium on High-Performance Computer Architecture

作者： Wan-Hsuan Lin Daniel Bochen Tan Jason Cong University of California Los Angeles Department of Physics Harvard University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Quantum computing architectures based on neutral atoms offer large scales and high-fidelity operations. They can be heterogeneous, with different zones for storage, entangling operations, and readout. Zoned architectures improve computation fidelity by shielding idling qubits in storage from side-effect noise, unlike monolithic architectures where all operations occur in a single zone. However, supporting these flexible architectures with efficient compilation remains challenging. In this paper, we propose ZAC, a scalable compiler for zoned architectures. ZAC minimizes data movement overhead between zones with qubit reuse, i.e., keeping them in the entanglement zone if an immediate entangling operation is pending. Other innovations include novel data placement and instruction scheduling strategies in ZAC, a flexible specification of zoned architectures, and an intermediate representation for zoned architectures, ZAIR. Our evaluation shows that zoned architectures equipped with ZAC achieve a 22x improvement in fidelity compared to monolithic architectures. Moreover, ZAC is shown to have a 10% fidelity gap on average compared to the ideal solution. This significant performance enhancement enables more efficient and reliable quantum circuit execution, enabling advancements in quantum algorithms and applications. ZAC is open source at https://***/UCLAVAST/ZAC

关键词： Technological innovation Quantum algorithm Program processors Scheduling algorithms Qubit Computer architecture Atoms parallel processing Integrated circuit reliability Quantum circuit

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