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ComPar: Optimized multi-compiler for Automatic OpenMP S2S Parallelization 16th

ComPar: Optimized Multi-compiler for Automatic OpenMP S2S Pa...

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16th international workshop on OpenMP (IWOMP)

作者： Mosseri, Idan Alon, Lee-Or Harel, Re'Em Oren, Gal Ben Gurion Univ Negev Dept Comp Sci POB 653 Beer Sheva Israel Nucl Res Ctr Negev Dept Phys POB 9001 Beer Sheva Israel Israel Atom Energy Commiss POB 7061 IL-61070 Tel Aviv Israel Bar Ilan Univ Dept Phys IL-52900 Ramat Gan Israel

ISBN: (纸本)9783030581442;9783030581435

Parallelization schemes are essential in order to exploit the full benefits of multi-core architectures, which have become widespread in recent years. In shared-memory architectures, the most comprehensive parallelization API is OpenMP. However, the introduction of correct and optimal OpenMP parallelization to applications is not always a simple task, due to common parallel shared-memory management pitfalls, architecture heterogeneity and the current necessity for human expertise in order to comprehend many fine details and abstract correlations. To ease this process, many automatic parallelization compilers were created over the last decade. [2] tested several source-to-source compilers and concluded that each has its advantages and disadvantages and no compiler is superior to all other compilers in all tests. This indicates that a fusion of the compilers' best outputs under the best hyper-parameters for the current hardware setups can yield greater speedups. To create such a fusion, one should execute a computationally intensive hyper-parameter sweep, in which the performance of each option is estimated and the best option is chosen. We created a novel parallelization sourceto-source multi-compiler named ComPar, which uses code segmentation-and-fusion with hyper-parameters tuning to achieve the best parallel code possible without any human intervention while maintaining the program's validity. In this paper we present ComPar and analyze its results on NAS and PolyBench benchmarks. We conclude that although the resources ComPar requires to produce parallel code are greater than other source-to-source parallelization compilers - as it depends on the number of parameters the user wishes to consider, and their combinations - ComPar achieves the best performance overall compared to the serial code version and other tested parallelization compilers. ComPar is publicly available at: https://***/Scientific-computing-LabNRCN/compar.

关键词： Application programming interfaces (API)

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Efficient Method for Mining High-Utility Itemsets Using High-Average Utility Measure 12th

Efficient Method for Mining High-Utility Itemsets Using High...

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12th international Conference on Computational Collective Intelligence (ICCCI)

作者： Nguyen, Loan T. T. Nguyen, Trinh D. D. Anh Nguyen Phuoc-Nghia Tran Cuong Trinh Bao Huynh Bay Vo Int Univ Sch Comp Sci & Engn Ho Chi Minh City Vietnam Vietnam Natl Univ Ho Chi Minh City Vietnam HCM Preuniv Sch Dept Informat Technol Ho Chi Minh City Vietnam Wroclaw Univ Sci & Technol Fac Comp Sci & Management Wroclaw Poland Bac Lieu Univ Bac Lieu Vietnam Ton Duc Thang Univ Fac Informat Technol Artificial Intelligence Lab Ho Chi Minh City Vietnam Ho Chi Minh City Univ Technol HUTECH Fac Informat Technol Ho Chi Minh City Vietnam

ISBN: (纸本)9783030630065;9783030630072

Mining high-utility itemsets (HUIs) based on high-average utility measure is an important task in the data mining field. However, many of the existing algorithms are performing the mining process sequentially and do not utilize the widely available multi-core processors, thus requiring long execution times. To address this issue, we propose an extended version of the HAUI-Miner algorithm, namely pHAUI-Miner. The algorithm applies multi-thread parallel processing to significantly reduce the mining time. Experimental evaluations on standard databases have shown the effectiveness of the proposed algorithm over the original and sequential method.

关键词： High-average utility itemset Data mining Parallel computing multi-thread

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A temporal dependency aware approach for scheduling real-time tasks on multi-core platforms 21

A temporal dependency aware approach for scheduling real-tim...

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21st ieee international Conference on High Performance computing and Communications, 17th ieee international Conference on Smart City and 5th ieee international Conference on Data Science and systems, HPCC/SmartCity/DSS 2019

作者： Han, Zijun Qu, Guangzhi Liu, Bo Zhang, Feng Oakland University 115 library drive Rochester MI48309 United States Beijing University of Technology China China University of Geosciences China

ISBN: (纸本)9781728120584

The growing demand for computing power in many sectors of industry calls for the utilization of multi-core processors. In order to take advantage of multi-core computing resources, efficient and effective multi-core task scheduling strategies are needed. Directed acyclic graphs (DAG) are commonly used to represent the task execution dependencies that any pair of tasks with dependencies need to be executed in the specified order. In this paper, we investigated and improved the DAGs based task model to consider the temporal property of data dependencies between tasks that the second task does not have to wait until the completion of the precedent task. Based on such a model, we proposed two scheduling strategies: static decomposed scheduling (SDS) and dynamic decomposed scheduling (DDS). The experimental results on both synthesized tasks and real industrial embedded programs show that SDS and DDS achieved good performance when compared with some of the state-of-the-art scheduling strategies. © 2019 ieee.

关键词： Scheduling

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multi-rate DAG Scheduling Considering Communication Contention for NoC-based Embedded many-core Processor 23

Multi-rate DAG Scheduling Considering Communication Contenti...

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23rd ieee/ACM international Symposium on Distributed Simulation and Real Time Applications (DS-RT)

作者： Igarashi, Shingo Kitagawa, Yuto Ishigooka, Tasuku Horiguchi, Tatsuya Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan Osaka Univ Grad Sch Engn Sci Osaka Japan Hitachi Ltd Ctr Technol Innovat Controls Res & Dev Grp Tokyo Japan

ISBN: (纸本)9781728129235

computing platforms for embedded systems are increasingly being transformed into multi/many-core platforms because embedded systems have become extensive, complex, and automated. In the case of an autonomous driving system, various applications are simultaneously running, and low power consumption and large-scale calculation are required. many-core processors with a multiple instruction, multiple data (MIMD) architecture can meet these requirements. This paper proposes a scheduling algorithm for an automotive driving system expressed in a directed acyclic graph (DAG) and we use Kalray MPPA-256 as the target many-core processor. On the basis of the architecture of Kalray MPPA-256, task processing that requires large-scale calculation and intercore communication is performed while avoiding communication contention by using a proposed grouping computational resource. In addition, we propose a scheduling method for a multi-rate DAG which is a DAG with multiple periods. This method generates a DAG task in a hyperperiod and schedules the DAG with dependency on tasks that have been released closely. The formulas for prioritization and processor selection are proposed for various generated tasks in a hyperperiod. Evaluation results show that the proposed algorithm is superior to existing DAG scheduling algorithms with regard to schedulability and deadline miss ratio.

关键词： multi-rate DAG many-core communication contention list-scheduling

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A STDM (Static Time Division multiplexing) switch on a multi-FPGA system 13

A STDM (Static Time Division Multiplexing) switch on a multi...

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ieee 13th international Symposium on Embedded multicore/many-core systems-on-Chip (MCSoC)

作者： Azegami, Keita Musha, Kazusa Hironaka, Kazuei Ben Ahmed, Akram Koibuch, Michihiro Hu, Yao Amano, Hideharu Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo Japan

ISBN: (纸本)9781728148823

FPGAs can be a promising accelerator used for MEC (multi-access Edge computing) which provides timing critical services for a number of terminals at the base stations near from edges. Although a high-end FPGA can support a fixed latency computation with a relatively small power consumption, they are expensive and the available acceleration circuits are limited into a size of single FPGA. FiC (Flow-in-Cloud) has been developed for building a virtual large FPGA from a number of middle-range economical FPGAs connected with high speed serial links. Although the current target of FiC is cloud computing, it is more suitable for the future MEC, because huge hardware resource can be supported with small cost. One of the problem to use such multi-FPGA systems for timing critical computation is network uncertainty. With a common packet switching, the computation speed is influenced with the network traffic. That is, the fixed latency computation which could be supported by a single FPGA is hard to be supported with multi-FPGA systems using common packet switching networks. In order to address this problem, we introduced STDM (Static Time Division multiplexing) switch in the FiC system. Since the STDM always supports a constant communication latency, transfer time can be estimated beforehand. Through the implementation of the STDM switch on the FPGA board for FiC, it appeared that the utilization ratio of the LUTs for the STDM switch is smaller than 14%. The required number of slots is less than 16 even for a system with 256 nodes. We implemented the Conjugate Gradient method, which includes all-to-all communication, on 4x2 FiC system. It achieved 17.9 times performance improvement of Intel E5-2667 2.90GHz CPU with 6 cores.

关键词： STDM multi-FPGA system FPGA-in-Cloud

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Parallelization planning for legacy programs: A multi-objective genetic algorithm approach 21

Parallelization planning for legacy programs: A multi-object...

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作者： Han, Zijun Qu, Guangzhi Liu, Bo Zhang, Feng Oakland University 115 library drive RochesterMI48309 United States Beijing University of Technology China China University of Geosciences China

ISBN: (纸本)9781728120584

Parallelization of legacy programs is on huge demand as multi-core platforms are pervasively adopted in many sectors of industry. In order to parallelize a legacy program, two steps must be done: parallelism discovery and parallelization planning. Parallelism discovery is the process of identifying code regions where have exploitable parallelism. And for parallelization planning, many aspects should be considered including but not limited to the speedup, core load balancing, communication costs, etc. In this work, we model the parallelization planning as a multi-objective optimization problem. A genetic algorithm is developed to solve this multi-objective optimization problem by evaluating the solution set taking consideration of all the above aspects. We have tested our approach on the real industrial applications to validate its feasibility and efficiency. © 2019 ieee.

关键词： multiobjective optimization

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A Cloud Based Super-Optimization Method to Parallelize the Sequential Code's Nested Loops 13

A Cloud Based Super-Optimization Method to Parallelize the S...

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ieee 13th international Symposium on Embedded multicore/many-core systems-on-Chip (MCSoC)

作者： Majd, Amin Loni, Mohammad Sahebi, Golnaz Daneshtalab, Masoud Troubitsyna, Elena Abo Akad Univ Dept Informat Technol Turku Finland Malardalen Univ Sch Innovat Design & Engn Vasteras Sweden KTH Royal Inst Technol Theoret Comp Sci Dept Stockholm Sweden

ISBN: (纸本)9781728148823

Advances in hardware architecture regarding multi-core processors make parallel computing ubiquitous. To achieve the maximum utilization of multi-core processors, parallel programming techniques are required. However, there are several challenges standing in front of parallel programming. These problems are mainly divided into three major groups. First, although recent advancements in parallel programming languages (e.g. MPI, OpenCL, etc.) assist developers, still parallel programming is not desirable for most programmers. The second one belongs to the massive volume of old software and applications, which have been written in serial mode. However, converting millions of line of serial codes to parallel codes is highly time-consuming and requiring huge verification effort. Third, the production of software and applications in parallel mode is very expensive since it needs knowledge and expertise. Super-optimization provided by super compilers is the process of automatically determine the dependent and independent instructions to find any data dependency and loop-free sequence of instructions. Super compiler then runs these instructions on different processors in the parallel mode, if it is possible. Super-optimization is a feasible solution for helping the programmer to get relaxed from parallel programming workload. Since the most complexity of the sequential codes is in the nested loops, we try to parallelize the nested loops by using the idea of super-optimization. One of the underlying stages in the super-optimization is scheduling tiled space for iterating nested loops. Since the problem is NP-Hard, using the traditional optimization methods are not feasible. In this paper, we propose a cloud-based super-optimization method as Software-as-a-Service (SaaS) to reduce the cost of parallel programming. In addition, it increases the utilization of the processing capacity of the multi-core processor. As the result, an intermediate programmer can use the whole process

关键词： Parallel Programming Cloud computing Super Compiler Speedup Diophantine Algorithm

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Heuristic Contention-Free Scheduling Algorithm for multi-core Processor using LET Model

Heuristic Contention-Free Scheduling Algorithm for Multi-cor...

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international workshop/Symposium on Distributed Simulation and Real-Time Applications (DS-RT)

作者： Shingo Igarashi Tasuku Ishigooka Tatsuya Horiguchi Ryotaro Koike Takuya Azumi Graduate School of Science and Engineering Saitama University Center for Technology Innovation - Controls Research and Development Group Hitachi Ltd.

ISBN: (数字)9781728173436

ISBN: (纸本)9781728173443

Embedded systems, e.g., self-driving systems and advanced driver-assistance systems (ADAS), require computing platforms with high computing power and low power consumption. multi-/many-core platforms satisfy these requirements effectively. However, for hard real-time applications, multiple demands on shared resources can impede real-time performance, and memory is one resource that can impair the desired performance significantly. Therefore, it is important that memory access timing be deterministic to facilitate predictability. To realize this, the Logical Execution Time (LET) paradigm is currently attracting attention. This paper proposes a theoretical scheduling method for a model applying the LET paradigm to directed acyclic graph (DAG) nodes for a multi-/many-core platform. The proposed method considers communication timing between nodes and generates a schedule that does not cause communication contentions. In addition, the proposed method attempts to distribute tasks and reduce LET intervals to address increased execution times due to the implementation of the LET paradigm. In the evaluation, we observed that the proposed method improved the schedule length by up to 40%.

关键词： Task analysis Integrated circuits Computational modeling Timing Schedules Memory management Data models

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Towards Heterogeneous computing Platforms for Autonomous Driving

Towards Heterogeneous Computing Platforms for Autonomous Dri...

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ieee international Conference on Embedded Software and systems (ICESS)

作者： Chishiro, Hiroyuki Suito, Kazutoshi Ito, Tsutomu Maeda, Seiya Azumi, Takuya Funaoka, Kenji Kato, Shinpei Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan Axell Corp Tokyo Japan Saitama Univ Grad Sch Sci & Engn Saitama Japan Tier IV Inc Tokyo Japan

ISBN: (纸本)9781728124377

This paper introduces a new project: Research and Development of System on a Chip and Software Platforms for Autonomous Driving, started in April 2019. State-of-the-art high-end embedded platforms have trade-offs between general-purpose processing and power consumption. In order to solve the trade-offs, this project develops heterogeneous computing platforms for autonomous driving. In particular, the heterogeneous computing platforms have a heterogeneous System on a Chip (SoC), which consists of Accelerated Processing Units for AI and robotic algorithms, multi-core CPUs for general-purpose processing, and many-core CPUs for real-time processing. This project also develops software platforms including compilers, operating systems, middleware, and applications for the heterogeneous SoC. The authors believe that this project contributes to early realize autonomous driving.

关键词： Autonomous Driving Autoware ROS Middle-ware Compiler Operating System System on a Chip

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Enabling Adaptive Intelligence in Cloud-augmented multiple Robots systems 13

Enabling Adaptive Intelligence in Cloud-augmented Multiple R...

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13th ieee international Conference on Service-Oriented System Engineering (SOSE) / 10th international workshop on Joint Cloud computing (JCC) / ieee international workshop on Cloud computing in Robotic systems (CCRS)

作者： Zhang, Shigeng Li, Yinggang Liu, Bo Fu, Shupo Liu, Xuan Cent South Univ Sch Comp Sci & Engn Changsha Hunan Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Changsha Hunan Peoples R China Nanjing Univ State Key Lab Novel Software Technol Nanjing Jiangsu Peoples R China

ISBN: (数字)9781728114422

ISBN: (纸本)9781728114422

multiple robot systems (MRSs) have been widely used in both military and civil applications. In recent years, machine learning approaches, especially deep learning, have been adopted to enhance the ability of MRSs in many scenarios, such as path planning, cooperative inference, and situation awareness. However, the robot individuals are usually severely limited in resources and they cannot afford the high computation requirements of deep learning approaches. Cloud-augmented multiple robot systems try to solve this problem by performing heavily computational tasks on the central cloud and performing only simple tasks on the robots. In this strategy, the robots need to transmit their collected data to the cloud, which might cause very long transmission latency and thus are not be suitable for many critical applications that have stringent requirements on response delay. The recently emerging cooperative deep inference can be a potential solution to enabling adaptive intelligence in cloud-augmented MRSs. Rather than transmitting all the data to the cloud and executing all computational tasks on the cloud, cooperative deep inference adaptively determines whether to perform some tasks on the robot before sending the data to the cloud, aiming to reduce the volume of data to be transmitted and reduce the latency. Moreover, the robot can adaptively determine which part of the task should be executed on the robot and which part should be executed on the cloud to optimize the time or energy efficiency subject to some task specific requirements. In this paper, we overview the recent progresses in cooperative deep inference and propose a framework that enables adaptive intelligence in cloud-augmented MRSs. We then demonstrate with a target detection scenario that the proposed framework can effectively reduce response latency.

关键词： multi-robot systems cloud robotics edge computing deep learning edge intelligence

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