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Towards Heterogeneous computing Platforms for Autonomous Driving

Towards Heterogeneous Computing Platforms for Autonomous Dri...

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ieee international Conference on Embedded Software and systems (ICESS)

作者： Chishiro, Hiroyuki Suito, Kazutoshi Ito, Tsutomu Maeda, Seiya Azumi, Takuya Funaoka, Kenji Kato, Shinpei Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan Axell Corp Tokyo Japan Saitama Univ Grad Sch Sci & Engn Saitama Japan Tier IV Inc Tokyo Japan

ISBN: (纸本)9781728124377

This paper introduces a new project: Research and Development of System on a Chip and Software Platforms for Autonomous Driving, started in April 2019. State-of-the-art high-end embedded platforms have trade-offs between general-purpose processing and power consumption. In order to solve the trade-offs, this project develops heterogeneous computing platforms for autonomous driving. In particular, the heterogeneous computing platforms have a heterogeneous System on a Chip (SoC), which consists of Accelerated Processing Units for AI and robotic algorithms, multi-core CPUs for general-purpose processing, and many-core CPUs for real-time processing. This project also develops software platforms including compilers, operating systems, middleware, and applications for the heterogeneous SoC. The authors believe that this project contributes to early realize autonomous driving.

关键词： Autonomous Driving Autoware ROS Middle-ware Compiler Operating System System on a Chip

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Enabling Adaptive Intelligence in Cloud-augmented multiple Robots systems 13

Enabling Adaptive Intelligence in Cloud-augmented Multiple R...

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13th ieee international Conference on Service-Oriented System Engineering (SOSE) / 10th international workshop on Joint Cloud computing (JCC) / ieee international workshop on Cloud computing in Robotic systems (CCRS)

作者： Zhang, Shigeng Li, Yinggang Liu, Bo Fu, Shupo Liu, Xuan Cent South Univ Sch Comp Sci & Engn Changsha Hunan Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Changsha Hunan Peoples R China Nanjing Univ State Key Lab Novel Software Technol Nanjing Jiangsu Peoples R China

ISBN: (数字)9781728114422

ISBN: (纸本)9781728114422

multiple robot systems (MRSs) have been widely used in both military and civil applications. In recent years, machine learning approaches, especially deep learning, have been adopted to enhance the ability of MRSs in many scenarios, such as path planning, cooperative inference, and situation awareness. However, the robot individuals are usually severely limited in resources and they cannot afford the high computation requirements of deep learning approaches. Cloud-augmented multiple robot systems try to solve this problem by performing heavily computational tasks on the central cloud and performing only simple tasks on the robots. In this strategy, the robots need to transmit their collected data to the cloud, which might cause very long transmission latency and thus are not be suitable for many critical applications that have stringent requirements on response delay. The recently emerging cooperative deep inference can be a potential solution to enabling adaptive intelligence in cloud-augmented MRSs. Rather than transmitting all the data to the cloud and executing all computational tasks on the cloud, cooperative deep inference adaptively determines whether to perform some tasks on the robot before sending the data to the cloud, aiming to reduce the volume of data to be transmitted and reduce the latency. Moreover, the robot can adaptively determine which part of the task should be executed on the robot and which part should be executed on the cloud to optimize the time or energy efficiency subject to some task specific requirements. In this paper, we overview the recent progresses in cooperative deep inference and propose a framework that enables adaptive intelligence in cloud-augmented MRSs. We then demonstrate with a target detection scenario that the proposed framework can effectively reduce response latency.

关键词： multi-robot systems cloud robotics edge computing deep learning edge intelligence

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Introducing multi-level parallelism, at coarse, fine and instruction level to enhance the performance of iterative solvers for large sparse linear systems on multi- and many-core architecture

Introducing multi-level parallelism, at coarse, fine and ins...

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LLVM Compiler Infrastructure in HPC (LLVM-HPC)

作者： Jean-Marc Gratien IFP Energies Nouvelles Rueil Malmaison France

ISBN: (数字)9780738110424

ISBN: (纸本)9781665422642

With the evolution of High Performance computing, multi-core and many-core systems are now a common feature of new hardware architectures. The introduction of very large number of cores at the processor level is challenging because it requires to handle multi level parallelism at various levels either coarse or fine to fully take advantage of the offered computing power. The induced programming effort can be fixed with parallel programming models based on the data flow model and the task programming paradigm [1]. To do so many of the standard numerical algorithms must be revisited as they cannot be easily parallelized at the finest levels. Iterative linear solvers are a key part of petroleum reservoir simulation as they can represent up to 80% of the total computing time. In these algorithms, the standard preconditioning methods for large, sparse and unstructured matrices - such as Incomplete LU Factorization (ILU) or Algebraic multigrid (AMG) - fail to scale on shared-memory architectures with large number of cores. In this paper we reconsider preconditioning algorithms to better introduce multi-level parallelism at both coarse level with MPI, fine level with threads and at the instruction level to enable SIMD optimizations. This paper illustrates how we enhance the implementation of preconditioners like the multilevel domain decomposition (DDML) preconditioners [2], based on the popular Additive Schwartz Method (ASM), or the classical ILU0 preconditioner with the fine grained parallel fixed point variant presented in [3]. Our approach is validated on linear systems extracted from realistic petroleum reservoir simulations. The robustness of the preconditioners is tested with respect to the data heterogeneities of the study cases. We evaluate the extensibility of our implementation regarding the model sizes and its scalability regarding the large number of cores provided by new KNL processors or multi-nodes clusters.

关键词： Task analysis Parallel processing Data models Computational modeling Runtime Computer architecture Scheduling

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RTL Test Generation on multi-core and many-core Architectures 32

RTL Test Generation on Multi-Core and Many-Core Architecture...

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32nd international Conference on VLSI Design (VLSID) / 18th international Conference on Embedded systems (ES)

作者： Varadarajan, Aravind Krishnan Hsiao, Michael S. Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9781728104096

Design Verification of complex circuits has become an increasingly time-consuming process. The advent of parallel computing using General Purpose Graphics Processing Units (GPGPUs) has led to enhanced performance for various applications. We propose to leverage both the multi-core CPU and the GPGPU for RTL test generation. This is achieved by implementing a test generation framework that can utilize the SIMD type parallelism available in GPGPUs and task level parallelism available on CPUs. Not all applications can be made parallel due to complex dependencies, making parallelism non-trivial. Besides, large memory bandwidth requirements can become a bottleneck hindering potential speedups. In this paper, we have ported an RTL branch coverage based test generation framework to work within the constraints of a GPGPU environment. Experimental results show that considerable speedup can be achieved for test generation without loss of coverage.

关键词： Graphics processing units Test pattern generators Parallel processing Integrated circuit modeling Instruction sets Kernel Synchronization

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Efficient parallel sort on AVX-512-based multi-core and many-core architectures 21

Efficient parallel sort on AVX-512-based multi-core and many...

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21st ieee international Conference on High Performance computing and Communications, 17th ieee international Conference on Smart City and 5th ieee international Conference on Data Science and systems, HPCC/SmartCity/DSS 2019

作者： Yin, Zekun Zhang, Tianyu Muller, Andre Liu, Hui Wei, Yanjie Schmidt, Bertil Liu, Weiguo School of Software Shandong University Jinan China Shenzhen Research Institute Shandong University China Institute for Computer Science Johannes Gutenberg University Mainz Germany Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Shenzhen China National Supercomputing Center in Wuxi Wuxi China

ISBN: (纸本)9781728120584

Sorting kernels are a fundamental part of numerous applications. The performance of sorting implementations is usually limited by a variety of factors such as computing power, memory bandwidth, and branch mispredictions. In this paper we propose an efficient hybrid sorting method which takes advantage of wide vector registers and the high bandwidth memory of modern AVX-512-based multi-core and many-core processors. Our approach employs a combination of vectorized bitonic sorting and load-balanced multi-threaded merging. Thread-level and data-level parallelism are used to exploit both compute power and memory bandwidth. Our single-threaded implementation is ~30x faster than qsort in the C standard library and ~10x faster than C++'s std::sort. Compared with the Intel Performance Primitives (IPP) library which is one of the most efficient CPU-based radix sort implementation, we obtain a speedup of 1.3 to 2.6. Furthermore, we achieve a peak performance of sorting 1.14 billion floats per second on a Xeon Phi 7210 processor. Moreover, we show the extensibility of our vectorized kernels to processing units with a varying of vector lanes. © 2019 ieee.

关键词： Sorting

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Accelerating Computer Vision Algorithms on Heterogeneous Edge computing Platforms

Accelerating Computer Vision Algorithms on Heterogeneous Edg...

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ieee workshop on Signal Processing systems (SIPS)

作者： Alok Prakash Nirmala Ramakrishnan Kratika Garg Thambipillai Srikanthan Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781728180991

Heterogeneity has become the cornerstone of modern embedded System-on-Chips (SoCs), used in latest smart-phones and edge computing platforms to achieve high performance under tight power budgets. Alongside the general purpose multi-core CPUs, such SoCs typically integrate several specialized processing elements such as GPU and DSP to ensure power-efficient execution of specific workloads. In the past, many computer vision algorithms and their kernels have been shown to benefit from execution on GPUs, both in terms of performance and power consumption. Existing work has also demonstrated the benefit of accelerating them simultaneously on multi-core CPUs and discrete as well as integrated GPUs found in PCs and workstations. Recently, authors have also focused on accelerating such applications on heterogeneous embedded SoCs with integrated CPU and GPU. In this paper, we first present an extensive literature review of such efforts and highlight their strengths and limitations. Next, we use the latest state-of-the-art edge computing platform, Odroid-N2, and the older Odroid-XU3 platform, both of which use heterogeneous embedded SoCs, to explore the acceleration of the convolution kernel with different filter sizes and its impact on the KLT tracking algorithm. Lastly, we discuss the challenges and opportunities in leveraging such SoCs for computer vision and other AI applications.

关键词： Graphics processing units Convolution Kernel Task analysis Acceleration Partitioning algorithms Computer vision

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Cache Oblivious Strategies to Exploit multi-Level Memory on manycore systems

Cache Oblivious Strategies to Exploit Multi-Level Memory on ...

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ieee/ACM workshop on Memory Centric High Performance computing (MCHPC)

作者： Neil A. Butcher Stephen L. Olivier Peter M. Kogge Univ. of Notre Dame Notre Dame IN USA Center for Computing Research Sandia National Laboratories Albuquerque NM USA

ISBN: (数字)9781665422789

ISBN: (纸本)9781665422796

many-core systems are beginning to feature novel large, high-bandwidth intermediate memory as a visible part of the memory hierarchy. This paper discusses how to make use of intermediate memory when composing matrix multiply with transpose to compute A * AT. We re-purpose the cache-oblivious approach developed by Frigo et al. and apply it to the composition of a bandwidth-bound kernel (transpose) with a compute-bound kernel (matrix multiply). Particular focus is on regions of matrix shapes far from square that are not usually considered. Our codes are simpler than optimized codes, but reasonably close in performance. Also, perhaps of more importance is developing a paradigm for how to construct other codes using intermediate memories.

关键词： Instruction sets Bandwidth Memory management Synchronization Shape Hardware Measurement

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Creating Stable Productive CSE Software Development and Integration Processes in Unstable Environments on the Path to Exascale 14

Creating Stable Productive CSE Software Development and Inte...

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14th ieee/ACM international workshop on Software Engineering for Science (SE4Science)

作者： Bartlett, Roscoe A. Frye, Joseph R. Sandia Natl Labs Dept Software Engn & Res Livermore CA 94550 USA

ISBN: (纸本)9781728122762

The Sandia National Laboratories (SNL) Advanced Technology Development and Mitigation (ATDM) project focuses on R&D for exascale computational science and engineering (CSE) software. Exascale application (APP) codes are co-developed and integrated with a large number of 2nd generation Trilinos packages built on top of Kokkos for achieving portable performance. These efforts are challenged by needing to develop and test on many unstable and constantly changing pre-exascale platforms using immature compilers and other system software. Challenges, experiences, and lessons learned are presented for creating stable development and integration workflows for these types of difficult projects. In particular, we describe automated workflows, testing, and integration processes as well as new tools and multi-team collaboration processes for effectively keeping a large number of automated builds and tests working on these unstable platforms.

关键词： software engineering software testing testing techniques exascale systems software libraries scientific computing high performance computing

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On-Demand Urgent High Performance computing Utilizing the Google Cloud Platform 1

On-Demand Urgent High Performance Computing Utilizing the Go...

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1st ieee/ACM international workshop on HPC for Urgent Decision Making (UrgentHPC)

作者： Posey, Brandon Deer, Adam Gorman, Wyatt July, Vanessa Kanhere, Neeraj Speck, Dan Wilson, Boyd Apon, Amy Clemson University United States Google TrafficVision Burwood Group United States

ISBN: (纸本)9781728159959

In this paper we describe how high performance computing in the Google Cloud Platform can be utilized in an urgent and emergency situation to process large amounts of traffic data efficiently and on demand. Our approach provides a solution to an urgent need for disaster management using massive data processing and high performance computing. The traffic data used in this demonstration is collected from the public camera systems on Interstate highways in the Southeast United States. Our solution launches a parallel processing system that is the size of a Top 5 supercomputer using the Google Cloud Platform. Results show that the parallel processing system can be launched in a few hours, that it is effective at fast processing of high volume data, and can be de-provisioned in a few hours. We processed 211TB of video utilizing 6,227,593 core hours over the span of about eight hours with an average cost of around $0.008 per vCPU hour, which is less than the cost of many on-premise HPC systems.

关键词： HPC in the commercial cloud Google Cloud Platform disaster management massive data processing traffic management

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Empirical Analysis of the I/O Characteristics of a Highly Integrated many-core Processor

Empirical Analysis of the I/O Characteristics of a Highly In...

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Autonomic computing and Self-Organizing systems Companion (ACSOS-C), ieee international Conference on

作者： Cheongjun Lee Jaehwan Lee Donghun Koo Chungyong Kim Jiwoo Bang Eun-Kyu Byun Hyeonsang Eom Department of Electronics and Information Engineering Korea Aerospace University Goyang-si Korea Department of Computer Science and Engineering Seoul National University Seoul Korea Division of National Supercomputing Korea Institute of Science and Technology Information Daejeon Korea

ISBN: (数字)9781728184142

ISBN: (纸本)9781728184159

Optimized for parallel operations, Intel's second-generation Xeon Phi processor, code-named Knights Landing (KNL), is actively utilized in high performance computing systems based on its highly integrated cores and high-bandwidth on-package memory, multi-Channel DRAM (MCDRAM). Recently, the emergence of data-intensive applications and the utilization of many-core processors have further increased the I/O performance requirements of high performance computing systems. Therefore, it is necessary to understand and analyze the I/O characteristics of many integrated core systems. In this paper, we experimentally analyze the I/O characteristics of KNL, focusing on single-thread, buffered-write operations. We determine that KNL has a bottleneck in its buffered write operation that utilizes page cache. To find this bottleneck point and identify its cause, we conduct the experiments in two different ways. First, we measure the execution time of the kernel functions through the kernel I/O path. Second, we measure the occurrence count of system events such as cache-misses and branch-misses. With results from the experiments, we discuss the characteristics on KNL's I/O performance involving the performance bottlenecks.

关键词： Kernel Linux Time measurement Random access memory Instruction sets High performance computing Parallel processing

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