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OpenMP4.5-enabled large-scale heterogeneous Lattice Boltzmann multiphase flow simulations 17

OpenMP4.5-enabled large-scale heterogeneous Lattice Boltzman...

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ieee Int Conf on Parallel and Distributed Processing with Applications, Big Data and Cloud computing, Sustainable computing and Communications, Social computing and Networking (ISPA/BDCloud/SocialCom/SustainCom)

作者： Xu, Chuanfu Wang, Xi Che, Yonggang Wang, Zhenghua Li, Dali Natl Univ Def Technol Coll Comp Changsha Peoples R China Natl Univ Def Technol Coll Aeronaut & Astronaut Changsha Peoples R China

ISBN: (纸本)9781728143286

Modern heterogeneous high-end computing systems featuring many-core co-processors/accelerators pose tough challenges to parallelize and optimize real-world scientific codes. In this paper, we demonstrate highly scalable 3D Lattice Boltzmann multiphase flow simulations on the heterogeneous Tianhe-2 supercomputer using MPI+OpenMP+SIMD. We highlight the use of the OpenMP4.5 accelerator programming model to collaborate CPUs and Intel many Integrated cores (MIC) co-processors, and present a range of optimizations to exploit hierarchical parallelism on the heterogeneous architecture. With SIMD-friendly data structures, computation reordering, cache blocking and auto-vectorization, we dramatically optimize the single-thread performance for typical LBM computational kernels on a CPU and MIC core. After implementation of shared-memory OpenMP threading, we further improve the OpenMP performance by enabling huge paging and OpenMP collapse clause on the thread-rich MIC architecture. To enhance the collaborative efficiency among intra-node CPUs and co-processors, we propose a flexible load balance model with heterogeneous domain decomposition for CPU-MIC task allocation, as well as asynchronous offloading to overlap operations of CPUs and multiple MICs. We effectively overlap all levels of CPU-MIC computation/communication and minimize the cost of halo exchanges as far as possible in large-scale scenario. 3D liquid and gases multi-phase cases simulating drop impact with gravity effect using D3Q19 Lattice Boltzmann discretization and Shan-Chen BGK collision model are presented, achieving a weak parallel efficiency of above 80% in going from 128 to 2048 compute nodes.

关键词： heterogeneous parallel computing lattice Boltzmann methods many-core processor OpenMP4.5 accelerator programming model

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Simulating Heterogeneous Models on multi-core Platforms using Julia's computing Language Parallel Potential

Simulating Heterogeneous Models on Multi-Core Platforms usin...

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international workshop/Symposium on Distributed Simulation and Real-Time Applications (DS-RT)

作者： Sergey Suslov Michael Schiek Markus Robens Christian Grewing Stefan van Waasen ZEA-2 - Electronic Systems Research Center Jülich Germany

ISBN: (数字)9781728173436

ISBN: (纸本)9781728173443

This paper addresses the questions of high-level system modelling using heterogeneous multi-tool modelling environment on parallel multi-core processing systems for simulation acceleration. The modelling technique has been applied for high-level validation of a high-precision Indoor Positioning System for Motion Analysis (IPS-MA) developed in the Central Institute Electronic systems (ZEA-2) of the Research Center Juelich GmbH. The heterogeneous modelling environment has been built using an implementation-level model designed in Matlab Simulink, a verification model for describing the system environment using Modelica language, and Julia language for automatic generation of binding modelling environment and parallelizing the simulation of the overall model. The approach showed a good flexibility in system description and verification in the multi-instrument modelling environment and a good performance gain due to simulation parallelism.

关键词： Handheld computers Computational modeling Software packages Patents Sensors

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A many-core Accelerator Design for On-Chip Deep Reinforcement Learning

A Many-Core Accelerator Design for On-Chip Deep Reinforcemen...

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ieee international Conference on Computer-Aided Design

作者： Ying Wang Mengdi Wang Bing Li Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing P.R. China Capital Normal University Beijing P.R. China

ISBN: (数字)9781665423243

Deep Reinforcement Learning (DRL) is substantially resource-consuming, and it requires large-scale distributed computing-nodes to learn complicated tasks, like video-game and Go play. This work attempts to down-scale a distributed DRL system into a specialized many-core chip and achieve energy-efficient on-chip DRL. With the customized Network-on-Chip that handles the communication of on-chip data and control-signals, we proposed a Synchronous Asynchronous RL Architecture (SARLA) and the according many-core chip that completely avoids the unnecessary data duplication and synchronization activities in multi-node RL systems. In evaluation, the SARLA system achieves considerable energy-efficiency boost over the GPU-based implementations for typical DRL workloads built with OpenAI-gym.

关键词： System-on-chip Computer architecture Reinforcement learning Neural networks Servers Parallel processing Training

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multi-rate DAG scheduling considering communication contention for NoC-based embedded many-core processor 19

Multi-rate DAG scheduling considering communication contenti...

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Proceedings of the 23rd ieee/ACM international Symposium on Distributed Simulation and Real Time Applications

作者： Shingo Igarashi Yuto Kitagawa Tasuku Ishigooka Tatsuya Horiguchi Takuya Azumi Saitama University Osaka University Hitachi Ltd Research and Development Group Hitachi Ltd

ISBN: (纸本)9781728129235

computing platforms for embedded systems are increasingly being transformed into multi/many-core platforms because embedded systems have become extensive, complex, and automated. In the case of an autonomous driving system, various applications are simultaneously running, and low power consumption and large-scale calculation are required. many-core processors with a multiple instruction, multiple data (MIMD) architecture can meet these requirements. This paper proposes a scheduling algorithm for an automotive driving system expressed in a directed acyclic graph (DAG) and we use Kalray MPPA-256 as the target many-core processor. On the basis of the architecture of Kalray MPPA-256, task processing that requires large-scale calculation and intercore communication is performed while avoiding communication contention by using a proposed grouping computational resource. In addition, we propose a scheduling method for a multi-rate DAG which is a DAG with multiple periods. This method generates a DAG task in a hyperperiod and schedules the DAG with dependency on tasks that have been released closely. The formulas for prioritization and processor selection are proposed for various generated tasks in a hyperperiod. Evaluation results show that the proposed algorithm is superior to existing DAG scheduling algorithms with regard to schedulability and deadline miss ratio.

关键词： many-core list-scheduling multi-rate DAG communication contention

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Neural-Network Optimized 1-bit Precoding for Massive MU-MIMO 20

Neural-Network Optimized 1-bit Precoding for Massive MU-MIMO

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20th ieee international workshop on Signal Processing Advances in Wireless Communications (SPAWC)

作者： Balatsoukas-Stimming, Alexios Castaneda, Oscar Jacobsson, Sven Durisi, Giuseppe Studer, Christoph Ecole Polytech Fed Lausanne Telecommun Circuits Lab Lausanne Switzerland Cornell Univ Sch Elect & Comp Engn Ithaca NY 14850 USA Ericsson Res Gothenburg Sweden Chalmers Univ Technol Gothenburg Sweden

ISBN: (纸本)9781538665282

Base station (BS) architectures for massive multi-user (MU) multiple-input multiple-output (MIMO) wireless systems are equipped with hundreds of antennas to serve tens of users on the same time-frequency channel. The immense number of BS antennas incurs high system costs, power, and interconnect bandwidth. To circumvent these obstacles, sophisticated MU precoding algorithms that enable the use of 1-bit DACs have been proposed. many of these precoders feature parameters that are, traditionally, tuned manually to optimize their performance. We propose to use deep-learning tools to automatically tune such 1-bit precoders. Specifically, we optimize the biConvex 1-bit PrecOding (C2PO) algorithm using neural networks. Compared to the original C2PO algorithm, our neural-network optimized (NNO-)C2PO achieves the same error-rate performance at 2x lower complexity. Moreover, by training NNO-C2PO for different channel models, we show that 1-bit precoding can be made robust to vastly changing propagation conditions.

关键词： analogue-digital conversion antenna arrays convex programming learning (artificial intelligence) MIMO communication neural nets precoding telecommunication computing prediction coding Neural network Analog-digital conversion telecommunication computing MIMO communication convex programming Antenna arrays 1-bit ANTENNA

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multi-threading Semantics for Highly Heterogeneous systems Using Mobile Threads

Multi-threading Semantics for Highly Heterogeneous Systems U...

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2019 international Conference on High Performance computing and Simulation, HPCS 2019

作者： Kogge, Peter M. Univ. of Notre Dame Dept. of Computer Sciene and Engr. Notre DameIN United States

ISBN: (纸本)9781728144849

Heterogeneous architectures are becoming the norm. The results are nodes that are not only multi-threaded, but simultaneously multi-threaded across several different instruction sets and core designs. Unfortunately, programming models for such systems are still evolving, and are nowhere near adequate as we move into an era of extreme heterogeneity with many new accelerator designs. This paper discusses the current range of multi-threading models and what features are liable to be needed for such future architectures. In addition, we suggest the potential value of using a new threading model, termed migrating threads, that may be an excellent match for a common 'glue' to efficiently combine all the emerging heterogeneity. © 2019 ieee.

关键词： Semantics

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Generalized Cost-Aware Cloudlet Placement for Vehicular Edge computing systems 11

Generalized Cost-Aware Cloudlet Placement for Vehicular Edge...

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11th ieee Int Conf on Cloud Comp Technol and Sci (CloudCom) / 19th ieee Int Conf Comp and Informat Technol (CIT) / 2019 Int workshop on Resource Brokering with Blockchain (RBchain) / Asia-Pacific Serv Comp Conf (APSCC)

作者： Bhatta, Dixit Mashayekhy, Lena Univ Delaware Dept Comp & Informat Sci Newark DE 19716 USA

ISBN: (纸本)9781728150116

One of the well-known challenges in Edge computing is strategic placement of cloudlets. The fundamental goals of this challenge are to minimize the deployment cost of cloudlets and to guarantee minimum latency for users of edge services. However, building cloudlet infrastructure may not be feasible in many situations and areas (e.g., disaster situations, unexpected surge in demand, and remote rural areas). Vehicular edge computing, VEC, introduces mobile cloudlets to augment edge computing capacity, enhance its coverage, and reduce latency significantly. However, efficient cloudlet placement is even more critical in VEC as it is not a long-term decision and needs to be repeated over time. In this paper, we address this challenge by designing a generalized cost-aware cloudlet placement approach that places a set of heterogeneous cloudlets in a region and fully maps user applications to appropriate cloudlets while ensuring their latency requirements. We first formulate the problem as a multi-objective integer programming model in a general deployment scenario. This is a computationally NP-hard problem. To tackle its intractability, we then propose a genetic algorithm-based approach, GACP. We investigate the effectiveness of GACP by performing extensive experiments on multiple deployment scenarios based on New York City OpenData. The results show that GACP obtains close to optimal cost placement in significantly reduced time.

关键词： edge computing mobile cloudlets optimization genetic algorithm

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AI on the Edge: Characterizing AI-based IoT Applications Using Specialized Edge Architectures

AI on the Edge: Characterizing AI-based IoT Applications Usi...

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ieee international workshop/Symposium on Workload Characterization

作者： Qianlin Liang Prashant Shenoy David Irwin University of Massachusetts Amherst Amherst U.S.A

ISBN: (数字)9781728176451

ISBN: (纸本)9781728176468

Edge computing has emerged as a popular paradigm for supporting mobile and IoT applications with low latency or high bandwidth needs. The attractiveness of edge computing has been further enhanced due to the recent availability of special-purpose hardware to accelerate specific compute tasks, such as deep learning inference, on edge nodes. In this paper, we experimentally compare the benefits and limitations of using specialized edge systems, built using edge accelerators, to more traditional forms of edge and cloud computing. Our experimental study using edge-based AI workloads shows that today's edge accelerators can provide comparable, and in many cases better, performance, when normalized for power or cost, than traditional edge and cloud servers. They also provide latency and bandwidth benefits for split processing, across and within tiers, when using model compression or model splitting, but require dynamic methods to determine the optimal split across tiers. We find that edge accelerators can support varying degrees of concurrency for multi-tenant inference applications, but lack isolation mechanisms necessary for edge cloud multi-tenant hosting.

关键词： Cloud computing Image edge detection Internet of Things Hardware Servers Graphics processing units Edge computing

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Performance Optimization and Scalability Analysis of the MGB Hydrological Model

Performance Optimization and Scalability Analysis of the MGB...

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international Conference on High Performance computing

作者： Henrique R. A. Freitas Celso L. Mendes Aleksandar Ilic Graduate Program in Applied Computing National Institute for Space Research São José dos Campos Brazil Associate Laboratory of Computing National Institute for Space Research São José dos Campos Brazil INESC-ID Instituto Superior Técnico University of Lisbon Lisbon Portugal

Hydrological models are extensively used in applications such as water resources, climate change, land use, and forecast systems. The focus of this paper is performance optimization of the MGB hydrological model, which is widely employed to simulate water flows in large-scale watersheds. The optimization strategies that we selected include AVX-512 vectorization, thread-parallelism on multi-core CPUs (OpenMP), and data-parallelism on many-core GPUs (CUDA). We conducted experiments for real-world input datasets on state-of-the-art HPC systems based on Intel's Skylake CPUs and NVIDIA GPUs. In addition, a Roofline model characterization for these datasets confirmed performance improvements of up to 37.5x on the most time-consuming part of the code and 8.6x on the full MGB model. The work proposed herein shows that careful optimizations are needed for hydrological models to achieve a significant fraction of the performance potential in modern processors.

关键词： Analytical models Computational modeling Scalability High performance computing Conferences Graphics processing units Predictive models

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Adaptive hybrid transaction processing with hardware transaction memory 21

Adaptive hybrid transaction processing with hardware transac...

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21st ieee international Conference on High Performance computing and Communications, 17th ieee international Conference on Smart City and 5th ieee international Conference on Data Science and systems, HPCC/SmartCity/DSS 2019

作者： He, Tao Li, Jianxin Beijing Advanced Innovation Center for Big Data and Brain Computing Beihang University Beijing China SKLSDE Lab Beihang University Beijing China

ISBN: (纸本)9781728120584

many performance-sensitive software systems gain benefit from the availability of advanced hardware features, and many research works have been transited to engineering reality. For instance, restricted hardware transaction memory (HTM), a hardware feature providing hardware atomicity and isolation guarantees for transactional execution, has gained much attention in the community of database system and becomes a new kind of approach for concurrency control of transaction processing. Previous works show that hardware transactional memory is a very promising mechanism when processing typical OLTP workloads and scales well on multi-core machines. However, the high transaction abort rate caused by capacity overflow is also the major trouble when applying hardware transactional memory in transaction execution under high-contention workloads. many methods, such as falling back to lock-based approaches, have been proposed to improve the performance when applying hardware transactional memory to transaction execution. In this paper, we analyze the penalty of abort and fall back when hardware transactional memory fails to process transactions. Based on these analyses, we exploit the strengths of hardware transactional memory with an adaptive hybrid mechanism to improve both the throughput and latency of transaction processing on the multicore systems. Our experiment on TPC-C shows that our adaptive design can remarkably improve the throughput and latency of in-memory transaction processing. © 2019 ieee.

关键词： Concurrency control

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