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2019 ieee international Conference on systems, Man and Cybernetics, SMC 2019

作者： Chen, Qiaosong Wang, Zhixiang Long, Baijun Sui, Xiaoxu Zhang, Meng Deng, Xin Wang, Jin Chongqing University of Posts and Telecommunications Key Laboratory of Data Engineering and Visual Computing Chongqing400065 China Streamax AI Lab Streamax Chongqing400039 China

ISBN: (纸本)9781728145693

Lane detection task is the most necessary part in modern intelligent driving technology. However, there still have many challenge need to be conquered. In this paper, we proposed a three-branch neural network, in this framework, there are several new techniques are used. Including multi-branch, lightweight module, feature recalibration and decoder module, named Three Branch Net. Furthermore, A new dataset have been used, which includes much more complex situation and more close to the real world. Compared with other newest method, experiment results shows the proposed approach is the most effective method in complex road conditions task. © 2019 ieee.

关键词： Complex networks

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An Efficient and Parallel Bad Block Checker for Parallelism of Storage Devices

An Efficient and Parallel Bad Block Checker for Parallelism ...

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Autonomic computing and Self-Organizing systems Companion (ACSOS-C), ieee international Conference on

作者： Jaehyun Han Guangyu Zhu Eunseo Lee Yongseok Son School of Computer Science and Engineering Chung-Ang University Seoul South Korea

ISBN: (数字)9781728184142

ISBN: (纸本)9781728184159

Cloud computing is being widely adopted in the industry due to providing more computation power and improve resource utilization. In cloud computing systems, many users execute various types of applications that produce a large amount of data. To handle a large amount of data, cloud computing systems provide various, high-performance, and large-scale clustered storage devices. With the large capacity, improving the performance of storage maintenance is an important issue since the large capacity can increase the suspend time during the maintenance significantly. As a storage maintenance technique, checking a bad block in which the data cannot be accessed anymore prevents I/O failure of the application. However, an existing bad block checker (e.g., badblocks in Linux) takes a long time, even when storage devices provide parallelism (e.g., multiple disks, multi-channel SSD, etc). It is because the existing bad block checker performs I/O and check operations in a serialized manner. To reduce the checking time, we propose an efficient and parallel bad block checker for exploiting the parallelism of storage devices. In our scheme, we enable parallel I/O and check operations for the bad block instead of the serialized operations. To do this, we first divide a series of check operations into parallel tasks (i.e., independent tasks). Second, we create a thread pool in which multiple workers fetch their tasks concurrently. Finally, we enable each checker to perform its own check and I/O operations in parallel. We implement and evaluate our checker on a 32-core machine with a disk array and an NVMe SSD. The experimental results show that our proposed bad block checker improves the performance by up to 99% and 98% in the disk array and NVMe SSD, respectively, compared with the existing bad block checker.

关键词： Task analysis Parallel processing Performance evaluation Maintenance engineering Cloud computing Linux Reliability

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Performance-Aware Model for Sparse Matrix-Matrix multiplication on the Sunway TaihuLight Supercomputer

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ieee TRANSACTIONS ON PARALLEL AND DISTRIBUTED systems 2019年第4期30卷 923-938页

作者： Chen, Yuedan Li, Kenli Yang, Wangdong Xiao, Guoqing Xie, Xianghui Li, Tao Hunan Univ Coll Informat Sci & Engn Changsha 410082 Hunan Peoples R China Natl Supercomp Ctr Changsha Changsha 410082 Hunan Peoples R China Hunan Univ Natl Supercomp Ctr Changsha Coll Informat Sci & Engn Changsha 410082 Hunan Peoples R China Univ Waterloo David R Cheriton Sch Comp Sci Waterloo ON N2L 3G1 Canada Jiangnan Inst Comp Technol State Key Lab Math Engn & Adv Comp Wuxi 214000 Jiangsu Peoples R China Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

General sparse matrix-sparse matrix multiplication (SpGEMM) is one of the fundamental linear operations in a wide variety of scientific applications. To implement efficient SpGEMM for many large-scale applications, this paper proposes scalable and optimized SpGEMM kernels based on COO, CSR, ELL, and CSC formats on the Sunway TaihuLight supercomputer. First, a multi-level parallelism design for SpGEMM is proposed to exploit the parallelism of over 10 millions cores and better control memory based on the special Sunway architecture. Optimization strategies, such as load balance, coalesced DMA transmission, data reuse, vectorized computation, and parallel pipeline processing, are applied to further optimize performance of SpGEMM kernels. Second, we thoroughly analyze the performance of the proposed kernels. Third, a performance-aware model for SpGEMM is proposed to select the most appropriate compressed storage formats for the sparse matrices that can achieve the optimal performance of SpGEMM on the Sunway. The experimental results show the SpGEMM kernels have good scalability and meet the challenge of the high-speed computing of large-scale data sets on the Sunway. In addition, the performance-aware model for SpGEMM achieves an absolute value of relative error rate of 8.31 percent on average when the kernels are executed in one single process and achieves 8.59 percent on average when the kernels are executed in multiple processes. It is proved that the proposed performance-aware model can perform at high accuracy and satisfies the precision of selecting the best formats for SpGEMM on the Sunway TaihuLight supercomputer.

关键词： Heterogeneous many-core processor parallelism performance analysis performance-aware SpGEMM Sunway TaihuLight supercomputer

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Smart Contracts on the Move

Smart Contracts on the Move

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international Conference on Dependable systems and Networks (DSN)

作者： Enrique Fynn Alysson Bessani Fernando Pedone Università della Svizzera Italiana Switzerland LASIGE Faculdade de Ciências Universidade de Lisboa Portugal Università della Svizzera Italiana Interchain Foundation Switzerland

ISBN: (数字)9781728158099

ISBN: (纸本)9781728158105

Blockchain systems have received much attention and promise to revolutionize many services. Yet, despite their popularity, current blockchain systems exist in isolation, that is, they cannot share information. While interoperability is crucial for blockchain to reach widespread adoption, it is difficult to achieve due to differences among existing blockchain technologies. This paper presents a technique to allow blockchain interoperability. The core idea is to provide a primitive operation to developers so that contracts and objects can switch from one blockchain to another, without breaking consistency and violating key blockchain properties. To validate our ideas, we implemented our protocol in two popular blockchain clients that use the Ethereum virtual machine. We discuss how to build applications using the proposed protocol and show examples of applications based on real use cases that can move across blockchains. To analyze the system performance we use a real trace from one of the most popular Ethereum applications and replay it in a multi-blockchain environment.

关键词： Contracts Protocols Peer-to-peer computing Interoperability Bitcoin

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OpenCL Superpixel Implementation on a General Purpose multi-core CPU

OpenCL Superpixel Implementation on a General Purpose Multi-...

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ieee international Conference on Imaging systems and Techniques (IST)

作者： Haseljic, Hana Cogo, Emir Prazina, Irfan Turcinhodzic, Razija Buza, Emir Akagic, Amila Univ Sarajevo Dept Comp Sci & Informat Fac Elect Engn Sarajevo Bosnia & Herceg

ISBN: (纸本)9781538666289

multi-, many-core, hybrid processors and parallel programming languages are slowly becoming pervasive in mainstream computing. It is expected that they will affect a large spectrum of systems, from embedded and general-purpose, to high-end computing systems. This architectural change has already challenged programmers to efficiently write an application code that can scale over many cores to utilize its computational power. Moreover, many heterogeneous architectures exist today, hence there was an emergent need for a uniform interface to these architectures. Recently, Khronos Group defined the Open computing Language (OpenCL) for abstracting the underlying hardware, which enables software developers to write a portable code across different shared-memory architectures. In this paper, we introduce a new parallel implementation of one of the fastest image segmentation algorithms known as Simple Linear Iterative Clustering based on OpenCL. We evaluate the effectiveness of this implementation using only multi-core GPCPU. Our implementation is fully compatible with sequential implementation. When the algorithm is executed sequentially it utilizes only 25% of total computational power of a GPCPU for any image resolution, while its modified algorithm is able to utilize close to 100% for high resolution images. The resulting algorithm is up to 5x faster than its sequential counterpart.

关键词： parallel programming multi-core gpcpu opencl superpixel image segmentation image processing

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AxMemo: Hardware-Compiler Co-Design for Approximate Code Memoization 19

AxMemo: Hardware-Compiler Co-Design for Approximate Code Mem...

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46th international Symposium on Computer Architecture (ISCA) / workshop on Computer Architecture Education (WCAE)

作者： Liu, Zhenhong Yazdanbakhsh, Amir Wang, Dong Kai Esmaeilzadeh, Hadi Kim, Nam Sung Univ Illinois Urbana IL 61801 USA Google Brain Mountain View CA USA Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9781450366694

Historically, continuous improvements in general-purpose processors have fueled the economic success and growth of the IT industry. However, the diminishing benefits from transistor scaling and conventional optimization techniques necessitates moving beyond common practices. Approximate computing is one such unconventional technique that has shown promise in pushing the boundaries of general-purpose processing. This paper sets out to employ approximation for processors that are commonly used in cyberphysical domains and may become building blocks of Internet of Things. To this end, we propose AxMemo to exploit the computation redundancy that stems from data similarity in the inputs of code blocks. Such input behavior is prevalent in cyber-physical systems as they deal with real-world data that naturally harbors redundancy. Therefore, in contrast to existing memoization techniques that replace costly floating-point arithmetic operations with limited number of inputs, AxMemo focuses on memoizing blocks of code with potentially many inputs. As such, AxMemo aims to replace long sequences of instructions with a few hash and lookup operations. By reducing the number of dynamic instructions, AxMemo alleviates the von Neumann and execution overheads of passing instructions through the processor pipeline altogether. The challenge AxMemo facing is to provide low-cost hashing mechanisms that can generate rather unique signature for each multi-input combination. To address this challenge, we develop a novel use of Cyclic Redundancy Checking (CRC) to hash the inputs. To increase lookup table hit rate, AxMemo employs a two-level memoization lookup, which utilizes small dedicated SRAM and spare storage in the last level cache. These solutions enable AxMemo to efficiently memoize relatively large code regions with variable input sizes and types using the same underlying hardware. Our experiment shows that AxMemo offers 2.64xspeedup and 2.58xenergy reduction with mere 0.2% of qualit

关键词： Memoization Approximate computing Hardware-Software Co-Design

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multi-Role SpTRSV on Sunway many-core Architecture 20

Multi-Role SpTRSV on Sunway Many-core Architecture<bold> </b...

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20th ieee international Conference on High Performance computing and Communications (HPCC) / 16th ieee international Conference on Smart City (SmartCity) / 4th ieee international Conference on Data Science and systems (DSS)

作者： Li, Mingzhen Liu, Yi Yang, Hailong Luan, Zhongzhi Qian, Depei Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781538666142

Sparse triangular solver (SpTRSV) is an important and indispensable building block for many scientific applications. The parallelism of SpTRSV is exploited using Level-Set method in literature, however this method still suffers from high synchronization cost and irregular global memory access especially on many-core architecture such as Sunway. In this paper, we propose an efficient implementation of SpTRSV using the massive computing resources on Sunway architecture. Specifically, we divide the 64 CPEs in a core group into three different roles, worker, router and storer. We also build a logical shared memory by carefully manipulating the scratchpad memory located in each storer and allow synchronization using the unique register communication on Sunway architecture. We partition the sparse matrix into multiple bands and replace the irregular global memory accesses with shared memory accesses, which significantly improves the data locality during the calculation of a band. Our experiments with 12 representative datasets demonstrate that our approach achieves up to 5.14x (2.65x on average) speedup.

关键词： Registers Sparse matrices Computer architecture Synchronization Program processors Parallel processing Conferences

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A Memory Access Reduced Sort on multi-core GPU 20

A Memory Access Reduced Sort on Multi-core GPU<bold> </bold>

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作者： Guo, Chengxin Chen, Hong Li, Cuiping Wu, Tianzhen Renmin Univ China Sch Informat Minist Educ Key Lab Data Engn & Knowledge Engn Beijing 100872 Peoples R China

ISBN: (纸本)9781538666142

In recent years, many cores architecture co-processors have become the main trend in high-performance computing area due to their powerful parallel computing capability. GPU is one of these promising high-performance computing co-processors and has been used in various applications for improvement. Sorting is a fundamental operation on computing area which can be used in a variety of applications. High efficient sorting algorithms can be achieved with the use of GPUs as well as challenges. On the one hand, GPU is a memory access sensitive hardware. On the other hand, many access on device memory are required in stages of sorting on GPU. In order to reduce the times of accessing device memory of sorting, we propose a Memory Access Reduced sort, an approach combining memory efficient radix sort and local sort. The local sort is implemented in two different ways. One is multiway bitonic sorting network (MAR-MBSN) in which the warp-shuffle instructions are taken advantage of. Another is radix and place sort (MAR-RPS). As the increasing require of high performance computing, multi-core GPUs have emerged. To fully use of the computing resources of GPU, two methods are applied for implementing our approach on dual-cores GPU. Experiments show that, compared to the CUB library sorting, MAR-MBSN has an up to 44% improvement and MAR-RPS gains an up to 3-fold speedup in local sort. As a result, MAR-MBSN and MAR-RPS achieves a speed up of no less than a factor of 1.5 and 1.66 respectively. Besides, multi-core GPU is introduced to implement our approaches and the factors relative to performance are analyzed.

关键词： Bitonic Sorting Network multi-core GPU WarpShuffle CUB library

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multi-rate DAG Scheduling Considering Communication Contention for NoC-based Embedded many-core Processor

Multi-rate DAG Scheduling Considering Communication Contenti...

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international workshop/Symposium on Distributed Simulation and Real-Time Applications (DS-RT)

作者： Shingo Igarashi Yuto Kitagawa Tasuku Ishigooka Tatsuya Horiguchi Takuya Azumi Graduate School of Science and Engineering Saitama University Graduate School of Engineering Science Osaka University Hitachi Ltd Center for Technology Innovation - Controls Research and Development Group

computing platforms for embedded systems are increasingly being transformed into multi/many-core platforms because embedded systems have become extensive, complex, and automated. In the case of an autonomous driving system, various applications are simultaneously running, and low power consumption and large-scale calculation are required. many-core processors with a multiple instruction, multiple data (MIMD) architecture can meet these requirements. This paper proposes a scheduling algorithm for an automotive driving system expressed in a directed acyclic graph (DAG) and we use Kalray MPPA-256 as the target many-core processor. On the basis of the architecture of Kalray MPPA-256, task processing that requires large-scale calculation and intercore communication is performed while avoiding communication contention by using a proposed grouping computational resource. In addition, we propose a scheduling method for a multi-rate DAG which is a DAG with multiple periods. This method generates a DAG task in a hyperperiod and schedules the DAG with dependency on tasks that have been released closely. The formulas for prioritization and processor selection are proposed for various generated tasks in a hyperperiod. Evaluation results show that the proposed algorithm is superior to existing DAG scheduling algorithms with regard to schedulability and deadline miss ratio.

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Rate-based thermal, power, and co-location aware resource management for heterogeneous data centers

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JOURNAL OF PARALLEL AND DISTRIBUTED computing 2018年第Part2期112卷 126-139页

作者： Oxley, Mark A. Jonardi, Eric Pasricha, Sudeep Maciejewski, Anthony A. Siegel, Howard Jay Burns, Patrick J. Koenig, Gregory A. Colorado State Univ Dept Elect & Comp Engn Ft Collins CO 80523 USA Colorado State Univ Informat Technol Ft Collins CO 80523 USA Oak Ridge Natl Lab Oak Ridge TN 37830 USA

Today's data centers contain large numbers of compute nodes that require substantial power, and therefore require a large amount of cooling resources to operate at a reliable temperature. The high power consumption of the computing and cooling systems produces extraordinary electricity costs, requiring some data center operators to be constrained by a specified electricity budget. In addition, the processors within these systems contain a large number of cores with shared resources (e.g., last-level cache), heavily affecting the performance of tasks that are co-located on cores and contend for these resources. This problem is only exacerbated as processors move to the many-core realm. These issues lead to interesting performance-power tradeoffs;by considering resource management in a holistic fashion, the performance of the computing system can be maximized while satisfying power and temperature constraints. In this work, the performance of the system is quantified as the total reward earned from completing tasks by their individual deadlines. By designing three resource allocation techniques, we perform a rigorous analysis on thermal, power, and co-location aware resource management using two different facility configurations, three different workload environments, and a sensitivity analysis of the power and thermal constraints. (C) 2017 Elsevier Inc. All rights reserved.

关键词： Heterogeneous computing Resource management Thermal-aware computing Power-aware computing DVFS Memory interference

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