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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 974 条记录，以下是11-20 订阅

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Invited Paper: Open Source Heterogeneous Chiplet-based computing Architectures 43

Invited Paper: Open Source Heterogeneous Chiplet-based Compu...

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43rd international Conference on Computer-Aided Design, ICCAD 2024

作者： Evans, Adrian Fuguet, César Million, Davy Univ. Grenoble Alpes CEA List Grenoble France

ISBN: (纸本)9798400710773

Leading edge processors, such as AMD’s MI300 and Intel’s Ponte Vecchio, rely on 3D integration of heterogeneous architectures including CPUs and GPUs or vector processors to provide the highest performance. There are many models for memory coherency within such chips and there is a need for research on the best way to map various kernels to these architectures including studying how best to share data. Unfortunately, the hardware in commercial processors is closed, which limits research opportunities, particularly for hardware/software co-design. Recent projects such as OpenPiton, and numerous follow-on projects, have made it possible for the research community to develop coherent, multi-core systems based on RISC-V. The next step is to enhance the support in open source, multi-core platforms for heterogeneous computing (GPUs, FPGA accelerators) and to explore 3D partitioning of such systems. In this paper, we present the state-of-the art of such open source platforms and sketch a roadmap which we hope will enable the research community to continue to contribute to the development of today’s advanced heterogeneous architectures. © 2024 Copyright is held by the owner/author(s).

关键词： Open systems

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Optimized All-to-all Connection Establishment for High-Performance MPI Libraries over InfiniBand 30

Optimized All-to-all Connection Establishment for High-Perfo...

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30th international Conference on High Performance computing, Data, and Analytics (HiPC)

作者： Xu, Shulei Kuncham, Goutham Kalikrishna Reddy Abduljabbar, Mustafa Subramoni, Hari Panda, Dhabaleswar K. (Dk) Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9798350383225

In modern multi-/many-core HPC systems, the increasing number of processor cores presents new challenges in managing parallel compute workloads across multiple nodes. One crucial aspect that significantly impacts the startup phase of parallel MPI jobs is the methodology used for connection establishment. In this paper, we investigate the limitations of existing all-to-all connection establishment designs in-depth, identify the primary sources of performance overhead, and propose an optimized all-to-all connection establishment design. This is done through an enforced ordering rank-by-rank scheme that significantly cuts down on the data exchange overhead via PMI. To address the increasing overheads associated with queue pair creation and synchronization, we explore multi-thread parallelism and incorporate CPU affinity awareness into our design. We implement our proposed design in the state-of-the-art MVAPICH2 MPI library and conduct extensive experiments on two emerging architectures. Through a comprehensive performance evaluation of these architectures, we demonstrate the efficacy of our optimized all-to-all connection establishment design. Our microbenchmark results reveal up to 20 times faster MPI Init time, while evaluations with application kernels exhibit a 31% improvement in throughput.

关键词： multi-/many-core HPC MPI Job Startup Connection Establishment InfiniBand RDMA

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Concurrent Scanning through Adaptive Task Distribution for Simultaneous Lexing on multi-core Platforms 2

Concurrent Scanning through Adaptive Task Distribution for S...

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2nd international Conference on Automation, computing and Renewable systems, ICACRS 2023

作者： Vaikunta Pai, T. Ashwin Shenoy, M. Nitte India Nitte India

ISBN: (纸本)9798350340235

The integration of advanced multi-core architectures is swiftly becoming customary in the realm of digital technology. This can be credited to their remarkable parallel computational capabilities, leading to substantial enhancements in performance. To fully leverage the potential of multi-core systems, a redesign of system software, including compilers, is imperative to accommodate parallel processing. Over time, notable progress has been made in enhancing the effectiveness of lexing through utilizing the inherent concurrent computational capabilities present in computer systems with multiple cores. This current advancement in implementation highlights the superiority of a concurrent lexical analyzer in contrast to its conventional sequential equivalent, especially during the execution of lexing tasks. The research explores the strategy of incorporating parallelism during the source code scanning phase within lexing process. The primary objective of this work is to elucidate the techniques employed to achieve parallel lexical analysis. Within the realm of processors with multiple cores, various instances of the lexer application can be executed simultaneously. This enables token identification by scanning many lines in the input stream at the same time. Tasks are assigned on a per-line basis to idle cores, thus enabling efficient parallel processing. Both theoretical analysis and empirical observations confirm that the introduced technique offers a significant advantage over the sequential approach regarding tokenization performance. Significantly, it diminishes the duration needed for tokenization process in the compilation. The results conclusively demonstrate that the efficiency of the parallel process in lexical analyzer is expected to exhibit a linear relationship with the cores employed in process. It is clear that the acceleration will increase with a higher count of CPU cores, potentially further expediting the compilation method. © 2023 ieee.

关键词： Lexing multi-core system Task distribution

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High Dynamic Collaborative Team Query via multi-Fuzzy-Constrained Graph Pattern Matching 9

High Dynamic Collaborative Team Query via Multi-Fuzzy-Constr...

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9th international Conference on Cloud computing and Big Data Analytics, ICCCBDA 2024

作者： Hu, Tao Zhang, Zan Bu, Chenyang Li, Lei Key Laboratory of Knowledge Engineering with Big Data The Ministry of Education of China School of Computer Science and Information Engineering Hefei University of Technology Hefei China

ISBN: (纸本)9798350373554

Graph pattern matching is a technique widely used in various fields such as protein structure analysis, social group querying, and expert localization. This technique involves finding matching subgraphs in large social networks that align with the patterns specified in the pattern graph. In this paper, we focus on a specific sub-problem in social group querying, known as the cooperative team query, which arises from practical applications, where the nodes in the pattern graph and the data graph represent team member entities, while the edges represent their social relationships. We note that the requirements of many teams in the real world are dynamic, necessitating iterative computation for graph pattern matching using traditional methods. To address this challenge in highly dynamic systems, we propose a graph pattern matching method based on core pattern graph matching cache. This approach involves extracting the core pattern graph, and comprising core team members based on the characteristics of cooperative teams. The core graph-based matching cache enables the second half of the algorithm to operate on an order-of-magnitude smaller graph, significantly improving efficiency. Additionally, the multi-threaded approach fully leverages hardware resources, synchronizing multiple matching result of the core pattern graph to reduce matching time. Experimental results on three real social network datasets demonstrate that our proposed algorithm, core Pattern Graph Matching Cache-based multi-threaded Exploration (CCMTE), significantly outperforms existing methods in terms of efficiency. © 2024 ieee.

关键词： Efficiency

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Memory-efficient Edge-based Non-Neural Face Recognition Algorithm on the Parallel Ultra-Low Power (PULP) Cluster 16

Memory-efficient Edge-based Non-Neural Face Recognition Algo...

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16th ieee international Symposium on Embedded multicore/many-core systems-on-Chip (MCSoC)

作者： Nagar, Mitul Sudhirkumar Maiti, Sayantan Kumar, Rahul Mewada, Hiren Engineer, Pinalkumar Sardar Vallabhbhai Natl Inst Technol Dept Elect Engn Surat India Prince Mohammad Bin Fahd Univ Elect Engn Dept Al Khobar Saudi Arabia

ISBN: (纸本)9798350393613

Resource-constrained edge computing nodes observed scarcity in terms of memory and computation power. It is inevitable to use computer vision (CV) algorithms on the edge for feature extractions. However, it is challenging to implement compute-intensive and resource-hungry convolution neural network (CNN) algorithms on the edge. Hence, this work targets a non-neural Eigenfaces-based face recognition (FR) algorithm to reduce the memory footprint and latency on the edge. Furthermore, the effective implementation of computations related to artificial neural networks (ANN) and machine learning (ML) algorithms has recently seen the development of quantization as an important and very active area of research. Quantization of Eigenface-based FR algorithm's training data from 32-bit floating-point to 8-bit fixed-point offers 93% accuracy on octacore PULP platform with 26.31x less model size compared to state-of-the-art (SoA) deep learning (DL) SqueezeNet1.1-based FR on GAP8 platform. Quantization and parallelization were performed on Eigenface-based FR to improve the performance in terms of response time. Additionally, the quantized model was transferred from HyperRAM (L3) to cluster memory (L1) using direct memory access (DMA) via fabric control memory (L2) with double DMA transfer ( D2 T), which reduces the number of execution cycles by 82x. With this technique, 120K faces can be recognized per second on the multi-core RISC-V PULP cluster at an accuracy of 93%. Compared to the non-DMA non-quantized (NDNQ) version of the Eigenfaces-based face recognition system, our implementation reduces the recognition time by 1742.85x and 917.43x for single- and octa-core, respectively. Quantization improves the recognition rate due to the reduction in execution cycles, instructions, and load operations by 82x, 25.37x, and 4658.74x respectively, compared to NDNQ versions of FR on the PULP cluster.

关键词： Quantization Non-Neural Eigenfaces-based face recognition multi-core cluster RISC-V

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A Case for Second-Level Software Cache Coherency on many-core Accelerators 33

A Case for Second-Level Software Cache Coherency on Many-Cor...

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33rd ieee international workshop on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Vianes, Arthur Petrot, Frederic Rousseau, Frederic de Dinechin, Benoit Dupont Univ Grenoble Alpes CNRS Grenoble INP TIMA F-38000 Grenoble France Kalray SA F-38330 Montbonnot St Martin France

ISBN: (纸本)9798350398519

Cache and cache-coherence are major aspects of today's high performance computing. A cache stores data as cachelines of fixed size, and coherence between caches is guaranteed by the cache-coherence protocol which operates on fixed size coherency-blocks. In such systems cache-lines and coherencyblocks are usually the same size and are relatively small, typically 64 bytes. This size choice is a trade-off selected for generalpurpose computing: it minimizes false-sharing while keeping cache-maintenance traffic low. False-sharing is considered an unnecessary cache-coherence traffic and it decreases performances. However, for dedicated accelerator this trade-off may not be appropriate: hardware in charge of cache-coherence is expensive and not well exploited by most accelerator applications as by construction these applications minimize false-sharing. This paper investigates the possibility of an alternative tradeoff of cache-coherency and cache-maintenance block size for many-core accelerators, by decoupling coherency-block and cache-lines sizes. Interests, advantages and difficulties are presented and discussed in this paper. Then we also discuss needs of software and hardware modifications in prototypes and the capability of such prototypes to evaluate different coherenceblock sizes.

关键词： software cache coherence many-core accelerator virtual memory memory pages

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multi-objective Optimization Regression Verification for multi-core Cache Coherence Protocol 23

Multi-objective Optimization Regression Verification for Mul...

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23rd ieee international Conference on High Performance computing and Communications, 7th ieee international Conference on Data Science and systems, 19th ieee international Conference on Smart City and 7th ieee international Conference on Dependability in Sensor, Cloud and Big Data systems and Applications, HPCC-DSS-SmartCity-DependSys 2021

作者： Luo, Li Zhang, Ying He, Hongjun Wang, Lei Xun, Chanzqing Pan, Guoteng Tie, Junbo Hu, Huili College of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781665494571

With the development of multi-core and many-core processor architecture, cache consistency protocols become increasingly complex, verification is also becoming more challenging. Regression verification runs through the whole process of chip design and is an indispensable part of chip design and verification. It takes a lot of time and resources to execute a gigantic set of test cases. In this paper, a test case priority ranking method based on multi-objective optimization is proposed, which is applied to the regression verification for RTL design of an original multi-core processor cache coherence protocol. Based on the detection rate of defect prediction and function coverage rate as the optimization objectives, the test case priority is ranked. The experimental results show that the proposed method can improve the effectiveness of simulation verification, reduce time and cost, find defects as soon as possible, improve the reliability of the chip, is of great theoretical significance and of engineering practical value. © 2021 ieee.

关键词： Protocols Costs multicore processing Smart cities Coherence Reliability engineering Complexity theory

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Developing a proxy application for an industrial unstructured CFD software: preliminary results 29

Developing a proxy application for an industrial unstructure...

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29th ieee international Conference on Parallel and Distributed systems, ICPADS 2023

作者： Wang, Qingsong Xu, Chuanfu Zhang, Jian Deng, Liang Dai, Zhe Qiu, Haozhong Dai, Weixi Lin, Yongzhen Ding, Yue Che, Yonggang National University of Defense Technology Institute for Quantum Information State Key Laboratory of High Performance Computing Changsha China China Aerodynamic Research and Development Center Mianyang China

ISBN: (纸本)9798350330717

As programming models and architectures evolve in the exa-scale era, porting large-scale HPC applications are becoming increasingly difficult and expensive. In HPC community, mini-apps are often developed to mimic real-world applications, and it offers an easy way to benchmark new HPC platforms. In this paper, we design and implement a mini-app MiniFS as a proxy for an industry-level unstructured Computational Fluid Dynamics (CFD) software FlowStar. The main purpose of MiniFS is to evaluate different shared memory approaches on emerging multi/many-core architectures, because data conflicts and data dependencies in unstructured CFD pose tough challenges for shared memory parallelization. Results show that our mini-app can represent the performance characteristic of the original application. However, the existing approaches are unscalable on modern multi/many-cores. It is imperative to develop novel scalable shared memory approaches for unstructured CFD. © 2023 ieee.

关键词： mini-app shared memory unstructured CFD

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A Scalable Parallel Partition Tridiagonal Solver for many-core and Low B/F Processors 36

A Scalable Parallel Partition Tridiagonal Solver for Many-Co...

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36th ieee international Parallel and Distributed Processing Symposium (ieee IPDPS)

作者： Mitsuda, Tatsuya Ono, Kenji Kyushu Univ Grad Sch Fukuoka Japan Kyushu Univ Fac Informat Sci & Elect Engn Fukuoka Japan Kyushu Univ Res Inst Informat & Technol Fukuoka Japan

ISBN: (纸本)9781665497473

Tridiagonal systems are among the most fundamental computations in science, engineering, and mathematics, and one solver used in such systems is Tree Partitioning Reduction (TPR), which is a divide-and-conquer method that solves large-scale linear equations by dividing them and then computing the parts in parallel within different local memory threads. Herein, we propose an improved TPR algorithm that has a parallel cyclic reduction flavor, with which we reduced the number of algorithm steps by approximately half while simultaneously increasing arithmetic intensity and cache reusability. A performance evaluation conducted on an Intel Skylake-SP microprocessor showed a high hit ratio for the L1 cache and that our solver was as much as 31 times faster on 32 threads for 262144 equations. In the case of a Nvidia Tesla P100 GPU, our method processed 10 MRow/s more than TPR and cuSPARSE.

关键词： Tridiagonal system GPU Parallel computing multi/many-core

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Optimizing GNN on ARM multi-core Processors 24

Optimizing GNN on ARM Multi-Core Processors

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24th ieee international Conference on High Performance computing and Communications, 8th ieee international Conference on Data Science and systems, 20th ieee international Conference on Smart City and 8th ieee international Conference on Dependability in Sensor, Cloud and Big Data systems and Application, HPCC/DSS/SmartCity/DependSys 2022

作者： Liu, Chaorun Su, Huayou Dou, Yong Chen, Kangkang Sun, Yanjie National University of Defense and Technology China

ISBN: (纸本)9798350319934

Graph Neural Network (GNN) has shown great success in graph learning, including physics systems, protein interfaces, disease classification, molecular fingerprints, etc. Due to the complexity of the real-world tasks and the big graph datasets, current GNN models become increasingly bigger and more complicated to enhance the learning ability and prediction accuracy. In addition, GNN contains two main major components graph operation and neural network (NN) operation, both are executed alternately during processing. The interleaved complex processing of GNN poses a challenge for many computational platforms, especially for those without accelerators. Current optimization frameworks solely for deep learning or graph computing cannot achieve good performance on GNN. In this work, we first investigate the performance bottlenecks when handling GNN over multi-core processors. Then, we perform a set of optimization strategies to leverage the capability of multi-core processors for GNN processing. Specifically, we build a set of microkernels for graph operations of GNN with assembly instructions that can exploit the capability of SIMD processing units within a core and implement a task allocator based on a greedy algorithm to balance the workloads between the cores of CPU. In addition, we use some strategies to optimize NN operation for GNN, according to the characteristics of NN operation in GNN. Experimental results show that the proposed methods can achieve a maximum of 2.88x and 4.08x performance improvements for various GNN models on Phytium 2000+ and Kunpeng 920 over the state-of-the-art GNN framework. © 2022 ieee.

关键词： Deep learning

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