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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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AutoStreams: Fully Automatic parallelization of Legacy Embedded Applications with Soft-core MPSoCs

AutoStreams: Fully Automatic parallelization of Legacy Embed...

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international Conference on Reconfigurable computing and FPGAs (ReConFig)

作者： Heid, Kris Hochberger, Christian Tech Univ Darmstadt Comp Syst Grp Darmstadt Germany

ISBN: (纸本)9781728119687

In many digital systems a considerable part of the functionality is defined in software. Implementing these systems on Field Programmable Gate Arrays offers the additional degree of freedom to implement arbitrary multi-core systems consisting of soft-cores. In case of existing legacy software, this requires to rewrite the software such that it can be executed on the multi-core setup. In this contribution, we present a tool that automatically converts a given legacy software into a functional pipeline of individual soft-cores. The user can specify a timing requirement and the tool autonomously chooses a suitable number of cores, partitions the software accordingly and generates the hardware setup for the multi-core system. We show that our method achieves equally good results as manually parallelized designs and achieves higher speedups compared to related publications.

关键词： AutoStreams automatic parallelization embedded MPSoC FPGA Soft-core

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Towards Incremental Static Race Detection in OpenMP Programs 2

Towards Incremental Static Race Detection in OpenMP Programs

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2nd ieee/ACM international workshop on Software Correctness for High-Performance computing (HPC) Applications

作者： Swain, Bradley Huang, Jeff Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

ISBN: (纸本)9781728102269

OpenMP is a high level API that allows programmers to write concurrent programs on multi- core systems. OpenMP provides an interface for easily managing teams of threads and concurrent tasks allowing the programmer to focus on modeling a problem concurrently rather than dealing with low level thread management details for each system on which the code may run. Although OpenMP can automatically handle many parts of writing parallel programs (thread management, work distribution, scheduling, etc.), OpenMP offers no protection against data races. The programmer is left with the difficult task of ensuring that OpenMP programs are free of data races. many concurrent programs, especially those related to high performance computing, can be difficult for programmers to reason through and are particularly prone to data races due to programmer error. This paper presents an extensible and incremental static analysis technique for detecting data races in OpenMP programs at compile time. Our technique is comprised of two primary components: (i): Array Index Analysis, which is used to detect when two array accesses made from separate threads may overlap resulting in multiple accesses to the same location in memory. (ii): An Incremental Phase Graph is used to build a May Happen in Parallel (MHP) model that is utilized in determining if overlapping array accesses are capable of occurring concurrently.

关键词： OpenMP Race Detection High Performance computing Static Analysis

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High-Throughput multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

High-Throughput Multi-Threaded Sum-Product Network Inference...

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ieee/ACM international workshop on Heterogeneous High-performance Reconfigurable computing (H2RC)

作者： Micha Ober Jaco Hofmann Lukas Sommer Lukas Weber Andreas Koch Embedded Systems and Applications Group TU Darmstadt Germany Technical University Darmstadt Darmstadt Germany

Large cloud providers have started to make powerful FPGAs available as part of their public cloud offers. One promising application area for this kind of instances is the acceleration of machine learning tasks. This work presents an accelerator architecture that uses multiple accelerator cores for the inference in so-called Sum-Product Networks and complements it with a host software interface that overlaps data-transfer and actual computation. The evaluation shows that, the proposed architecture deployed to Amazon AWS F1 instances is able to outperform a 12-core Xeon processor by a factor of up to 1.9x and a Nvidia Tesla V100 GPU by a factor of up to 6.6x.

关键词： Field programmable gate arrays Cloud computing Acceleration Probabilistic logic Machine learning Software Graphical models

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HSTREAM: A directive-based language extension for heterogeneous stream computing 21

HSTREAM: A directive-based language extension for heterogene...

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21st ieee international Conference on Computational Science and Engineering (CSE)

作者： Memeti, Suejb Pllana, Sabri Linnaeus Univ Dept Comp Sci Vaxjo Sweden

ISBN: (纸本)9781538676493

Big data streaming applications require utilization of heterogeneous parallel computing systems, which may comprise multiple multi-core CPUs and many-core accelerating devices such as NVIDIA GPUs and Intel Xeon Phis. Programming such systems require advanced knowledge of several hardware architectures and device-specific programming models, including OpenMP and CUDA. In this paper, we present HSTREAM, a compiler directive-based language extension to support programming stream computing applications for heterogeneous parallel computing systems. HSTREAM source-to-source compiler aims to increase the programming productivity by enabling programmers to annotate the parallel regions for heterogeneous execution and generate target specific code. The HSTREAM runtime automatically distributes the workload across CPUs and accelerating devices. We demonstrate the usefulness of HSTREAM language extension with various applications from the STREAM benchmark. Experimental evaluation results show that HSTREAM can keep the same programming simplicity as OpenMP, and the generated code can deliver performance beyond what CPUs-only and GPUs-only executions can deliver.

关键词： stream computing heterogeneous parallel computing systems source-to-source compilation

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COMFAST: A Comparative Framework for Analysis of Scheduling Techniques in multi-core systems 12

COMFAST: A Comparative Framework for Analysis of Scheduling ...

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12th Annual ieee international systems Conference (SYSCON)

作者： Shah, Sarah Qahir, Abdul Safeer, Masooma Mazahir, Sana Hasan, Osman Natl Univ Sci & Technol Sch Elect Engn & Comp Sci Islamabad Pakistan

ISBN: (纸本)9781538636640

multi-core systems are increasingly being used for developing many real-time systems to meet the growing demands of high-speed computing and low-power dissipation. However, the delays due to the conflicts that arise when multiple cores access the shared system resources simultaneously encumber these systems to reach their peak efficiency. Several scheduling algorithms have been proposed to abate the issue of resource contention. However, comparing various scheduling techniques is a major challenge due to the different underlying assumptions and the lack of a common ground for analysis. In this paper, we propose a unified Comparative Framework for Analysis of Scheduling Techniques (COMFAST) in multi-core systems. The proposed framework supports the comparison based on a general data set and characterizes the performance in terms of the worst-case response times (WCRT) and acceptance ratios. For illustration, the paper presents the comparison of two of the recently proposed scheduling techniques, i.e., 1) Dynamic Task Aware Scheduling that uses complimentary tasks to mitigate contention, and 2) First Fit Allocation Based on Symmetric Analysis that approaches response time through the shared-resource-centric perspective and the core-centric-perspective. Our results show that Dynamic Task Aware Scheduling provides considerably reduced response times for a variety of resource access frequencies compared to First Fit Allocation. However, in terms of acceptance ratios, First Fit Allocation demonstrates a much better performance.

关键词： multi-core Shared Resources Resource Contention Scheduling Algorithm Worst Case Response Time (WCRT) Acceptance Ratio

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FPGA Implementation of a multi-Channel Continuous-Throughput FFT Processor

FPGA Implementation of a Multi-Channel Continuous-Throughput...

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ieee international workshop on Signal Processing systems (ieee SiPS)

作者： Fankhauser, Elia Wassner, Juergen Lucerne Univ Appl Sci & Arts RSLUR Intelligent Sensors & Networks Lab ISN Luzern Switzerland

ISBN: (纸本)9781538663189

The Fast Fourier Transform (FFT) is at the heart of many signal processing systems, e.g. those using orthogonal frequency-division multiplexing (OFDM) modulation. For such systems the FFT is typically implemented on dedicated hardware, e.g. field-programmable gate arrays (FPGAs), to meet the high throughput and latency requirements. This paper describes a 2 parallel radix-2 FFT core embedded into an overall processing architecture that allows data interfaces to be tailored to application specific needs. The proposed solution can dynamically switch between different FFT sizes while maintaining its maximum theoretical throughput. Our experiments show that a two-fold increase in throughput can be achieved without doubling resource usage, when taking into account FPGA-specific features for several optimizations.

关键词： FFT FPGA Throughput Butterfly

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Dual Graph-Regularized multi-View Feature Learning 20

Dual Graph-Regularized Multi-View Feature Learning

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20th ieee international Conference on High Performance computing and Communications (HPCC) / 16th ieee international Conference on Smart City (SmartCity) / 4th ieee international Conference on Data Science and systems (DSS)

作者： Chen, Zhikui Qiu, Xiru Zhao, Liang Du, Jianing Dalian Univ Technol Sch Software Technol Dalian Peoples R China Key Lab Ubiquitous Network & Serv Software Liaoni Dalian Peoples R China

ISBN: (纸本)9781538666142

Real-world datasets often describe data instances in different views that complement information for each other. Unfortunately, synthesizing these views for learning a comprehensive description of data items is challenging. To tackle it, many approaches have been studied to explore correlations between various features by assuming that all views can be projected into a same semantic subspace. Following this idea, we propose a novel semi-supervised method, namely dual graph-regularized multi-view feature learning (DGMFL), for data representation in this paper. The core idea is to generate a latent subspace among different views. Our approach utilizes dual graph regularization to capture semantic relationships among data items on both multi-view features and label information, as well as locates view-specific features for each view to reduce the effects of uncorrelated items. In this way, DGMFL could achieve more comprehensive representations hidden in multi-view datasets. Extensive experiments demonstrate that DGMFL model is superior to state-of-the-art multi-view learning methods on real-world datasets.

关键词： noise reduction multi-view data dual graph regularization

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multi-tasking Execution in PGAS Language XcalableMP and Communication Optimization on many-core Clusters 2018

Multi-tasking Execution in PGAS Language XcalableMP and Comm...

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international Conference on High Performance computing in Asia-Pacific Region (HPC Asia) / workshop on Partitioned Global Address Space Programming Models - Experiences and Implementations (PGAS-EI) / Intel-Xeon-Phi-User's-Group (IXPUG) workshop Asia

作者： Tsugane, Keisuke Lee, Jinpil Murai, Hitoshi Sato, Mitsuhisa Univ Tsukuba Grad Sch Syst & Informat Engn Ibaraki Japan RIKEN Adv Inst Computat Sci Kobe Hyogo Japan

ISBN: (纸本)9781450353724

Large-scale clusters based on many-core processors such as Intel Xeon Phi have recently been deployed. multi-tasking execution using task dependencies in OpenMP 4.0 is a promising candidate for facilitating the parallelization of such many-core processors, because this enables users to avoid global synchronization through fine-grained task-to-task synchronization using userspecified data dependencies. Recently, the partitioned global address space (PGAS) model has emerged as a usable distribute-dmemory programming model. In this paper, we propose a multitasking execution model in the PGAS language XcalableMP (XMP) for many-core clusters. The model provides a method to describe interactions between tasks based on point-to-point communications on the global address space. A communication is executed non-collectively among nodes. We implemented the proposed execution model in XMP, and designed a simple code transformation algorithm to MPI and OpenMP. We implemented two benchmarks using our model for preliminary evaluation, namely blocked Cholesky factorization and the Laplace equation solver. Most of the implementations using our model outperform the conventional barrier-based data-parallel model. To improve the performance in many-core clusters,we propose a communication optimization method by dedicating a single thread for communications, to avoid performance problems related to the current multi-threaded MPI execution. As a result, the performances of blocked Cholesky factorization and the Laplace equation solver using this communication optimization are improved to 138% and 119% compared with the barrier-based implementation in Intel Xeon Phi KNL clusters, respectively. From the viewpoint of productivity, the program implemented by our model in XMP is almost the same as the implementation based on the OpenMP task depend clause, because XMP enables the parallelization of the serial source code with additional directives and small changes as well as OpenMP.

关键词： Task Parallelism many-core cluster PGAS XcalableMP

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DM-HEOM: A Portable and Scalable Solver-Framework for the Hierarchical Equations of Motion 32

DM-HEOM: A Portable and Scalable Solver-Framework for the Hi...

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32nd ieee international Parallel and Distributed Processing Symposium (IPDPS)

作者： Noack, Matthias Reinefeld, Alexander Kramer, Tobias Steinke, Thomas Zuse Inst Berlin Berlin Germany

ISBN: (纸本)9781538655559

computing the Hierarchical Equations of Motion (HEOM) is by itself a challenging problem, and so is writing portable production code that runs efficiently on a variety of architectures while scaling from PCs to supercomputers. We combined both challenges to push the boundaries of simulating quantum systems, and to evaluate and improve methodologies for scientific software engineering. Our contributions are threefold: We present the first distributed memory implementation of the HEOM method (DM-HEOM), we describe an interdisciplinary development workflow, and we provide guidelines and experiences for designing distributed, performance-portable HPC applications with MPI3, OpenCL and other state-of-the-art programming models. We evaluated the resulting code on multi- and many-core CPUs as well as GPUs, and demonstrate scalability on a Cray XC40 supercomputer for the PS I molecular light harvesting complex.

关键词： Parallel Programming Portability Portable Performance OpenCL MPI Scientific computing HEOM

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Survey of Memory, Timing, and Power Management Verification Methods for multi-core Processors

Survey of Memory, Timing, and Power Management Verification ...

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international Conference and workshop on computing and Communication (IEMCON)

作者： Savita Patil Sabrina Scholten Melody Tao Hussain Al-Asaad Electrical and Computer Engineering Department University of California Davis CA USA

ISBN: (纸本)9781728125312

Currently, the most significant challenge multicore design engineers face is improving the performance of multiprocessors while decreasing the power consumption. multi-core systems provide a good solution to the increasing high computing applications that need performance boost. However, a good multi-core processor requires thorough and efficient verification procedures. We present a survey on verification techniques for multi-core systems specifically targeting memory, timing, and power management schemes. For memory verification we look into structural simulation-based verification for register arrays, co-simulation techniques, threaded core memory model, symbolic trajectory evaluation for memory arrays, hardware logic emulation, graph model of cache hierarchy and assertion-based simulation schemes. Furthermore, we look into post-silicon verification techniques using the inverse of an instruction and a specific method called DACOTA. For timing verification, we cover three categories of verification: full integration, temporal isolation, and interference effects on schedulability. For dynamic power management schemes, we cover statistical model checking, probabilistic model checking, fractal design verification, and verification for schemes that are interwoven in hardware and software. These verification techniques are tested on the following power management schemes: dynamic voltage and frequency scaling , power gating, and fractal design.

关键词： Program processors multicore processing Power system management Memory management Interference Model checking Timing

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