检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

952 篇 会议
20 篇 期刊文献
2 册 图书

馆藏范围

974 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

653 篇 工学
- 595 篇 计算机科学与技术...
- 238 篇 软件工程
- 190 篇 电气工程
- 76 篇 电子科学与技术（可...
- 61 篇 信息与通信工程
- 31 篇 控制科学与工程
- 23 篇 动力工程及工程热...
- 11 篇 机械工程
- 11 篇 仪器科学与技术
- 8 篇 生物医学工程（可授...
- 7 篇 力学（可授工学、理...
- 7 篇 环境科学与工程（可...
- 6 篇 安全科学与工程
- 5 篇 材料科学与工程（可...
- 5 篇 建筑学
- 5 篇 交通运输工程
- 5 篇 生物工程
- 5 篇 网络空间安全
91 篇 理学
- 53 篇 数学
- 27 篇 系统科学
- 18 篇 物理学
- 8 篇 生物学
- 6 篇 统计学（可授理学、...
- 5 篇 化学
88 篇 管理学
- 76 篇 管理科学与工程(可...
- 31 篇 工商管理
- 14 篇 图书情报与档案管...
10 篇 经济学
- 10 篇 应用经济学
8 篇 法学
- 7 篇 社会学
6 篇 医学
4 篇 教育学
- 4 篇 教育学
3 篇 文学
2 篇 农学
2 篇 军事学

主题

75 篇 computer archite...
62 篇 hardware
60 篇 parallel process...
55 篇 multicore proces...
48 篇 computational mo...
37 篇 concurrent compu...
36 篇 high performance...
34 篇 instruction sets
34 篇 multi-core
33 篇 graphics process...
31 篇 scalability
31 篇 cloud computing
30 篇 parallel program...
29 篇 programming
29 篇 program processo...
29 篇 graphics process...
27 篇 kernel
25 篇 embedded systems
24 篇 conferences
24 篇 resource managem...

机构

9 篇 ohio state univ ...
5 篇 saitama univ gra...
4 篇 ohio state univ ...
3 篇 saitama universi...
3 篇 vienna universit...
3 篇 oak ridge natl l...
3 篇 graduate school ...
3 篇 fraunhofer igd t...
3 篇 center for compu...
3 篇 karlsruhe instit...
3 篇 oak ridge natl l...
3 篇 beihang univ sch...
2 篇 penn state univ ...
2 篇 uppsala univ upp...
2 篇 seoul natl univ ...
2 篇 coll william & m...
2 篇 china university...
2 篇 waseda univ dept...
2 篇 tsinghua univers...
2 篇 national univers...

作者

6 篇 takuya azumi
6 篇 panda d. k.
6 篇 azumi takuya
5 篇 subramoni hari
5 篇 shingo igarashi
5 篇 benini luca
4 篇 tatsuya horiguch...
4 篇 tasuku ishigooka
4 篇 petiton serge
4 篇 el-ghazawi tarek
4 篇 sato mitsuhisa
4 篇 amano hideharu
3 篇 liu bo
3 篇 klasky scott
3 篇 dongarra jack
3 篇 varbanescu ana l...
3 篇 qian depei
3 篇 sriram krishnamo...
3 篇 weichslgartner a...
3 篇 alam sadaf r.

语言

969 篇 英文
4 篇 其他
1 篇 中文

检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 974 条记录，以下是221-230 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Lazy Persistency: a High-Performing and Write-Efficient Software Persistency Technique 18

Lazy Persistency: a High-Performing and Write-Efficient Soft...

引用

45th ACM/ieee Annual international Symposium on Computer Architecture (ISCA)

作者： Alshboul, Mohammad Tuck, James Solihin, Yan North Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)9781538659847

Emerging Non-Volatile Memories (NVMs) are expected to be included in future main memory, providing the opportunity to host important data persistently in main memory. However, achieving persistency requires that programs be written with failure-safety in mind. many persistency models and techniques have been proposed to help the programmer reason about failure-safety. They require that the programmer eagerly flush data out of caches to make it persistent. Eager persistency comes with a large overhead because it adds many instructions to the program for flushing cache lines and incurs costly stalls at barriers to wait for data to become durable. To reduce these overheads, we propose Lazy Persistency (LP), a software persistency technique that allows caches to slowly send dirty blocks to the NVMM through natural evictions. With LP, there are no additional writes to NVMM, no decrease in write endurance, and no performance degradation from cache line flushes and barriers. Persistency failures are discovered using software error detection (checksum), and the system recovers from them by recomputing inconsistent results. We describe the properties and design of LP and demonstrate how it can be applied to loop-based kernels popularly used in scientific computing. We evaluate LP and compare it to the state-of-the-art Eager Persistency technique from prior work. Compared to it, LP reduces the execution time and write amplification overheads from 9% and 21% to only 1% and 3%, respectively.

关键词： Emerging Memory Technology Memory systems multi-core and Parallel Architectures

来源：评论

学校读者我要写书评

暂无评论

Performance Evaluation for Omni XcalableMP Compiler on many-core Cluster System based on Knights Landing 18

Performance Evaluation for Omni XcalableMP Compiler on Many-...

引用

international Conference on High Performance computing in Asia-Pacific Region (HPC Asia) / workshop on Partitioned Global Address Space Programming Models - Experiences and Implementations (PGAS-EI) / Intel-Xeon-Phi-User's-Group (IXPUG) workshop Asia

作者： Nakao, Masahiro Murai, Hitoshi Boku, Taisuke Sato, Mitsuhisa RIKEN Adv Inst Computat Sci Kobe Hyogo Japan Univ Tsukuba Ctr Computat Sci Ibaraki Japan

ISBN: (纸本)9781450363471

To reduce the programming cost on a cluster system, Partitioned Global Address Space (PGAS) languages are used. We have designed an XcalableMP (XMP) PGAS language and developed the OmniXMPcompiler (Omni compiler) for XMP. In the present study, we evaluated the performance of the Omni compiler on Oakforest-PACS, which is a cluster system based on Knights Landing, and on a general Linux cluster system. We performed performance tuning for the Omni compiler using a Lattice QCD mini-application and some mathematical functions appearing in that application. As a result, the performance of the Omni compiler after tuning was improved compared to before tuning on both systems. Furthermore, we compared the performance of MPI and OpenMP (MPI+OpenMP), which is an existing programming model, to that of XMP with the tuned Omni compiler. The results showed that the performance of the Lattice QCD mini-application using XMP was achieving more than 94% of the implementation written in MPI + OpenMP.

关键词： Knights Landing Cluster system PGAS language Compiler

来源：评论

学校读者我要写书评

暂无评论

Message from the workshop Chairs

Message from the Workshop Chairs

引用

international Symposium on Computer Architecture and High Performance computing (SBAC-PAD)

We are pleased to meet our community for the ninetieth edition of the workshop on Applications for multi-core Architectures (WAMCA), held together with the international Symposium on Computer Architectures and High Performance computing at Lyon, France. Since the advent of the multicore concept, significant advances have been made on many of the related aspects. multi-core has become a natural element in the HPC ecosystem, and its pervasiveness within the landscape of common computing devices has made it a standard. The available on-chip computing power is increasing through more CPUcores and more efficient memory systems. However, designing programs that keep scaling well on new generation multicore processors needs skilful investigations. WAMCA aims at providing an opportunity to address all related technical challenges and more, including reports on specific case studies and prospective studies.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Low-Latency Software LDPC Decoders for x86 multi-core Devices

Low-Latency Software LDPC Decoders for x86 Multi-core Device...

引用

ieee international workshop on Signal Processing systems (SiPS)

作者： Le Gal, Bertrand Jego, Christophe Univ Bordeaux IMS Lab Bordeaux INP Bordeaux France

ISBN: (纸本)9781538604465

LDPC codes are a family of error correcting codes used in most modern digital communication standards even in future 3GPP 5G standard. Thanks to their high processing power and their parallelization capabilities, prevailing multi-core and many-core devices facilitate real-time implementations of digital communication systems, which were previously implemented on dedicated hardware targets. Through massive frame decoding parallelization, current LDPC decoders throughputs range from hundreds of Mbps up to Gbps. However, inter-frame parallelization involves latency penalties, while in future 5G wireless communication systems, the latency should be reduced as far as possible. To this end, a novel LDPC parallelization approach for LDPC decoding on a multi-core processor device is proposed in this article. It reduces the processing latency down to some microseconds as highlighted by x86 multi-core experimentations.

关键词： Decoding Parity check codes Throughput Standards Program processors Parallel processing

来源：评论

学校读者我要写书评

暂无评论

Exploring Scalable Data Allocation and Parallel computing on NoC-based Embedded many cores 35

Exploring Scalable Data Allocation and Parallel Computing on...

引用

35th ieee international Conference on Computer Design (ICCD)

作者： Maruyama, Yuya Kato, Shinpei Azumi, Takuya Osaka Univ Grad Sch Engn Sci Suita Osaka Japan Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan

ISBN: (纸本)9781538622544

In embedded systems, high processing requirements and low power consumption need heterogeneous computing platforms. Considering embedded requirements, applications need to be designed based on scalable data allocation and parallel computing with non-uniform memory access (NUMA) many cores. In this paper, we use one of the embedded commercial off-the-shelf (COTS) multi/many-core components, the Massively Parallel Processor Arrays (MPPA) 256 developed by Kalray, and conduct evaluations of data transfer and parallelization of a practical application. We investigate currently achievable data transfer latencies between distributed memories on network-on-chip (NoC), memory access characteristics, and parallelization potential with many cores. Subsequently, we run a practical application, the core of the autonomous driving system, on many-core processors and acceleration by parallelization indicates practicality of many cores. By highlighting many-core computing capabilities, we explore the scalable data allocation and parallel computing on NoC-based embedded many cores.

关键词： Data transfer Hardware Embedded systems Computational modeling Parallel processing Routing Topology

来源：评论

学校读者我要写书评

暂无评论

Parallelizing and optimizing LHCb-Kalman for Intel Xeon Phi KNL processors 26

Parallelizing and optimizing LHCb-Kalman for Intel Xeon Phi ...

引用

26th Euromicro international Conference on Parallel, Distributed, and Network-Based Processing (PDP)

作者： Fernandez, Placido del Rio Astorga, David Dolz, Manuel F. Fernandez, Javier Awile, Omar Garcia, Daniel CERN EP LBC CH-1211 Geneva 23 Switzerland Univ Carlos III Madrid Dept Comp Sci Madrid Spain CERN IT CF FPP CH-1211 Geneva 23 Switzerland

ISBN: (纸本)9781538649756

Real time data processing is an important component of particle physics experiments with large computing resource requirements. As the Large Hadron Collider (LHC) at CERN is preparing for its next upgrade the LHCb experiment is upgrading its detector for a 30x increase in data throughput. In preparation for this upgrade the experiment is considering a number of architectural improvements encompassing both its software and hardware infrastructure. One of the hardware platforms under consideration is the Intel Xeon-Phi Knights Landing processor. Thanks to its on-package high-bandwidth memory and many-core architecture it offers an interesting alternative to more traditional server systems. We present a scalable, multi-threaded and NUMA-aware Kalman filter proto-application for particle track fitting expressed in terms of generic parallel patterns using the GRPPI interface. We show how code maintainability and readability improves, while maintaining comparable levels of performance to the baseline implementation. This is achieved by keeping the parallel algorithms in the underlying framework generic, but topology aware through the use of the Portable Hardware Locality (hwloc) library, which allows us to target different architectures with the same program. We measure the performance of our topology-aware GRPPI Kalman filter implementation on the Intel Xeon-Phi Knights Landing platform and conclude on the feasibility of integrating such high-level parallelization libraries in complex software frameworks such as LHCb's Gaudi framework.

关键词： NUMA affinity LHCb parallel patterns GRPPI Kalman filter knl multi-threading xeon phi

来源：评论

学校读者我要写书评

暂无评论

Thread- and Data-Level Parallel Simulation in SystemC, a Bitcoin Miner Case Study 19

Thread- and Data-Level Parallel Simulation in SystemC, a Bit...

引用

19th ieee international High Level Design Validation and Test workshop (HLDVT)

作者： Cheng, Zhongqi Schmidt, Tim Liu, Guantao Domer, Rainer Univ Calif Irvine Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA

ISBN: (纸本)9781509039975

The rapidly growing design complexity has become a big obstacle and dramatically increased the time required for SystemC simulation. In this case study, we exploit different levels of parallelism, including thread-and data-level parallelism, to accelerate the simulation of a Bitcoin miner model in SystemC. Our experiments are performed on two multi-core processors and one many-core Intel (R) Xeon Phi (TM) Coprocessor. Our results show that with the combination of data-and thread-level parallelism, the peak simulation speed improves by over 11x on a 4-core host, 50x on a 16-core host, and 510x on a 60-core host, respectively. The results confirm the efficiency of combining thread-and data-level parallelism for higher SystemC simulation speed, and can serve as a benchmark for future optimization of system level design, modeling, and simulation.

关键词： Bitcoin Parallel processing Computational modeling Peer-to-peer computing Instruction sets Synchronization Ports (Computers)

来源：评论

学校读者我要写书评

暂无评论

Process-Based Asynchronous Progress Model for MPI Point-to-Point Communication 19

Process-Based Asynchronous Progress Model for MPI Point-to-P...

引用

19th ieee international Conference on High Performance computing and Communications (HPCC) / 15th ieee international Conference on Smart City (SmartCity) / 3rd ieee international Conference on Data Science and systems (DSS)

作者： Si, Min Balaji, Pavan Argonne Natl Lab Argonne IL 60439 USA

ISBN: (纸本)9781538625880

The MPI two-sided communication model has been widely used in scientific applications for decades. The nonblock-hag version of the two-sided routines allows the application to potentially improve performance on many systems by overlapping communication and computation. In practice, unfortunately, the overlap is hard to achieve because of the limitations of the MPI internal progress engine and the underlying network. The traditional approach to resolving this issue is to implement an asynchronous progress engine based on either additional threads or hardware interrupts;however, such approaches may result in reduced computing power or expensive overheads. In this paper, we present a portable process-based asynchronous progress approach for two-sided communication in the PMPI-based Casper framework. It allows the user to specify an arbitrary number of cores on a multicore or many-core architecture and offload the point-to-point communication to these cores, thus ensuring asynchronous progress with low overhead. Unlike our previous work that supports asynchronous progress for the MPI one-sided model, a completely new design is needed for the message-matching-based two-sided model in order to ensure comprehensive semantics correctness as defined in the MPI standard. We present a detailed design of this two-sided model and compare it with the traditional thread-based approach on both a multicore Intel Xeon cluster and a many-core Knights Landing cluster.

关键词： Asynchronous progress MPI point-to-point two-sided communications multi-core many-core

来源：评论

学校读者我要写书评

暂无评论

international workshops on High Performance computing, ISC High Performance 2016 and workshop on 2nd international workshop on Communication Architectures at Extreme Scale, ExaComm 2016, workshop on Exascale multi/many core computing systems, E-MuCoCoS 2016, HPC I/O in the Data Center, HPC-IODC 2016, Application Performance on Intel Xeon Phi - Being Prepared for KNL and Beyond, IXPUG 2016, international workshop on OpenPOWER for HPC, IWOPH 2016, international workshop on Performance Portable Programming Models for Accelerators, P^3MA 2016, workshop on Virtualization in High-Performance Cloud computing, VHPC 2016, workshop on Performance and Scalability of Storage systems, WOPSSS 2016

International Workshops on High Performance Computing, ISC H...

引用

international workshops on High Performance computing, ISC High Performance 2016 and workshop on 2nd international workshop on Communication Architectures at Extreme Scale, ExaComm 2016, workshop on Exascale multi/many core computing systems, E-MuCoCoS 2016, HPC I/O in the Data Center, HPC-IODC 2016, Application Performance on Intel Xeon Phi – Being Prepared for KNL and Beyond, IXPUG 2016, international workshop on OpenPOWER for HPC, IWOPH 2016, international workshop on Performance Portable Programming Models for Accelerators, P^3MA 2016, workshop on Virtualization in High-Performance Cloud computing, VHPC 2016, workshop on Performance and Scalability of Storage systems, WOPSSS 2016

ISBN: (纸本)9783319460789

The proceedings contain 48 papers. The special focus in this conference is on E-MuCoCoS, ExaComm, HPC-IODC, IWOPH, IXPUG, WOPSSS and VHPC. The topics include: Behavioral emulation for scalable design-space exploration of algorithms and architectures;energy efficient runtime framework for exascale systems;extreme-scale in situ visualization of turbulent flows on IBM blue gene/Q JUQUEEN;work distribution of data-parallel applications on heterogeneous systems;automated communication characterization for HPC applications;an overview of the sirocco parallel storage system;data reduction for integrated application workflows and data storage;early application performance at the hartree centre with the OpenPOWER architecture;exploring energy efficiency for GPU-accelerated POWER Servers;high performance computing on the IBM power8 platform;performance analysis of Spark/GraphX on POWER8 cluster;application performance on intel xeon phi - being prepared for KNL and beyond;application suitability assessment for many-core targets and applying the roofline performance model to the Intel Xeon Phi knights landing processor.

关键词：

来源：评论

学校读者我要写书评

暂无评论

SALaR: Scalable and Adaptive Designs for Large Message Reduction Collectives

SALaR: Scalable and Adaptive Designs for Large Message Reduc...

引用

ieee international Conference on Cluster computing

作者： Mohammadreza Bayatpour Jahanzeb Maqbool Hashmi Sourav Chakraborty Hari Subramoni Pouya Kousha Dhabaleswar K. Panda Department of Computer Science and Engineering The Ohio State University

Message Passing Interface (MPI), thus far, has remained a dominant programming model to program large-scale scientific applications. Collective communication operations in MPI are of significant importance due to their communication intensive nature and use in scientific applications. With the emergence of multi-/many-core systems and rise of deep learning applications, it is important to revisit MPI collectives, particularly MPI Allreduce to exploit vast parallelism offered by modern architectures. In this paper, we take up this challenge and propose Scalable and Adaptive designs for Large message Reduction collectives (SALaR). We focus on MPI Allreduce due to its use in deep learning frameworks and propose new designs that can significantly improve its performance by exploiting architectural features of modern multi-/many-cores in tandem with high-throughput network such as InfiniBand. We also propose a theoretical model to analyze communication and computation cost and use these insights to guide our designs. The evaluation of the proposed SALaR based designs shows significant performance gains over state-of-the-art designs on a wide variety of micro-benchmarks and applications.

关键词： Peer-to-peer computing Computational modeling Libraries Software algorithms Tuning Pipeline processing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共98页 << < 19 20 21 22 23 24 25 26 27 28 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：