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Assessing sparse triangular linear system solvers on GPUs 29

Assessing sparse triangular linear system solvers on GPUs

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8th international Symposium on Computer Architecture and High Performance computing (SBAC-PADW)

作者： Erguiz, Daniel Dufrechou, Ernesto Ezzatti, Pablo Univ Republica Inst Comp Montevideo Uruguay

ISBN: (纸本)9781538648193

An important number of Numerical Linear Algebra methods to tackle problems in diverse fields of science and engineering, rely heavily on the solution of one or many sparse triangular linear systems. Since the early years, this has motivated numerous efforts that seek to produce efficient implementations of this kernel for most hardware platforms. However, this operation implies strong data dependencies and unbalanced computations that difficult the concurrency, specially when massively-parallel processors such as GPUs are employed. In this work we review the different techniques to expose the data parallelism in this operation with special attention to the many-core based proposals. Additionally, we experimentally evaluate the two most successful approaches, namely the routine that is included in CUSPARSE library and the synchronization free method of W. Liu et al. [1]. Finally, we advance in the characterization of the triangular sparse linear systems to select the best solver in each case.

关键词： graphic processors multi-core processors sparse triangular linear systems high performance

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ShenTu: Processing multi-Trillion Edge Graphs on Millions of cores in Seconds 18

ShenTu: Processing Multi-Trillion Edge Graphs on Millions of...

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ACM/ieee international Conference for High Performance computing, Networking, Storage, and Analysis

作者： Heng Lin Xiaowei Zhu Bowen Yu Xiongchao Tang Wei Xue Wenguang Chen Lufei Zhang Torsten Hoefler Xiaosong Ma Xin Liu Weimin Zheng Jingfang Xu Tsinghua University and Fma Technology Tsinghua University and Qatar Computing Research Institute Tsinghua University State Key Laboratory of Mathematical Engineering and Advanced Computing ETH Zurich Qatar Computing Research Institute National Research Centre of Parallel Computer Engineering and Technology Beijing Sogou Technology Development Co. Ltd

ISBN: (纸本)9781538683859

Graphs are an important abstraction used in many scientific fields. With the magnitude of graph-structured data constantly increasing, effective data analytics requires efficient and scalable graph processing systems. Although HPC systems have long been used for scientific computing, people have only recently started to assess their potential for graph processing, a workload with inherent load imbalance, lack of locality, and access irregularity. We propose ShenTu ⁸ the first general-purpose graph processing framework that can efficiently utilize an entire Petascale system to process multi-trillion edge graphs in seconds. ShenTu embodies four key innovations: hardware specialization, supernode routing, on-chip sorting, and degree-aware messaging, which together enable its unprecedented performance and scalability. It can traverse a record-size 70-trillion-edge graph in seconds. Furthermore, ShenTu enables the processing of a spam detection problem on a 12-trillion edge Internet graph, making it possible to identify trustworthy and spam webpages directly at the fine-grained page level.

关键词： Random access memory Servers Data analysis Supercomputers Task analysis Computer architecture Optimization supercomputer task analysis random access machine Computer Architecture Servers Data analysis core core samples Scalability Edge of a figure or solid Unsolicited electronic mail

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Proceedings of the 20th international workshop on Software and Compilers for Embedded systems, SCOPES 2017

Proceedings of the 20th International Workshop on Software a...

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20th international workshop on Software and Compilers for Embedded systems, SCOPES 2017

ISBN: (纸本)9781450350396

The proceedings contain 14 papers. The topics discussed include: numerical accuracy improvement by interprocedural program transformation;TETRiS: a multi-application run-time system for predictable execution of static mappings;robust mapping of process networks to many-core systems using bio-inspired design centering;constructing HPSSA over SSA;hybrid latency minimization approach using model checking and dataflow analysis;data dependent energy modeling for worst case energy consumption analysis;combining dataflow applications and real-time task sets on multi-core platforms;exploiting predictability in dynamic network communication for power efficient data transmission in LTE-radio systems;enabling zero-copy OpenMP offoading on the PULP many-core accelerator;automatic tuning with ordinal regression;the LPGPU2 project - low-power parallel computing on GPUs;automatic conversion of Simulink models to SysteMoC actor networks;on the accuracy of near-optimal GPU-based path planning for UAVs;and self-adaptive FPGA-based image processing filters using approximate arithmetics.

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Tiny Directory: Efficient Shared Memory in many-core systems with Ultra-low-overhead Coherence Tracking 23

Tiny Directory: Efficient Shared Memory in Many-core Systems...

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23rd ieee international Symposium on High Performance Computer Architecture (HPCA)

作者： Shukla, Sudhanshu Chaudhuri, Mainak Indian Inst Technol Kanpur Dept Comp Sci & Engn Kanpur Uttar Pradesh India

ISBN: (纸本)9781509049851

The sparse directory has emerged as a critical component for supporting the shared memory abstraction in multi-and many-core chip-multiprocessors. Recent research efforts have explored ways to reduce the number of entries in the sparse directory. These include tracking coherence of private regions at a coarse grain, not tracking blocks that belong to pages identified as private by the operating system (OS), and not tracking a subset of blocks that are speculated to be private by the hardware. These techniques require support for multi-grain coherence, assistance of OS, or broadcast-based recovery on sharing an untracked block that is wrongly speculated as private. In this paper, we design a robust minimally-sized sparse directory that can offer adequate performance while enjoying the simplicity, scalability, and OS-independence of traditional broadcast-free block-grain coherence. We begin our exploration with a naive design that does not have a sparse directory and the location/sharers of a block are tracked by borrowing a portion of the block's last-level cache (LLC) data way. Such a design, however, lengthens the critical path from two transactions to three transactions (two hops to three hops) for the blocks that experience frequent shared read accesses. We address this problem by architecting a tiny sparse directory that dynamically identifies and tracks a selected subset of the blocks that experience a large volume of shared accesses. We augment the tiny directory proposal with an option of selectively spilling into the LLC space for tracking the coherence of the critical shared blocks that the tiny directory fails to accommodate. Detailed simulation-based study on a 128-core system with a large set of multi-threaded applications spanning scientific, general-purpose, and commercial computing shows that our coherence tracking proposal operating with 1/32 X to 1/256 X sparse directories offers performance within a percentage of a traditional 2X sparse directory.

关键词： sparse directory cache coherence shared memory

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Right-sizing Geo-distributed Data Centers for Availability and Latency 37

Right-sizing Geo-distributed Data Centers for Availability a...

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37th ieee international Conference on Distributed computing systems (ICDCS)

作者： Narayanan, Iyswarya Kansal, Aman Sivasubramaniam, Anand Penn State Univ University Pk PA 16802 USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781538617915

We show cloud developers how to right size data center (DC) capacity for geo-distributed applications deployed on several multi-megawatt DCs, possibly also using many smaller edge DCs. Note that capacity considerations for a geo-distributed infrastructure do not decompose into individual DC capacity planning. When edge DCs are used, heterogeneous availability and costs affect the capacity split between the edge and core DCs. Non-uniform spatial distribution of clients and interdependence between latency and availability constraints make it non-trivial to provision the right capacity at each DC. We develop a geo-distributed capacity planning framework to capture the key factors that influence capacity, ranging from application demand patterns, latency and availability requirements, DC cost-availability trade-offs, and data replication overheads. We apply our framework to a realistic application and DC infrastructure setting to gather insights into how capacity should be provisioned and allocated across DCs for a representative set of requirements and costs.

关键词： Servers Cloud computing Capacity planning Cooling Biological system modeling Bandwidth Optimization

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Digital image processing through parallel computing in single-core and multi-core systems using MATLAB 2

Digital image processing through parallel computing in singl...

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2nd ieee international Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2017

作者： Reddy, Ritesh Kompala, Neeharika Ravi, Nitin Chaitanya Bharathi Institute of Technology India Chowdary Chaitanya Bharathi Institute of Technology India

ISBN: (纸本)9781509037049

Matlab by default is a single threaded application. so the single thread uses just one core irrespective of how many cores are available to run any simulation. Data analysis and visualization tool which has been designed with powerful support for matrices and matrix operations. when we talk here about digital image processing we basically refer to how we change the nature of the image either to improve its pictorial representation for better human understanding or to more suitable for machine interpretation. huge matrix calculations take place in matrix pixels, all these calculations are done in single core. here, we talk about three major digital image processing features provided by Matlab and how parallel computing feature provided by matlab helps its computational speed by decreasing the time of it execution. we compare matlab's performance on different systems using different number of cores. Overall the parallel computing tool in matlab helps in solving computationally intensive and data-intensive problems with much more ease and efficiency with regards to time. © 2017 ieee.

关键词： Parallel processing systems

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2013 ieee 6th international workshop on multi-/many-core computing systems, MuCoCoS 2013

2013 IEEE 6th International Workshop on Multi-/Many-Core Com...

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2013 ieee 6th international workshop on multi-/many-core computing systems, MuCoCoS 2013

ISBN: (纸本)9781479910106

The proceedings contain 8 papers. The topics discussed include: optimizing sparse matrix vector multiplication on emerging multicores;dataflow language compilation for a single chip massively parallel processor;multiscale dataflow computing;automatic extraction of multi-objective aware parallelism for heterogeneous MPSoCs;quantifying the performance impacts of using local memory for many-core processors;topology-aware equipartitioning with coscheduling on multicore systems;one OpenCL to rule them all?;algorithmic species revisited: a program code classification based on array references;towards a compiler/runtime synergy to predict the scalability of parallel loops;and ELB-trees: an efficient and lock-free B-tree derivative.

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Parallelization, Modeling, and Performance Prediction in the multi-/many core Area: A Systematic Literature Review 7

Parallelization, Modeling, and Performance Prediction in the...

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ieee 7th international Symposium on Cloud and Service computing (ieee SC2)

作者： Frank, Markus Hilbrich, Marcus Lehrig, Sebastian Becker, Steffen Tech Univ Chemnitz Chemnitz Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9781538658628

Context: Software developers face complex, connected, and large software projects. The development of such systems involves design decisions that directly impact the quality of the software. For an early decision making, software developers can use model-based prediction approaches for (non-)functional quality properties. Unfortunately, the accuracy of these approaches is challenged by newly introduced hardware features like multiple cores within a single CPU (multicores) and their dependence on shared memory and other shared resources. Objectives: Our goal is to understand whether and how existing model-based performance prediction approaches face this challenge. We plan to use gained insights as foundation for enriching existing prediction approaches with capabilities to predict systems running on multicores. Methods: We perform a Systematic Literature Review (SLR) to identify current model-based prediction approaches in the context of multicores. Results: Our SLR covers the software engineering, embedded systems, High Performance computing, and Software Performance Engineering domains for which we examined 34 sources in detail. We found various performance prediction approaches which tries to increase prediction accuracy for multicore systems by including shared memory designs to the prediction models. Conclusion: However, our results show that the memory designs models are only in an initial phase. Further research has to be done to improve cache, memory, and memory bandwidth model as well as to include auto tuner support.

关键词： Software multicore processing Predictive models Unified modeling language Parallel programming Hardware Computational modeling

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SWhybrid: A Hybrid-Parallel Framework for Large-Scale Protein Sequence Database Search 31

SWhybrid: A Hybrid-Parallel Framework for Large-Scale Protei...

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31st ieee international Parallel and Distributed Processing Symposium (IPDPS)

作者： Lan, Haidong Liu, Weiguo Liu, Yongchao Schmidt, Bertil Shandong Univ Jinan Shandong Peoples R China Georgia Tech Atlanta GA USA Johannes Gutenberg Univ Mainz Mainz Germany

ISBN: (纸本)9781538639146

Computer architectures continue to develop rapidly towards massively parallel and heterogeneous systems. Thus, easily extensible yet highly efficient parallelization approaches for a variety of platforms are urgently needed. In this paper, we present SWhybrid, a hybrid computing framework for large-scale biological sequence database search on heterogeneous computing environments with multi-core or many-core processing units (PUs) based on the SmithWaterman (SW) algorithm. To incorporate a diverse set of PUs such as combinations of CPUs, GPUs and Xeon Phis, we abstract them as SIMD vector execution units with different number of lanes. We propose a machine model, associated with a unified programming interface implemented in C++, to abstract underlying architectural differences. Performance evaluation reveals that SWhybrid (i) outperforms all other tested state-of-the-art tools on both homogeneous and heterogeneous computing platforms, (ii) achieves an efficiency of over 80% on all tested CPUs and GPUs and over 70% on Xeon Phis, and (iii) achieves utlization rates of over 80% on all tested heterogeneous platforms. Our results demonstrate that there is enough commonality between vector-like instructions across CPUs and GPUs that one can develop higher-level abstractions and still specialize with close-to-peak performance. SWhybrid is open-source software and freely available at https://github. com/turbo0628/swhybrid.

关键词： Biological sequence comparison CUDA SIMD Xeon Phi Heterogeneous computing

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Proceedings of ScalA 2017: 8th workshop on Latest Advances in Scalable Algorithms for Large-Scale systems - Held in conjunction with SC 2017: The international Conference for High Performance computing, Networking, Storage and Analysis

Proceedings of ScalA 2017: 8th Workshop on Latest Advances i...

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8th workshop on Latest Advances in Scalable Algorithms for Large-Scale systems, ScalA 2017 - Held in conjunction with the international Conference for High Performance computing, Networking, Storage and Analysis, SC 2017

ISBN: (纸本)9781450351256

The proceedings contain 10 papers. The topics discussed include: analyzing the criticality of transient faults-induced SDCs on GPU applications;a highly scalable, algorithm-based fault-tolerant solver for gyrokinetic plasma simulations;flexible batched sparse matrix-vector product on GPUs;parallel jaccard and related graph clustering techniques;leveraging NVLINK and asynchronous data transfer to scale beyond the memory capacity of GPUs;dynamic task discovery in PaRSEC- a data-flow task-based runtime;application of a communication-avoiding generalized minimal residual method to a gyrokinetic five dimensional eulerian code on many core platforms;snowpack: efficient parameter choice for GPU kernels via static analysis and statistical prediction;dynamic load balancing of massively parallel unstructured meshes;and investigating half precision arithmetic to accelerate dense linear system solvers.

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