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10th ieee international Symposium on Embedded multicore/many-core systems-on-Chip (MCSOC)

作者： Teich, Juergen Glass, Michael Roloff, Sascha Schroeder-Preikschat, Wolfgang Snelting, Gregor Weichslgartner, Andreas Wildermann, Stefan Friedrich Alexander Univ Erlangen Nurnberg Dept Comp Sci FAU Erlangen Germany Karlsruhe Inst Technol Dept Comp Sci D-76021 Karlsruhe Germany

ISBN: (纸本)9781509035311

The predictability of execution qualities including timeliness, power consumption, and fault-tolerability is of utmost importance for the successful introduction of multi-core architectures in embedded systems requiring guarantees rather than best effort behavior. Examples are real-time and/or safety-critical parallel applications. In particular for future many-core architectures, analysis tools for proving such properties to hold for a given application irrespective of other workload either suffer from computational complexity. Or, sound bounds are of no practical interest due to severe interferences of resources and software at multiple levels. In view of abundant computational and memory resources becoming available, we propose to apply the principles of invasive computing to avoid sharing of resources at run time as much as possible. We subsequently show that statically proven quality guarantees may be enforced on many multi-core architectures by a presented hybrid mapping approach. Rather than fixed resource mappings, this approach provides only constellations of resource allocations to the run-time system that searches for such constellations and assigns the invader a suitable claim of resources, if possible. We have implemented this hybrid approach and the interface to the language InvadeX10, a library-based extension of the X10 programming language. In this extension, so-called requirements on execution qualities such as deadlines (e.g., in the form of latency constraints) may be annotated to individual programs or even program segments. These are then translated into satisfying resource constellations that need to be found at run time prior to admitting a parallel application to start, respectively continue in view of required execution quality requirements. We give a real-world case study from the domain of heterogeneous robot vision to demonstrate the capabilities of this approach to guarantee statically analyzed best and worst-case timing requirements on

关键词： analysis dse invasive computing manycore predictability real time simulation x10

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User-space APIs for Dynamic Power Management in many-core ARMv8 computing Nodes 14

User-space APIs for Dynamic Power Management in Many-core AR...

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international workshop on Parallel Optimization using/for multi and many-core High Performance computing (POMCO) in conjunction with 14th international Conference on High Performance computing and Simulation (HPCS)

作者： Bortolotti, Daniele Tinti, Simone Altoe, Piero Bartolini, Andrea EEES DEI Univ Bologna Bologna Italy E4 Comp Engn Scandiano Italy Swiss Fed Inst Technol Integrated Syst Lab Zurich Switzerland

ISBN: (纸本)9781509020881

The push for energy-efficient and energyproportional computing nodes, together with the increasing number of cores integrated in the same silicon die has lead to computing nodes with fine grained power management capabilities. To unleash the potential of this HW design a novel user-space power management APIs is needed to bring fine-grain power management in the hands of the programmer. In this work we present a novel programming mechanism for energy efficiency which is build around novel user-space power management APIs suitable to be embedded in userspace applications. We evaluated its timing and power saving performance on a novel computing node based on Cavium ThunderX ARMv8-based many-cores SoC.

关键词： Power management

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Cache timing attacks on recent microarchitectures

Cache timing attacks on recent microarchitectures

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ieee international workshop on Hardware-Oriented Security and Trust (HOST)

作者： Alexandres Andreou Andrey Bogdanov Elmar Tischhauser Danmarks Tekniske Universitet Lyngby DK

ISBN: (纸本)9781538639306

Summary form only given: Cache timing attacks have been known for a long time, however since the rise of cloud computing and shared hardware resources, such attacks found new potentially devastating applications. One prominent example is S$A (presented by Irazoqui et al at S&P 2015) which is a cache timing attack against AES or similar algorithms in virtualized environments. This paper applies variants of this cache timing attack to Intel's latest generation of microprocessors. It enables a spy-process to recover cryptographic keys, interacting with the victim processes only over TCP. The threat model is a logically separated but CPU co-located attacker with root privileges. We report successful and practically verified applications of this attack against a wide range of microarchitectures, from a two-core Nehalem processor (i5-650) to two-core Haswell (i7-4600M) and four-core Skylake processors (i7-6700). The attack results in full key recovery. Compared to earlier processor generations, the attacks are more involved, but still of practical complexity, requiring between 2 19 and 2 21 encryptions. For the last two processors, the cache slice selection algorithm (CSSA) was not known before and had to be reverse engineered as part of this work. This is the first time CSSAs for the Skylake architecture are reported. Our attacks demonstrate that cryptographic applications in cloud computing environments using key-dependent tables for acceleration are still vulnerable even on recent architectures, including Skylake. Our reverse engineering of the CSSAs of these processors will also be beneficial for developers in many other contexts, for instance for implementing page colouring in modern operating systems.

关键词： Timing Cryptography Microarchitecture Cloud computing Computer architecture Hardware Microprocessors

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Parameter studies on heterogeneous computing infrastructures with the Scalarm platform 14

Parameter studies on heterogeneous computing infrastructures...

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作者： Krol, Dariusz Slota, Renata Kitowski, Jacek AGH Univ Sci & Technol Dept Comp Sci Krakow Poland AGH Univ Sci & Technol ACC Cyfronet AGH Krakow Poland

ISBN: (纸本)9781509020881

The main goal of this tutorial is to demonstrate the Scalarm platform as a tool supporting parameter studies on different computing infrastructures like clusters, grids and clouds. Parameter study (also called parameter sweep) is an approach where the same application is executed many times with different input parameter values. Afterwards, results from every execution are collected to identify trends or anomalies in the data that may lead to new insights. Despite their simplicity, parameter studies are commonly used in many fields of science, including computational fluid dynamics, particle physics, and discrete-event simulation. It is arguable the most popular way of scientific computing organization.

关键词： Discrete event simulation

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Network on chip and parallel computing in embedded systems 10

Network on chip and parallel computing in embedded systems

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10th ieee international Symposium on Embedded multicore/many-core systems-on-Chip (MCSOC)

作者： Belkacemi, Dihia Bouchebaba, Youcef Daoui, Mehammed Lalam, Mustapha Univ Tizi Ouzou Lab Rech Informat Tizi Ouzou Algeria ONERA Toulouse Toulouse France

ISBN: (纸本)9781509035311

In order to cope with the increasing application requirements, heterogeneous MPSoC are considered as the major solution of future embedded systems thanks to their advantages in performance and low power dissipation. However traditional communication infrastructure such as a bus or a point to point are not scalable and become communication bottleneck for large systems. Network on chip (NoC) architectures have been proposed to handle this communication problem. One of the most critical problem in NoC based heterogeneous MPSoC is how to map an application on this platform. Due to the large solution search space, design of tools that can automate this step is of major importance. In this paper, we present a new tool for mapping applications on NoC based heterogeneous MPSoC. A set of multi-objective optimization algorithms are used to explore the mapping space and to find a set of Pareto optimal solutions.

关键词： Network-on-chip

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Towards an Object Oriented Programming Framework for Parallel Matrix Algorithms 14

Towards an Object Oriented Programming Framework for Paralle...

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作者： Kutil, Rade Salzburg Univ Dept Comp Sci A-5020 Salzburg Austria

ISBN: (纸本)9781509020881

A C++ programming framework (Slabber) is introduced which supports matrix algorithms on distributed and shared memory parallel architectures in an object oriented way. It has the following goals: First, the algorithm implementation should be as convenient as possible by making parallelization details transparent to the algorithm implementation. Second, the choice of architecture (MPI or threads) and the choice of data distribution must not require changing or adapting the algorithm. These goals are achieved by a new approach to decompose matrix operations such as the matrix multiplication into communication free sub-operators, and letting the framework take care of data redistributions between those sub-operators. As a usage example, an iterative algorithm for the non-negative matrix decomposition is implemented using the framework, serving as a usage tutorial and performance test. The results are promising and improve over a straight forward ScaLapack implementation while providing a much cleaner and easier algorithm formulation.

关键词： programming framework MPI multi-core matrix automatic parallelization

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Community Detection in multi-Partite multi-Relational Networks Based on Information Compression

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NEW GENERATION computing 2016年第1-2期34卷 153-176页

作者： Liu, Xin Liu, Weichu Murata, Tsuyoshi Wakita, Ken Tokyo Inst Technol Grad Sch Informat Sci & Engn Dept Comp Sci Meguro Ku 2-12-1 Ookayama Tokyo 1528552 Japan JST CREST Chiyoda Ku Ks Gobancho 7 Tokyo 1020076 Japan Wuhan Univ Technol 122 Luoshi Rd Wuhan 430070 Hubei Peoples R China

Community detection in uni-partite single-relational networks which contain only one type of nodes and edges has been extensively studied in the past decade. However, many real-world systems are naturally described as multi-partite multi-relational networks which contain multiple types of nodes and edges. In this paper, we propose an information compression based method for detecting communities in such networks. Specifically, based on the minimum description length (MDL) principle, we propose a quality function for evaluating partitions of a multi-partite multi-relational network into communities, and develop a heuristic algorithm for optimizing the quality function. We demonstrate that our method outperforms the state-of-the-art techniques in both synthetic and real-world networks.

关键词： Community Detection Graph Mining Clustering multi-Partite multi-Relational Network Information Compression

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MetaMorph: A Library Framework for Interoperable Kernels on multi- and many-core Clusters

MetaMorph: A Library Framework for Interoperable Kernels on ...

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international Conference on High Performance computing, Networking, Storage and Analysis (SC)

作者： Helal, Ahmed E. Sathre, Paul Feng, Wu-Chun Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24061 USA Virginia Tech Dept Comp Sci Blacksburg VA USA

ISBN: (纸本)9781467388153

To attain scalable performance efficiently, the HPC community expects future exascale systems to consist of multiple nodes, each with different types of hardware accelerators. In addition to GPUs and Intel MICs, additional candidate accelerators include embedded multiprocessors and FPGAs. End users need appropriate tools to efficiently use the available compute resources in such systems, both within a compute node and across compute nodes. As such, we present MetaMorph, a library framework designed to (automatically) extract as much computational capability as possible from HPC systems. Its design centers around three core principles: abstraction, interoperability, and adaptivity. To demonstrate its efficacy, we present a case study that uses the structured grids design pattern, which is heavily used in computational fluid dynamics. We show how MetaMorph significantly reduces the development time, while delivering performance and interoperability across an array of heterogeneous devices, including multicore CPUs, Intel MICs, AMD GPUs, and NVIDIA GPUs.

关键词： parallel libraries performance portability programmability accelerators accelerator-aware MPI GPU MIC CUDA OpenCL OpenMP MPI structured grids exascale

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BoostNoC: Power Efficient Network-on-Chip Architecture for Near Threshold computing 35

BoostNoC: Power Efficient Network-on-Chip Architecture for N...

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35th ieee/ACM international Conference on Computer-Aided Design (ICCAD)

作者： Rajamanikkam, Chidhambaranathan Rajesh, J. S. Chakraborty, Koushik Roy, Sanghamitra Utah State Univ Elect & Comp Engn USU BRIDGE LAB Logan UT 84322 USA

ISBN: (纸本)9781450344661

While near threshold design space provides a promising approach towards energy-efficient computing, it is plagued by sub-optimal performance. Application characteristics and hardware non-idealities of conventional architectures (optimized for the nominal voltage) prevent us fromfully leveraging the potential of NTC systems. Further, the popular approach of increasing the computational core count to compensate for the performance loss severely burdens the on-chip communication fabric with an increased communication demand. In this work, we quantitatively analyze the performance bottleneck created by a conventional NoC architecture in many-core NTC systems. To reclaim the performance lost due to a sub-optimal NoC, we propose BoostNoC-a power efficient, multi-layered network-on-chip architecture. BoostNoC improves the system performance by nearly 2x over a conventional NTC system. Further, we improve the energy efficiency by 1.4x with the use of drowsy routers.

关键词： Network-on-chip

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Efficient parallelization of MATLAB stencil applications for multi-core clusters 6

Efficient parallelization of MATLAB stencil applications for...

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6th international workshop on Domain-Specific Languages and High-Level Frameworks for High Performance computing, WOLFHPC 2016

作者： Spazier, Johannes Christgau, Steffen Schnor, Bettina Institute for Computer Science University of Potsdam August-Bebel-Strasse 89 Potsdam14482 Germany

ISBN: (纸本)9781509061563

This paper presents the automatic parallelization of Stencil codes written in MATLAB for distributed systems. The compiler translates MATLAB source into C code and automatically parallelizes using MPI. For clusters of multi-cores, also a hybrid approach is presented where the generated code combines MPI and OpenMP parallelization. The parallelization concepts are evaluated with two stencil computation benchmarks. The automatically generated code not only outperforms the MATLAB code, but shows also a very good scaling. © 2016 ieee.

关键词： MATLAB

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