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Exploring the Potential of Error-permissive Communication in multi-FPGA-based Edge computing 15

Exploring the Potential of Error-permissive Communication in...

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15th ieee international Symposium on Embedded multicore/many-core systems-on-Chip, MCSoC 2022

作者： Ben Ahmed, Akram Takano, Ryousei Hirofuchi, Takahiro Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology 2-3-26 Aomi Koto-ku Tokyo Japan

ISBN: (纸本)9781665464994

In recent years, Edge computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on multi-FPGA systems which have gained significant attention in Edge computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%. © 2022 ieee.

关键词： Electric power utilization

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Evaluating HPX and Kokkos on RISC-V using an astrophysics application Octo-Tiger

Evaluating HPX and Kokkos on RISC-V using an astrophysics ap...

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2023 international Conference on High Performance computing, Network, Storage, and Analysis, SC workshops 2023

作者： Diehl, Patrick Daiss, Gregor Brandt, Steven Kheirkhahan, Alireza Kaiser, Hartmut Taylor, Christopher Leidel, John Center of Computation & Technology Louisiana State University Baton RougeLA United States Tactical Computing Labs LindsayTX United States

ISBN: (纸本)9798400707858

In recent years, computers based on the RISC-V architecture have raised broad interest in the high-performance computing (HPC) community. As the RISC-V community develops the core instruction set architecture (ISA) along with ISA extensions, the HPC community has been actively ensuring HPC applications and environments [10, 29] are supported. In this context, assessing the performance of asynchronous many-task runtime systems (AMT) is essential. In this paper, we describe our experience with porting of a full 3D adaptive mesh-refinement, multi-scale, multi-model, and multi-physics application, Octo-Tiger, that is based on the HPX AMT, and we explore its performance characteristics on different RISC-V systems. Despite the (limited) capabilities of the RISC-V test systems we used, Octo-Tiger already shows promising results and good scaling. We, however, expect that additional hardware support based on dedicated ISA extensions (such as single-cycle context switches, extended atomic operations, and direct support for HPX's global address space) would allow for even better performance results. © 2023 Owner/Author.

关键词： Computer architecture

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NSF/ieee-TCPP Curriculum on Parallel and Distributed computing for Undergraduates - Version II - Big Data, Energy, and Distributed computing 2023

NSF/IEEE-TCPP Curriculum on Parallel and Distributed Computi...

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54th Annual ACM SIGCSE Technical Symposium on Computer Science Education (SIGCSE TS)

作者： Prasad, Sushil Weems, Charles Sussman, Alan Gupta, Anshul Estrada, Trilce Vaidyanathan, Ramachandran Ghafoor, Sheikh Kant, Krishna Stunkel, Craig Univ Texas San Antonio San Antonio TX 78249 USA Univ Massachusetts Amherst MA 01003 USA Univ Maryland College Pk MD 20742 USA IBM Res Yorktown Hts NY USA Univ New Mexico Albuquerque NM 87131 USA Louisiana State Univ Baton Rouge LA 70803 USA Tennessee Technol Univ Cookeville TN USA Temple Univ Philadelphia PA 19122 USA NVIDIA St Louis MO USA

ISBN: (纸本)9781450394338

This special session will report on the updated NSF/ieee-TCPP Curriculum on Parallel and Distributed computing released in Nov 2020 by the Center for Parallel and Distributed computing Curriculum Development and Educational Resources (CDER). The purpose of the special session is to obtain SIGCSE community feedback on this curriculum in a highly interactive manner employing the hybrid modality and supported by a full-time CDER booth for the duration of SIGCSE. In this era of big data, cloud, and multi- and many-core systems, it is essential that the computer science (CS) and computer engineering (CE) graduates have basic skills in parallel and distributed computing (PDC). The topics are primarily organized into the areas of architecture, programming, and algorithms topics. A set of pervasive concepts that percolate across area boundaries are also identified. Version 1 of this curriculum was released in December 2012. That curriculum guideline has over 140 early adopter institutions worldwide and has been incorporated into the 2013 ACM/ieee Computer Science curricula. This Version-II represents a major revision. The updates have focused on enhancing coverage related to the topical aspects of Big Data, Energy, and Distributed computing. The session will also report on related CDER activities including a workshop series on a PDC institute conceptualization, developing a CE-oriented version of the curriculum, and identifying a minimal set of PDC topics aligned with ABET's exposure-level PDC requirements. The interested SIGCSE audience includes educators, authors, publishers, curriculum committee members, department chairs and administrators, professional societies, and the computing industry.

关键词： Education Undergraduate Curriculum Parallel and Distributed computing Bloom's Classification Learning Outcomes

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Leveraging the Compute Power of Two HPC systems for Higher-Dimensional Grid-Based Simulations with the Widely-Distributed Sparse Grid Combination Technique 23

Leveraging the Compute Power of Two HPC Systems for Higher-D...

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2023 international Conference for High Performance computing, Networking, Storage and Analysis, SC 2023

作者： Pollinger, Theresa Van Craen, Alexander Niethammer, Christoph Breyer, Marcel Pflüger, Dirk Institute for Parallel and Distributed Systems Universität Stuttgart Stuttgart Germany High Performance Computing Center Universität Stuttgart Stuttgart Germany

ISBN: (纸本)9798400701092

Grid-based simulations of hot fusion plasmas are often severely limited by computational and memory resources;the grids live in four- to six-dimensional space and thus suffer the curse of dimensionality. However, high resolutions are required to fully capture the physics of interest. The sparse grid combination technique is a multi-scale method in which many anisotropically coarse resolved grids are used to approximate a fine-scale solution - -and it alleviates the curse of *** paper presents the core concepts of the widely-distributed combination technique, which allows us to use the compute power and memory of more than one HPC system for the same simulation. We apply the sparse grid combination technique to a six-dimensional advection problem serving as a proxy for plasma simulations. The full-grid solution approximated by the combination technique would contain ≈ 5 ZB if computed with conventional grid-based methods. Even the combination technique simulation operates on ≈ 1 × 1011 double-precision degrees of freedom, or 988 GB, plus the supporting sparse grid data structures. We propose a new approach to divide the compute load between the two HPC systems, requiring only 76 GB to be exchanged. Based on this, we have realized the first synchronous combination technique simulation using two HPC systems, in our case the two German Tier-0 supercomputers HAWK and SuperMUC-NG. On two systems, the simulation can be computed at an average overhead of ≈ 35 % (108 s per combination step) for file I/O and transfer. The presented concepts apply to any pair of HPC systems if high-speed data transfer is possible. © 2023 ACM.

关键词： Supercomputers

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Modeling multi-Threaded Aggregated I/O for Asynchronous Checkpointing on HPC systems 22

Modeling Multi-Threaded Aggregated I/O for Asynchronous Chec...

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22nd international Symposium on Parallel and Distributed computing, ISPDC 2023

作者： Gossman, Mikaila J. Nicolae, Bogdan Calhoun, Jon C. Clemson University Holcombe Department of Electrical and Computing Engineering ClemsonSC29634 United States Argonne National Laboratory Mathematics and Computer Science Division LemontIL60439 United States

ISBN: (纸本)9798350341270

HPC systems encompass more components with each new generation. As a result, the process of interacting with stable storage systems like parallel file systems (PFS) becomes increasingly difficult. Larger systems often result in more frequent failures, increasing the need and frequency to incorporate fault-tolerant mechanisms. One example is checkpoint-restart (C/R), where applications or systems save their data to non-volatile storage devices, such as a PFS. On failure, the system or application is restored to a saved state and computation continues. Today, asynchronous C/R is gaining traction for its ability to checkpoint data to permanent storage concurrently with the application. However, asynchronous C/R brings about many new challenges. For starters, asynchronous C/R introduces complex resource contention between the application and the C/R implementation. Additionally, some implementations adopt file-per-process writing strategies, which overwhelm PFS' at high core counts. In this work, we explore how multi-threaded POSIX I/O impacts aggregated throughput. To this extent we characterize the influence of different I/O parameters, such as the number of writer threads and how they access storage devices, has on aggregated I/O. We use the information gathered in this study to identify best practices when performing aggregated I/O as a first step in designing an efficient I/O aggregation scheme for asynchronous C/R. © 2023 ieee.

关键词： Fault tolerance

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One Shot System Based Reliability Modelling And Analysis for Low-Cost Fault-Tolerant computing System Comprising of One Instruction cores

One Shot System Based Reliability Modelling And Analysis for...

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2022 international Conference on Smart Generation computing, Communication and Networking, SMART GENCON 2022

作者： Venkatesha, Shashikiran Parthasarathi, Ranjani Vellore Intitute of Technology Vellore India College of Engineering Guindy Anna University Chennai India

ISBN: (纸本)9781665454995

Rapid CMOS device size reduction resulted in billions of transistors on a chip have led to integration of many cores leading to many challenges such as increased power dissipation, thermal dissipation, occurrence of transient faults and permanent faults. In a multi-core scenario, the mitigation of transient faults and permanent faults at the core level using redundancy-based fault mitigation technique thereby improves the reliability of multi-core systems. In an asymmetric multi-core system, the smaller cores provide fault tolerance to larger cores is a core-level fault mitigation technique that has gained momentum and focus from a large number of researchers. The paper presents an economical, asymmetric multi-core system consisting of one instruction cores (MCS-OIC). The term 'Low Cost' signifies power and area consumed by MCS-OIC. In MCS-OIC, MIPS cores are the conventional core and OICs are support standby redundant core. OICs pro-vide functional support to conventional cores for shorter periods of time. Failure in Arithmetic Logic Unit to execute instructions result in transfer of operation codes to OIC. OIC executes failed instructions by the repeated execution of one instruction named 'subleq'. The behavior of OICs in MCS-OIC is modelled using a One-Shot System (OSS) model for reliability analysis. The OSS based reliability model allows effectively map the model parameters to core-level and functional-level probabilities to estimate the system reliability. Increase in number of OICs results in enhancement system reliability is validated using simulation results, thereby scalability of the MCS-OIC is observed. © 2022 ieee.

关键词： Redundancy

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Proceedings - 2022 ieee 15th international Symposium on Embedded multicore/many-core systems-on-Chip, MCSoC 2022

Proceedings - 2022 IEEE 15th International Symposium on Embe...

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15th ieee international Symposium on Embedded multicore/many-core systems-on-Chip, MCSoC 2022

ISBN: (纸本)9781665464994

The proceedings contain 58 papers. The topics discussed include: evaluating the optimal self-checking carry propagate adder for cryptographic processor;buffer allocation for exposed Datapath architectures;movie oriented positive negative emotion classification from EEG signal using wavelet transformation and machine learning approaches;design of reward functions for RL-based high-speed autonomous driving;a lightweight end-to-end network for wearing mask recognition on low-resolution images;automatic endometrial segmentation in ultrasound images using deep learning;fake image detection using an ensemble of CNN models specialized for individual face parts;exploring the potential of error-permissive communication in multi-FPGA-based edge computing;cluster based smart random walk for data aggregation in wireless sensor network;radar and camera fusion for object forecasting in driving scenarios;online image sensor fault detection for autonomous vehicles;and systolic array based convolutional neural network inference on FPGA.

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Performance Optimization and Analysis of the Unstructured Discontinuous Galerkin Solver on multi-core and many-core Architectures 24

Performance Optimization and Analysis of the Unstructured Di...

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24th ieee international Conference on High Performance computing and Communications, 8th ieee international Conference on Data Science and systems, 20th ieee international Conference on Smart City and 8th ieee international Conference on Dependability in Sensor, Cloud and Big Data systems and Application, HPCC/DSS/SmartCity/DependSys 2022

作者： Dai, Zhe Deng, Liang Wang, Yueqing Wang, Fang Li, Ming Zhang, Jian Computational Aerodynamics Institute China Aerodynamics Research and Development Center Mianyang China State Key Laboratory of Aerodynamics China Aerodynamics Research and Development Center Mianyang China

ISBN: (纸本)9798350319934

The discontinuous Galerkin (DG) algorithm is a representative high order method in Computational Fluid Dynamics (CFD) area which possesses considerable mathematical advantages such as high resolution, low dissipation, and dispersion. However, DG is rather computationally intensive to demonstrate practical engineering problems. This paper discusses the implementation of our in-house practical DG application in three different programming models, as well as some optimization techniques, including grid renumbering and mixed precision to maximize the performance improvements in a single node system. The experiment on CPU and GPU shows that our CUDA, OpenACC, and OpenMP-based code obtains a maximum speedup of 42.9x, 35.3x, and 8.1x compared with serial execution by the original application, respectively. Besides, we systematically compare the programming models in two aspects: performance and productivity. Our empirical conclusions facilitate the programmers to select the right platform with a suitable programming model according to their target applications. © 2022 ieee.

关键词： Graphics processing unit

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Maximizing multi-core Efficiency in BLAS: A Scalable Architecture for Performance

Maximizing Multi-Core Efficiency in BLAS: A Scalable Archite...

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ieee international Conference on High Performance computing workshops (HiPCW)

作者： Shivam Gautam Deeksha Goplani Darshan Patel Ragesh Hajela Masahiro Doteguchi Ikuo Miyoshi Priyanka Sharma Fujitsu Research of India Bangalore India Fujitsu Limited Japan

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

Basic Linear Algebra Subprograms (BLAS) operations are fundamental computational building blocks widely used in machine learning models and AI libraries. Among BLAS routines, General Matrix multiplication(GEMM) is one of the most computationally intensive tasks, making it crucial to leverage multi-core CPU systems for enhanced efficiency and speed. The existing threading architecture in OpenBLAS, a popular BLAS library, only allows for a single execution of GEMM at a time, which fails to meet the extensive computational requirements of modern applications. This limitation restricts parallelism and CPU core *** poster introduces a scalable and enhanced architecture in OpenBLAS that facilitates parallel BLAS executions with loosely coupled synchronization using POSIX conditional variables, thereby boosting performance and core utilization. With the proposed algorithmic changes to OpenBLAS, we have observed an average improvement of 30 % for matrix sizes of 128 and 256 on a 64-core AWS Graviton3 instance.

关键词： multicore processing Instruction sets High performance computing Conferences Computational modeling Computer architecture Linear algebra Parallel processing Libraries Synchronization

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Assessing the Role of Communication in Scalable multi-core Quantum Architectures

Assessing the Role of Communication in Scalable Multi-Core Q...

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ieee international Symposium on Embedded multicore Socs (MCSoC)

作者： Maurizio Palesi Enrico Russo Davide Patti Giuseppe Ascia Vincenzo Catania University of Catania Catania Italy

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

multi-core quantum architectures offer a solution to the scalability limitations of traditional monolithic designs. However, dividing the system into multiple chips introduces a critical bottleneck: communication between cores. This paper introduces qcomm, a simulation tool designed to assess the impact of communication on the performance of scalable multi-core quantum architectures. Qcomm allows users to adjust various architectural and physical parameters of the system, and outputs various communication metrics. We use qcomm to perform a preliminary study on how these parameters affect communication performance in a multi-core quantum system.

关键词： Wireless communication Measurement Quantum system Quantum computing Protocols multicore processing Electric breakdown Scalability Computer architecture Network architecture

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