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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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Proceedings - 2016 26th international workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016

Proceedings - 2016 26th International Workshop on Power and ...

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26th international workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016

ISBN: (纸本)9781509007332

The proceedings contain 47 papers. The topics discussed include: performance estimation of program partitions on multi-core platforms;pipelining for dual supply voltages;thermally-aware composite run-time CPU power models;investigation of electrical and thermal properties of carbon nanotube interconnects;multi-scale electrothermal simulation and modeling of resistive random access memory devices;thermoelectric effects in graphene and grapheme-based nanostructures using atomistic simulation;fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing;hold-time violation analysis and fixing in near-threshold region;and design challenges for near and sub-threshold operation: a case study with an ARM Cortex-M0+ based WSN subsystem.

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Ray-tracing domain decomposition methods for real-time simulation on multi-core and multi-processor systems

Ray-tracing domain decomposition methods for real-time simul...

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4th international workshop on Embedded multicore computing and Applications in conjunction with the 16th ieee international Conference on High Performance and Communications

作者： Magoules, Frederic Gbikpi-Benissan, Guillaume Callet, Patrick Technol Res Inst SystemX 8 Ave Vauve F-91120 Palaiseau France CentraleSupelec F-92295 Chatenay Malabry France

This paper describes the use of domain decomposition methods for accelerating wave physics simulation. Numerical wave-based methods provide more accurate simulation than geometrical methods, but at a higher computation cost as well. In the context of virtual reality, the quality of the results is estimated according to human perception, what makes geometrical methods an interesting approach for achieving real-time physically-based rendering. Here, we investigate a geometrical method based on both beams and rays tracing, which we enhance by two levels of parallel processing. Techniques from domain decomposition methods are coupled with classical parallel computing on both shared and distributed memory. Both optic and acoustic renderings are experimented to evaluate the acceleration impact of the domain decomposition scheme. Speedup measurements clearly show the efficiency of using domain decomposition methods for real-time simulation of wave physics. Copyright (C) 2015 John Wiley & Sons, Ltd.

关键词： ray-tracing beam-tracing parallel computing domain decomposition method wave propagation acoustic optic

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Evolutionary vs. Revolutionary interconnect technologies for future low-power multi-core systems 16

Evolutionary vs. Revolutionary interconnect technologies for...

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1st international workshop on Advanced Interconnect Solutions and Technologies for Emerging computing systems, AISTECS 2016

作者： Miorandi, Gabriele Tala, Mahdi Balboni, Marco Ramini, Luca Bertozzi, Davide ENDIF Engineering Department in Ferrara University of Ferrara Italy

ISBN: (纸本)9781450340847

Networks-on-chip (NoCs) are today at the core of multiand many-core systems, acting as the system-level integration framework. In order to support scaling to future device generations, NoCs will struggle to deliver the required communication performance within tight power budgets. In this respect, evolutionary as well as revolutionary interconnect technologies are currently being considered. On one hand, clockless handshaking materializes GALS systems that completely remove the system clock while reducing idle power to only the leakage power. On the other hand, the technology platform could be changed, by replacing electrical wires with optical links and networks. This paper provides a comprehensive power analysis of the two technologies under test on a path-by-path basis, by comparing them with each other and with a baseline synchronous NoC. The outcome of this paper can support the selection of interconnect solutions for future manycore systems where power is the primary concern, as well as the runtime selection policy of routing paths in the context of hybrid interconnect fabrics. © 2016 ACM.

关键词： Network-on-chip

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A Parallel Implementation of Reinforced Learning Model used in Analyzing Risky Decision Making 14

A Parallel Implementation of Reinforced Learning Model used ...

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international workshop on Parallel Optimization using/for multi and many-core High Performance computing (POMCO) in conjunction with 14th international Conference on High Performance computing and Simulation (HPCS)

作者： Gavirangaswamy, Vinay B. Gupta, Ajay Gupta, Aakash Western Michigan Univ Dept Comp Sci Kalamazoo MI USA Thredup Inc San Francisco CA USA

ISBN: (纸本)9781509020881

Analyzing datasets for Risky Decision Making (RDM) is a challenging task involving the identification of varied decision making patterns and the categorization of individuals. Researchers from various fields as diverse as psychology and marketing are actively working to identify suitable techniques, which will allow understanding decision making processes better. Researchers have commonly used machine learning algorithms to model decision making processes. However, the high computational costs of most machine learning algorithms make such endeavors challenging for increasingly large datasets. One of the most promising approaches is to use ensemble clustering for RDM analysis. Ensemble clustering is computationally intensive and thus we propose to improve its performance. Our study reveals that computational overhead is introduced through the use of dimensions in ensemble cluster RDM analyses. Improving performance requires more than the parallelization of individual clustering techniques of the ensemble. We therefore propose a FIFO queue based implementation for analyzing RDM datasets using a HPC cluster on a distributed system. Our technique is able to achieve almost a linear speedup (e.g. 44.79x using 48 MPI threads). Possible shortcomings of the proposed method, opportunities for future work, and alternative parallelization scenarios are also discussed in this paper.

关键词： component ensemble clustering application machine learning MPI multi-objective optimization parallel distributed processing risky decision making

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A Review of Lightweight Thread Approaches for High Performance computing

A Review of Lightweight Thread Approaches for High Performan...

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ieee international Conference on Cluster computing (CLUSTER)

作者： Castello, Adrian Pena, Antonio J. Seo, Sangmin Mayo, Rafael Balaji, Pavan Quintana-Orti, Enrique S. Univ Jaume 1 Castellon De La Plana Spain Barcelona Supercomp Ctr Barcelona Spain Argonne Natl Lab Argonne IL 60439 USA

ISBN: (纸本)9781509036530

High-level, directive-based solutions are becoming the programming models (PMs) of the multi/many-core architectures. Several solutions relying on operating system (OS) threads perfectly work with a moderate number of cores. However, exascale systems will spawn hundreds of thousands of threads in order to exploit their massive parallel architectures and thus conventional OS threads are too heavy for that purpose. Several lightweight thread (LWT) libraries have recently appeared offering lighter mechanisms to tackle massive concurrency. In order to examine the suitability of LWTs in high-level runtimes, we develop a set of microbenchmarks consisting of commonly-found patterns in current parallel codes. Moreover, we study the semantics offered by some LWT libraries in order to expose the similarities between different LWT application programming interfaces. This study reveals that a reduced set of LWT functions can be sufficient to cover the common parallel code patterns and that those LWT libraries perform better than OS threads-based solutions in cases where task and nested parallelism are becoming more popular with new architectures.

关键词： Libraries

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MUDVA: A multi-sensory dataset for the vehicular CPS applications 18

MUDVA: A multi-sensory dataset for the vehicular CPS applica...

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18th ieee international workshop on multimedia Signal Processing, MMSP 2016

作者： Alam, Kazi Masudul Hariz, Mohammed Bin Hosseinioun, Seyed Vahid Saini, Mukesh El Saddik, Abdulmotaleb Multimedia Computing Research Laboratory University of Ottawa OttawaON Canada Division of Engineering New York University Abu Dhabi Abu Dhabi United Arab Emirates

ISBN: (纸本)9781509037247

Vehicular Cyber-Physical System (VCPS) is a new trend in the research of the intelligent transport systems (ITS). In VCPS, vehicles work as a hub of sensors to collect interior and exterior information about the vehicle. Vehicles can use ad-hoc networking or 3G/LTE communication technology to share useful information with their neighboring vehicles or with the infrastructures to accomplish user safety, comfort, and entertainment tasks. In order to facilitate efficient sensor-services fusion in the VCPS applications, we need real life vehicular sensory datasets. While there has been many datasets containing vehicle mobility traces, there is hardly any that contains sensory information to be shared on the network. In this paper, we present a scenario specific modular dataset architecture along with some multi-sensory dataset modules. One of the dataset modules provides time synchronized multi-vehicle data including multi-view video, multi-directional sound, GPS, accelerometer, gyroscope, and magnetic field sensors. Each of the three vehicles recorded front, back, left, and right videos while moving closely in the suburban areas to let explore vehicular cooperative applications. Another module presents necessary tools and datasets to identify vehicular events such as acceleration, deceleration, turn, and no-turn events. We also present development details of a safety application using the presented datasets along with a list of other possible applications. © 2016 ieee.

关键词： Intelligent systems

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Proceedings - ieee international Conference on Cluster computing, ICCC

Proceedings - IEEE International Conference on Cluster Compu...

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2016 ieee international Conference on Cluster computing, CLUSTER 2016

ISBN: (纸本)9781509036530

The proceedings contain 81 papers. The topics discussed include: evaluation of topology-aware broadcast algorithms for dragonfly networks;compiler-assisted overlapping of communication and computation in MPI applications;vProbe: scheduling virtual machines on NUMA systems;GLAP: distributed dynamic workload consolidation through gossip-based learning;CORP: cooperative opportunistic resource provisioning for short-lived jobs in cloud systems;time optimization modeling for big data placement and analysis for geo-distributed data centers;reduced-precision floating-point formats on GPUs for high performance and energy efficient computation;conflict prediction-based transaction execution for transactional memory in multi-core in-memory databases;skyline service selection based on QoS prediction;minimizing CMT miss penalty in selective page-level address mapping table;efficient semantic-aware coflow scheduling for data-parallel jobs;spatial locality aware, fast, and scalable SLINK algorithm for commodity clusters;high throughput log-based replication for many small in-memory objects;TwinPCG: dual thread redundancy with forward recovery for preconditioned conjugate gradient methods;active learning in performance analysis;and dynamically building energy proportional data centers with heterogeneous computing resources.

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Improving the Accuracy of Intrusion Detection Using GAR-Forest with Feature Selection 4th

Improving the Accuracy of Intrusion Detection Using GAR-Fore...

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4th international Conference on Frontiers in Intelligent computing - Theory and Applications (FICTA)

作者： Kanakarajan, Navaneeth Kumar Muniasamy, Kandasamy Amrita Vishwa Vidyapeetham TIFAC CORE Cyber Secur Coimbatore 641112 Tamil Nadu India

ISBN: (纸本)9788132226956;9788132226932

Intrusion detection systems (IDS) are designed to detect malicious activities in a large-scale infrastructure. many classification methods have been proposed to improve the classification accuracy of IDS. In this paper, we have applied greedy randomized adaptive search procedure with annealed randomness-Forest (GAR-Forest), a novel tree ensemble technique, with feature selection to improve classification accuracy of IDS. GAR-forest uses metaheuristic GRASP with annealed randomness to increase the diversity of ensemble. We used NSL-KDD datasets to study the classification accuracy of GAR-forest for both binary and multi-class classification problems. The results show that GAR-forest performs better when compared with random forest, C4.5, naive Bayes and multilayer perceptron for binary and multi-class classification problem achieving 82.3989 and 77.2622% accuracy, respectively, while classifying test data. We have also applied feature selection procedures, such as information gain, symmetrical uncertainty and correlation-based feature subset, to select relevant features for improving the accuracy of GAR-forest. GAR-forest with symmetrical uncertainty yields 85.0559% accuracy using 32 features for binary classification problem and information gain yields accuracy of 78.9035% using 10 features for multi-class classification problem. GAR-forest is found to be relatively much faster than multilayer perceptron though it is slower than naive Bayes, random forest and C4.5 algorithm. The metaheuristic GRASP procedure enables GAR-forest to reach the global optimal solution which greedy deterministic approaches fail to reach.

关键词： Feature selection GAR-forest GRASP metaheuristic Intrusion detection system Random forest

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Proceedings of the 7th international workshop on Programming Models and Applications for multicores and manycores, PMAM 2016

Proceedings of the 7th International Workshop on Programming...

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7th international workshop on Programming Models and Applications for multicores and manycores, PMAM 2016

ISBN: (纸本)9781450319089

The proceedings contain 13 papers. The topics discussed include: an evaluation of emerging many-core parallel programming models;discovering pipeline parallel patterns in sequential legacy C++ codes;embedding semantics of the single-producer/single-consumer lock-free queue into a race detection tool;accelerating dynamic data race detection using static thread interference analysis;efficient parallelization of complex automotive systems;enhancing metaheuristic-based virtual screening methods on massively parallel and heterogeneous systems;parallel locality and parallelization quality;software-managed cache coherence for fast one-sided communication;multitasking real-time embedded GPU computing tasks;flow driven GPGPU programming combining textual and graphical programming;multi-GPU implementation of the horizontal diffusion method of the weather research and forecast model;and JParEnt: parallel entropy decoding for JPEG decompression on heterogeneous multicore architectures.

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A Novel Fault Tolerant Voter for Identical core in Satellite Application

A Novel Fault Tolerant Voter for Identical Core in Satellite...

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international Conference on Advanced Communication Control and computing Technologies (ICACCCT)

作者： Priya, P. Lakshmi Kirubanandasarathy, N. Syed Ammal Engn Coll Dept ECE Ramanathapuram India

ISBN: (纸本)9781467395458

As the most quantitative measures of VLSI enactment have enhanced by many orders of level and it has been accomplished by the persistent scaling of the sizes of MOSFETs. However, scaling also impairs fault, noise and reliability issues, thus pretense new challenges in digital circuit design and system. Reliability becomes a foremost concern due to many and often correlated factors, such constraints and/or engineering deviations, aging and soft errors. A Defect and/or fault tolerance may be necessary at several levels throughout the system to improve the reliability of the system. Generally a fault tolerance technique is used to improve the reliability. Quadded logic (QL) is an interwoven redundant logic technique while Quadded Transistor (QT) corrects errors while performing the function of a circuit. The proposed Quadded logic Quadded transistor (QLQT) technique with multi voltage logic to reduce the power consumption and design half adder using this technique. To implement this technique in multiple identical core, TMR is introduced that allows the core to be efficiently tested. A scan chain based technique is employed to recover multiple errors in Triple modular redundancy (TMR) systems. This technique makes use of the scan chain flipflops that are employed to recover the correct state of a Triple Modular Redundancy system in the presence of temporary or permanent errors. This technique can detect both permanent faults and transient faults. Also a fault tolerant voter identifies multiple faults. The proposed technique improves reliability and reduce the fault. The proposed method is simulated by using Xilinx simulator.

关键词： Quadded logic Quadded Transistor Triple modular redundancy

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