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High-performance many-core networking: Design and implementation 2

High-performance many-core networking: Design and implementa...

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2nd workshop on Innovating the Network for Data-Intensive Science, INDIS 2015

作者： Ros-Giralt, Jordi Commike, Alan Honey, Dan Lethin, Richard Reservoir Labs 632 Broadway New YorkNY10012 United States

ISBN: (纸本)9781450340021

Operating systems play a key role in providing general purpose services to upper layer applications at the highest available performance level. The two design requirements - generality and performance - are however in contention: the more general purpose a service layer is, the more overhead it incurs in accessing domain-specific high-performance features provided by the layers beneath it. This trade-off comes to manifest in modern computer systems as the state-of-the-art has evolved from architectures with a few number of cores to systems employing a very large number of cores (many-core systems). Such evolution has rendered the networking layer in current operating systems inefficient as its general purpose design deprives it from a proper use of the large number of cores. In this paper we introduce DNAC (Dynamic Network Acceleration for many-core), a high-performance abstraction layer designed to target the maximum network performance available from the network interface in many-core general purpose operating systems. © 2015 ACM.

关键词： Closed loop control systems

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Customizable Heterogeneous Acceleration for Tomorrow's High-Performance computing 17

Customizable Heterogeneous Acceleration for Tomorrow's High-...

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2015 ieee 17th international Conference on High Performance computing and Communications (HPCC)

作者： Cilardo, Alessandro Flich, Jose Gagliardi, Mirko Gavila, Rafael T. Univ Naples Federico II DIETI Naples Italy Univ Politecn Valencia GAP Valencia Spain

ISBN: (纸本)9781479989379

High-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. This paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based manycore system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. The paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to FPGAs, might play for tomorrow's high-performance computing.

关键词： field programmable gate arrays graphics processing units multiprocessing systems network-on-chip parallel processing power aware computing quality of service FPGA GPU-like processors NoC-based many-core system QoS-sensitive computing customizable heterogeneous acceleration heterogeneous acceleration heterogeneous manycore systems high-level design principles high-performance computing innovative architecture medium-end CPU multicore processors power-efficient high-performance computing reconfigurable hardware regions Acceleration Computer architecture Field programmable gate arrays Hardware Program processors Quality of service Registers Field programmable gate arrays High Performance computing Quality of service power aware computing Program processors multiprocessing systems network-on-chip Computer Architecture Registers acceleration PARALLEL PROCESSING (COMPUTERS) multi-core processors Computer hardware Graphics Processing Unit

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Heterogeneous programming with Single Operation multiple Data

Heterogeneous programming with Single Operation Multiple Dat...

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Paulino, Herve Marques, Eduardo Univ Nova Lisboa Fac Ciencias & Tecnol Dept Informat CITI P-2829516 Caparica Portugal

Heterogeneity is omnipresent in today's commodity computational systems, which comprise at least one Central Processing Unit (CPU) and one Graphics Processing Unit (GPU). Nonetheless, all this computing power is not being harnessed in mainstream computing, as the programming of these systems entails many details of the underlying architecture and execution models. Current research on parallel programming is addressing these issues but, still, the system's heterogeneity is exposed at language level. This paper proposes a uniform framework, grounded on the Single Operation multiple Data model, for the programming of such heterogeneous systems. We designed a simple extension of the Java programming language that embodies the model, and developed a compiler that generates code for both multi-core CPUs and GPUs. A performance evaluation attests that, despite being based on a simple programming model, the approach is able to deliver performance gains on par with hand-tuned data-parallel multi-threaded Java applications. (c) 2014 Elsevier Inc. All rights reserved.

关键词： Data parallelism Single Operation multiple Data multi-cores GPUs

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A Dynamic Contention-aware Application Allocation Algorithm for many-core Processor 17

A Dynamic Contention-aware Application Allocation Algorithm ...

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2015 ieee 17th international Conference on High Performance computing and Communications (HPCC)

作者： Wang, Chang Zhu, Yongxin Jiang, Jiang Liu, Xu Han, Xing Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn 800 DongChuan Rd Shanghai Peoples R China

ISBN: (纸本)9781479989379

Concurrently executing diverse independent applications on a many-core processor with hundreds of cores requests allocating application tasks to minimize communication contention and communication cost. In this paper, we propose a novel application allocation algorithm to assign applications onto a many-core processor with considering communications between tasks and contentions on network channels. Our dynamic contention-aware application allocation (DC3A) algorithm focuses on reducing both external/internal communication contentions and communication cost on network by adopting a novel edge-centric method to delicately arrange positions of tasks of an application to form a specific rectangular mapping and an efficient method to select a rectangular resource region composed of available cores to allocate the application based on the mapping. In order to evaluate DC3A, we have implemented new thread spawning/joining modules and multi-application synchronization modules in Graphite simulator. The simulation results of DC3A and peer algorithms illustrate that with the increase of communication density, DC3A can better optimize the network performance. We have observed a reduction of average packet latency (APL) at most up to 35.6%, 32.6% and 24.6% when compared with first free (FF) algorithm, nearest neighbour (NN) algorithm and contiguous neighborhood allocation (CoNA) algorithm, respectively.

关键词： many-core processor dynamic application allocation edge-centric region forming rectangular region selection contention-aware

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A framework to the design and programming of many-core focal-plane vision processors 13

A framework to the design and programming of many-core focal...

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13th international Conference on Embedded and Ubiquitous computing (EUC 2015)

作者： Mori, Jones Y. Llanos, Carlos Huebner, Michael Ruhr Univ Bochum Chair Embedded Syst Informat Technol ESIT Bochum Germany Univ Brasilia Dept Mech Engn BR-70910900 Brasilia DF Brazil

ISBN: (纸本)9781467382991

The Focal-Plane Image Processing area aims to bring processing elements as near as possible to the pixels and to the camera's focal-plane. Most of the works reported in the literature uses only simple processing elements, in general analog ones, with few flexibility. With the technology advances, a new generation of Vision Processors is emerging. It is expected that multi/many-core systems will be integrated to the pixel sensors, offering several opportunities for parallelism exploration, resulting in high performance and flexible processing systems. The programmability is one of the main problems in this area, since most programmers are not able to create parallel algorithms and applications. In this work, we propose a methodology to the design and programming of many-core focal-plane vision processors. The application is described using a Domain Specific Language, from which the parallelism characteristics are extracted. Afterwards, a new abstract model is derived using techniques such as Program Slicing (PS) and Task-Graph Clustering (TGC). The abstract model is then transformed in a SystemC/TLM2.0 description, in order to allow for different timing accuracy simulations. The results of the simulations are used together with an ASIP design tool in order to determine both the microarchitecture of processing elements and the communication structure of the new system. Finally, from the model derived before, a new source code is generated and programmed into the new platform. In this context, the main concepts and ideas are described in this work, as well as some partial results.

关键词： Real-Time computer vision embedded computing focal-plane image processing many-core architecture Embedded computing images computer vision Programming communication structure core construction PROCESSOR Sight pixel Processing Element Microarchitecture Parallel algorithms Real time

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Preparing for exascale: Modeling MPI for many-core systems using fine-grain queues 3

Preparing for exascale: Modeling MPI for Many-core systems u...

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3rd workshop on Exascale MPI, ExaMPI 2015

作者： Bridges, Patrick G Dosanjh, Matthew G.F. Grant, Ryan Skjellum, Anthony Farmer, Shane Brightwell, Ron Department of Computer Science University of New Mexico United States Scalable System Software Department Sandia National Laboratories United States Department of Computer Science and Software Engineering Auburn University United States

ISBN: (纸本)9781450339988

This paper presents a fine-grain queueing model of MPI point-To-point messaging performance for use in the design and analysis of current and future large-scale computing sys-Tems. In particular, the model seeks to capture key perfor-mance behavior of MPI communication on many-core sys-Tems. We demonstrate that this model encompasses key MPI performance characteristics, such as short/long proto-col and offoad/onload protocol tradeos, and demonstrate its use in predicting the potential impact of architectural and software changes for many-core systems on communication performance. In addition, we also discuss the limitations of this model and potential directions for enhancing its fi-delity. © 2015 ACM.

关键词： Queueing theory

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An Empirical Study of Performance, Power Consumption, and Energy Cost of Erasure Code computing for HPC Cloud Storage systems 10

An Empirical Study of Performance, Power Consumption, and En...

引用

ieee international Conference on Networking, Architecture and Storage (NAS 2015)

作者： Chen, Hsing-bung Grider, Gary Inman, Jeff Fields, Parks Kuehn, Jeff Alan Los Alamos Natl Lab Los Alamos NM 87545 USA

ISBN: (纸本)9781467378918

Erasure code storage systems are becoming popular choices for cloud storage systems due to cost-effective storage space saving schemes and higher fitult-resilience capabilities. Both erasure code encoding and decoding procedures are involving heavy array, matrix, and table-lookup compute intensive operations. multi-core, many-core, and streaming SIMD extension are implemented in modern CPU designs. In this paper, we study the power consumption and energy efficiency of erasure code computing using traditional Intel x86 platform and Intel Streaming SIMD extension platform. We use a breakdown power consumption analysis approach and conduct power studies of erasure code encoding process on various storage devices. We present the impact of various storage devices on erasure code based storage systems in terms of processing time, power utilization, and energy cost. Finally we conclude our studies and demonstrate the Intel x86's Streaming SIMD extensions computing is a cost-effective and favorable choice for future power efficient HPC cloud storage systems.

关键词： Erasure code SIMD Vectorization Power measurement Energy cost Power consumption Cloud storage

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Top-down profiling of application specific many-core neuromorphic platforms 9

Top-down profiling of application specific many-core neuromo...

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9th ieee international Symposium on Embedded multicore/manycore systems-on-Chip (MCSoC)

作者： Urgese, Gianvito Barchi, Francesco Macii, Enrico Politecn Torino Dept Control & Comp Engn DAUIN Cso Duca degli Abruzzi 24 I-10129 Turin Italy

ISBN: (纸本)9781479986705

In this paper we present a top-down methodology aimed at evaluating the scalability of Spiking Neural Network (SNN) simulations on massively many-core and densely interconnected platforms. Spiking neural networks mimic brain activity by emulating spikes sent among neurons populations. many-core platforms are emerging computing targets to achieve real-time simulation SNN. Neurons are mapped to parallel cores and spikes are sent over the on-chip and off-chip network. However, due to the heterogeneity and complexity of neuron population activity, achieving an efficient exploitation of platforms resources is a challenging problem, often impacting simulation reliability and limiting the biological network size. To address this challenge, the proposed methodology, based on customized SNN configurations, extracts detailed profiling information about network usage of on-chip and off-chip resources. We first show the results of the application of our methodology to the SpiNNaker neuromorphic many-core platform. Then, we demonstrate how the profiling information can be used to improve the reliability of biologically plausible SNN simulations.

关键词： multiprocessing systems neural nets SNN configuration SpiNNaker neuromorphic many-core platform application specific many-core neuromorphic platform biologically plausible SNN simulation densely interconnected platforms neuron population activity spiking neural network top-down profiling Analytical models Biological system modeling Brain modeling Neurons Routing Sociology Statistics many-core multi-chip Neuromorphic Profiling Neural network Brain modeling Biological system modeling multiprocessing systems Neuromorphics Sociology ANALYSIS MODELS Neurons Network routing SNN gene Platform

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WISE-SPL: Bringing multi-tenancy to the Weather InSights Environment System 5

WISE-SPL: Bringing Multi-tenancy to the Weather InSights Env...

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ieee/ACM 5th international workshop on Product Line Approaches in Software Engineering (PLEASE)

作者： Segura, Vinicius C. V. B. Tizzei, Leonardo P. Ramirez, Joao Paulo de F. dos Santos, Marcelo N. Azevedo, Leonardo G. Cerqueira, Renato F. de G. IBM Res 146 Pasteur Ave BR-22290240 Rio De Janeiro Brazil

ISBN: (纸本)9781467370615

Weather conditions affect many cities and companies. The WISE (Weather InSights Environment) system serves as a central place to gather and present weather related information for decision makers. It was initially developed to fit a single tenant. Due to a multi-tenant opportunity, WISE is evolving to be deployed on a Cloud environment to support on-demand computing resources and multiple clients. Software product line techniques were applied to model common and variable features of tenants. WISE-SPL enables the derivation of products for each client and also the deployment on Cloud infrastructure. The contribution of this work is a demonstration and discussion of benefits and limitations in applying SPL techniques, following a extractive approach, to build a multi-tenant Cloud application.

关键词： cloud scientific application software product line weather application Clouds environment systems Software product lines decision makers Weather Clients customers weather condition

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Local parallelization of pleasingly parallel stream processing on multiple CPU cores

Local parallelization of pleasingly parallel stream processi...

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international Conference and workshop on computing and Communication (IEMCON)

作者： Ruediger Gad Martin Kappes Inmaculada Medina-Bulo Terma GmbH Space Darmstadt Germany Frankfurt University of Applied Sciences Frankfurt am Main Germany Universidad de Cádiz Cádiz Spain

ISBN: (纸本)9781509009978

Data stream processing addresses the need for high-throughput near real-time data processing, which can be considered as one part of Big Data or Fast Data. In this paper, we study the local parallelization of stream processing on a single multi-core Central Processing Unit (CPU) computer system, which, in our opinion, was not sufficiently addressed yet. In distributed systems, optimizing the local throughput can help to improve the overall system. In less resource demanding scenarios, it may be beneficial to use more lightweight local parallelization instead of more complex distributed approaches. We present our work-in-progress on locally parallelizing stream processing on multiple CPU cores and on ways for further improving the local data processing. In order to study the fundamental mechanisms and effects, we focused on pleasingly parallel workloads. While pleasingly parallel tasks, by definition, can be easily parallelized, our results show that stream processing adds important aspects and that the outcomes strongly vary depending on use case and parallelization approach. Furthermore, we present early stages of a stream transformation Domain Specific Language and of a self-adaptive mechanism for easing and optimizing the processing. We published our implementations as Open Source Software.

关键词： Pipelines Data processing Throughput Central Processing Unit DSL Parallel processing Concurrent computing

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