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Pool Directory: Efficient Coherence Tracking with Dynamic Directory Allocation in many-core systems 33

Pool Directory: Efficient Coherence Tracking with Dynamic Di...

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33rd ieee international Conference on Computer Design (ICCD)

作者： Shukla, Sudhanshu Chaudhuri, Mainak Indian Inst Technol Dept Comp Sci & Engn Kanpur 208016 Uttar Pradesh India

ISBN: (纸本)9781467371667

The coherence directory in a chip-multiprocessor keeps track of each memory block inside the cache hierarchy and plays a significant role in offering a scalable shared memory abstraction in many-core systems. multi-threaded applications typically require two types of directory entries, namely, limited pointer entries tracking a few sharers of a block and bitvector entries tracking larger number of sharers for widely shared blocks. Recent proposals aiming to optimize the average number of bits per directory entry have organized the directory as either a static mix of these two types of entries or a collection of relatively short bitvector entries that can encode either a limited number of sharer pointers or a larger number of sharers hierarchically. In this paper, we present a directory organization that facilitates allocation of two different types of directory entries dynamically. Our design maintains a pool of limited pointer entries, where each entry can also double as a segment directory entry encoding the sharers in a cluster of cores. Each tag in the primary sparse directory array has a pointer that can either represent a sharer or point to an entry in the pool. When multiple segment directory entries are needed to encode all the sharers of a block, our pool management protocol guarantees that all these entries are allocated contiguously so that maintaining a pointer to the head entry is enough. Such a design offers significant flexibility in sharer encoding and allows us to independently size the sparse directory array and the pool. Detailed simulation results show that our proposal incorporated in a 128-core system running multi-threaded applications drawn from scientific, general-purpose, and commercial computing domains can offer, on average, 5% improvement in performance and 20% savings in interconnect traffic compared to the state-of-th-eart scalable coherence directory ( SCD) proposal when using a 1/16 x sparse directory.

关键词： many-core coherence dynamic directory allocation directory scalability

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Fast and Accurate Support Vector Machines on Large Scale systems

Fast and Accurate Support Vector Machines on Large Scale Sys...

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ieee international Conference on Cluster computing (CLUSTER)

作者： Vishnu, Abhinav Narasimhan, Jeyanthi Holder, Lawrence Kerbyson, Darren Hoisie, Adolfy Pacific NW Natl Lab Adv Comp Math & Data Div 902 Battelle Blvd Richland WA 99352 USA Washington State Univ Sch Elect Engn & Comp Sci Pullman WA 99164 USA

ISBN: (纸本)9781467365987

Support Vector Machines (SVM) is a supervised Machine Learning and Data Mining (MLDM) algorithm, which has become ubiquitous largely due to its high accuracy and obliviousness to dimensionality. The objective of SVM is to find an optimal boundary - also known as hyperplane - which separates the samples (examples in a dataset) of different classes by a maximum margin. Usually, very few samples contribute to the definition of the boundary. However, existing parallel algorithms use the entire dataset for finding the boundary, which is sub-optimal for performance reasons. In this paper, we propose a novel distributed memory algorithm to eliminate the samples which do not contribute to the boundary definition in SVM. We propose several heuristics, which range from early (aggressive) to late (conservative) elimination of the samples, such that the overall time for generating the boundary is reduced considerably. In a few cases, a sample may be eliminated (shrunk) pre-emptively - potentially resulting in an incorrect boundary. We propose a scalable approach to synchronize the necessary data structures such that the proposed algorithm maintains its accuracy. We consider the necessary trade-offs of single/multiple synchronization using in-depth time space complexity analysis. We implement the proposed algorithm using MPI and compare it with libsvm - de facto sequential SVM software - which we enhance with OpenMP for multi-core/many-core parallelism. Our proposed approach shows excellent efficiency using up to 4096 processes on several large datasets such as UCI HIGGS Boson dataset and Offending URL dataset.

关键词： computational complexity data analysis data mining data structures distributed memory systems learning (artificial intelligence) parallel algorithms support vector machines synchronisation MLDM algorithm MPI OpenMP UCI HIGGS Boson dataset boundary definition distributed memory algorithm hyperplane large scale systems many-core parallelism multicore parallelism multiple synchronization offending URL dataset sequential SVM software single synchronization supervised machine learning and data mining algorithm time-space complexity analysis Accuracy Algorithm design and analysis Complexity theory Data structures Kernel Machine learning algorithms Support vector machines Extreme Scale Support Vector Machines Support Vector Network Data structures Parallel algorithms large-scale systems message passing mannose phosphate isomerase remote procedure calls Algorithm design and analysis distributed memory systems Hyperplane Machine learning algorithms Complexity theory data mining complexity classes

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The (Low) Power of Less Wiring: Enabling Energy Efficiency in many-core Platforms Through Wireless NoC 34

The (Low) Power of Less Wiring: Enabling Energy Efficiency i...

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34th ieee/ACM international Conference on Computer-Aided Design (ICCAD)

作者： Pande, Partha Pratim Kim, Ryan Gary Choi, Wonje Chen, Zhuo Marculescu, Diana Marculescu, Radu Washington State Univ Sch EECS Pullman WA 99164 USA Carnegie Mellon Univ Dept ECE Pittsburgh PA 15213 USA

ISBN: (纸本)9781467383882

During the last decade, we have witnessed a major transition from computation-to communication-centric design of integrated circuits and systems. In particular, the network-on-chip (NoC) approach has emerged as the major design paradigm for multicore systems-on-chip (SoC). The major challenges in traditional wire-based NoCs are the high latency and power consumption of the multi-hop links. By inserting single-hop long-range wireless links in place of multihop wired links, the overall system performance can be significantly improved. We should adopt novel architectures inspired by the on-chip wireless links to design high-performance multi-core chips. In this regard, the small-world network-inspired wireless NoC (WiNoC) has emerged as an enabling interconnection infrastructure to design high-bandwidth and energy-efficient multicore chips. In this paper we present the various challenges and possible solutions for designing energy-efficient massive multicore chips enabled by the WiNoC paradigm.

关键词： NoC VFI Dynamic V/F Wireless multicore Low-power

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Fault tolerance features of a new multi-SPMD programming/execution environment 1

Fault tolerance features of a new multi-SPMD programming/exe...

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1st international workshop on Extreme Scale Programming Models and Middleware, ESPM2 2015

作者： Tsuji, Miwako Petiton, Serge Sato, Mitsuhisa RIKEN Advanced Institute for Computational Science University of Tsukuba Japan University Lille 1 Sciences and Technologies CNRS/LIFL CNRS/Maison de la Simulation France

ISBN: (纸本)9781450339964

Supercomputers in the exascale era would consist of a huge number of nodes arranged in a multi-level hierarchy. There are many important challenges to exploit such systems such as scalability, programmability, reliability and energy effi- ciency. In the previous work, we had focused on the scalability and programmability. We had proposed FP2C (Framework for Post-Petascale computing), which is a development and execution environment based on workow and PGAS (Partitioned Global Address Space) programming models for parallel programming. In this paper, we focus on the reliability. We extend FP2C by adding a fault detection capability to the middleware of FP2C and by incorporating fault resilience scheduling policy into the workow scheduler. Using the extended FP2C, fault tolerance can be achieved without modifying applications. © 2015 ACM.

关键词： Fault tolerance

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Proceedings of the 6th international workshop in Performance Modeling, Benchmarking and Simulation of High Performance Computer systems, PMBS 2015 - Held as part of ACM/ieee Supercomputing 2015, SC 2015

Proceedings of the 6th International Workshop in Performance...

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6th international workshop in Performance Modeling, Benchmarking and Simulation of High Performance Computer systems, PMBS 2015 - Held as part of the 27th ACM/ieee international Conference for High Performance computing, Networking, Storage and Analysis, SC 2015

ISBN: (纸本)9781450340090

The proceedings contain 9 papers. The topics discussed include: performance evaluation of the IBM POWER8 system to support computational neuroscientific application using morphologically detailed neurons;performance analysis of OpenMP on a GPU using a CORAL proxy application;examining recent many-core architectures and programming models using SHOC;automatic loop kernel analysis and performance modeling with Kerncraft;techniques for modeling large-scale HPC I/O workloads;characterizing node orderings for improved performance;simulating stencil-based application on future Xeon Phi processor;ARMv8 micro-architectural design space exploration for high performance;and guided profiling for auto-tuning array layouts on GPUs.

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A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms

A resource-efficient multi-camera GigE vision IP core for em...

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international Conference on ReConFigurable computing and FPGAs, ReConFig 2015

作者： Ibraheem, Omar W. Irwansyah, Arif Hagemeyer, Jens Porrmann, Mario Rueckert, Ulrich Cognitronics and Sensor Systems Group CITEC Bielefeld University Bielefeld Germany

ISBN: (纸本)9781467394062

In vision processing systems, many applications require multi-camera support. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resourceefficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supports the connection of multi-camera interfaces to a single Gigabit Ethernet port using an Ethernet switch. The multicamera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras. © 2015 ieee.

关键词： Field programmable gate arrays (FPGA)

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Unobtrusive Posture Recognition via Online Learning of multi-Dimensional RFID Received Signal Strength 21

Unobtrusive Posture Recognition via Online Learning of Multi...

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21st ieee international Conference on Parallel and Distributed systems ICPADS

作者： Yao, Lina Sheng, Quan Z. Ruan, Wenjie Li, Xue Wang, Sen Yang, Zhi Univ Adelaide Sch Comp Sci Adelaide SA 5005 Australia Univ Queensland Sch ITEE Brisbane Qld 4072 Australia

ISBN: (纸本)9780769557854

Activity recognition is a core component of ubiquitous computing applications (e.g., fall detection of elder people) since many of such applications require an intelligent environment to infer what a person is doing or attempting to do. Unfortunately, the success of existing approaches on activity recognition relies heavily on people's involvement such as wearing battery-powered sensors, which might not be practical in real-world situations (e.g., people may forget to wear sensors). In this paper, we propose a device-free, real-time posture recognition technique using an array of pure passive RFID tags. In particular, posture recognition is treated as a machine learning problem where a series of probabilistic model is built via learning how the Received Signal Strength Indicator (RSSI) from the tag array is distributed when a person performs different postures. We also design a segmentation algorithm to divide the continuous, multidimensional RSSI data stream into a set of individual segments by analyzing the shape of the RSSI data. Our approach for posture recognition eliminates the need for the monitored subjects to wear any devices. To the best of our knowledge, this work is the first on device-free posture recognition using low cost, unobtrusive RFID technology. Our experimental studies demonstrate the feasibility of the proposed approach for posture recognition.

关键词： Ubiquitous computing

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A Hierarchical perspective to Fuzzy Inductive Reasoning

A Hierarchical perspective to Fuzzy Inductive Reasoning

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ieee international Conference on Fuzzy systems, FUZZ-ieee 2015

作者： Bagherpour, Solmaz Mugica, Fransisco Nebot, Angela Soft Computing Research Group Computer Science Department Universitat Politècnica de Catalunya-Barcelona Tech Jordi Girona 1-3 Barcelona08034 Spain

ISBN: (纸本)9781467374286

Generalizing hypotheses based on the past data in order to predict the future is the essential core of human learning. Various successful methods and techniques have been developed so far that perform some sort of classification of current data in order to predict future unseen cases. multi class classification problems are among them as well. In many domains in spite of these automatic techniques, involvement of human experts is crucial. In this paper we are proposing a Hierarchical perspective to Fuzzy Inductive Reasoning (FIR) method as a classifier, in order to provide more insights for experts to the predictive model offered by FIR. Also, This method puts a hierarchical constrain on FIR's generalization which might be useful in finding and predicting exceptional cases of data that don't follow the general rule offered by the model. © 2015 ieee.

关键词： Decision making

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Modeling Stencil Computations on Modern HPC Architectures 5th

Modeling Stencil Computations on Modern HPC Architectures

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5th international workshop on Performance Modeling, Benchmarking, and Simulation of High Performance computing systems

作者： de la Cruz, Raul Araya-Polo, Mauricio Barcelona Supercomp Ctr CASE Dept Barcelona Spain Shell Int Explorat & Prod Inc Houston TX USA

ISBN: (纸本)9783319172484;9783319172477

Stencil computations are widely used for solving Partial Differential Equations (PDEs) explicitly by Finite Difference schemes. The stencil solver alone -depending on the governing equation-can represent up to 90% of the overall elapsed time, of which moving data back and forth from memory to CPU is a major concern. Therefore, the development and analysis of source code modifications that can effectively use the memory hierarchy of modern architectures is crucial. Performance models help expose bottlenecks and predict suitable tuning parameters in order to boost stencil performance on any given platform. To achieve that, the following two considerations need to be accurately modeled: first, modern architectures, such as Intel Xeon Phi, sport multi-or manycore processors with shared multi-level caches featuring one or several prefetching engines. Second, algorithmic optimizations, such as spatial blocking or Semi-stencil, have complex behaviors that follow the intricacy of the above described modern architectures. In this work, a previously published performance model is extended to effectively capture these architectural and algorithmic characteristics. The extended model results show an accuracy error ranging from 5-15 %.

关键词： Stencil computation FD Modeling HPC Prefetching Spatial blocking Semi-stencil multi-core Intel Xeon Phi

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The Performance Survey of In Memory Database 21

The Performance Survey of In Memory Database

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21st ieee international Conference on Parallel and Distributed systems ICPADS

作者： Wang, Yinfeng Zhong, Guiquan Kun, Lin Wang, Longxiang Kai, Huang Guo, Fuliang Liu, Chengzhe Dong, Xiaoshe ShenZhen Inst Informat Technol Shenzhen Guangdong Peoples R China ShenZhen Kingdom Ltd Share Ltd Shenzhen Guangdong Peoples R China Xi An Jiao Tong Univ Dept Comp Sci Xian Shaanxi Peoples R China

ISBN: (纸本)9780769557854

To satisfy the ever-increasing performance demand of Big Data and critical applications the data management needs to offer the flexible schema, high availability, light weight replica, high volume and high scalability features so as to facilitate the transaction. The in memory database (IMDB) eliminates the I/O bottleneck by storing data in main memory. We give a deeper analysis of current main-stream IMDB systems performance which focuses on the data structure, architecture, volume, concurrency, availability and scalability. The V3 performance model is proposed to evaluate the Velocity, Volume and Varity of the 19 IMDB systems, in order to highlight the candidates with real-time transaction and high volume processing capacity coordinately. Test results clearly demonstrate that NewSQL is better at dealing with high-frequency trading models. To fully utilize the advantages of the multi-core and many-core processors capability improvements, a three-level optimization design strategy, which includes the memory-access level, the kernel-speedup level and the data-partition level also be proposed using the hardware parallelism for achieving task-level and data-level parallelism of IMDB programs, guarantees the IMDB could accelerate the real-time transaction in an efficient way. We believe that IMDB should become a compulsive option for enterprise users.

关键词： In Memory Database Trading System Performance Evaluation Memory computing Big Data

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