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An Efficient Scheduling Algorithm for Interdependent Tasks in Heterogeneous multi-core systems

An Efficient Scheduling Algorithm for Interdependent Tasks i...

引用

ieee international Conference on systems, Man, and Cybernetics (SMC)

作者： Fan, Zhichao Hu, Wei Guo, Hong Liu, Jing Gan, Yu Wuhan Univ Sci & Technol Coll Comp Sci & Technol Wuhan 430065 Hubei Peoples R China

ISBN: (纸本)9781665442077

Due to the increasing demand for computing power in many industries, heterogeneous multi-core processors are needed to solve the problem. In order to make full use of multi-core computing resources, an effective scheduling strategy for heterogeneous multi-core processor tasks is required. Directed acyclic graph (DAG) is usually used to represent data dependencies between tasks. Each task needs to be executed in the order of its data dependencies. Research under this model has made great progress. In this article, we study and improve the DAG-based task model, taking into account the fact that not only one-way data transmission is possible between tasks, but also two-way data exchange. Based on this model, we propose two scheduling strategies, overall cutting scheduling (OCS) and greedy selection scheduling (GSS). As far as we know, there is currently no work considering the existence of a special task model of two-way transmission between tasks, nor has it considered task scheduling in two-way transmission. In order to evaluate and demonstrate its feasibility and practicability, we proposed a reference method and supplemented with large-scale system experiments. These experiments show that the scheduling efficiency of the proposed method is greatly improved.

关键词： multi-core scheduling algorithm heterogeneous two-way transmission tasks

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Accelerated multilevel Graph Partitioning on GPUs

Accelerated Multilevel Graph Partitioning on GPUs

引用

ieee international Conference on High Performance computing workshops (HiPCW)

作者： Amitesh Singh Bhakti Dhorajiya Vishwesh Jatala Department of CSE IIT Bhilai India

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

Graph partitioning is a long-standing research problem and has applications in various domains, such as data mining, scientific computing, VLSI design. For many years researchers have been focusing on improving the performance of graph partitioning using multi-core CPUs and accelerators like GPUs. However, efficient implementation of graph partitioning on GPU is a challenge. This is because graphs exhibit irregular behavior whereas GPUs follow SIMD execution patterns and GPUs have various resources and efficient utilization is the key to improving the *** paper aims to provide an efficient GPU based implementation of multi-level graph partitioning scheme. We provide GPU implementations of coarsening, partitioning, and refinement phases of the algorithm, to improve the overall performance of the graph partitioning scheme. We evaluated our implementation on various real-world datasets, and we observed a significant improvement in the performance when compared to the baseline METIS.

关键词： Single instruction multiple data Scientific computing High performance computing Conferences Graphics processing units Focusing Very large scale integration Partitioning algorithms Data mining

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An Efficient Bandit Learning for Matching based Distributed Task Offloading in Fog computing Network

An Efficient Bandit Learning for Matching based Distributed ...

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ieee international Symposium on Embedded multicore Socs (MCSoC)

作者： Hoa Tran-Dang Dong-Seong Kim Department of IT Convergence Engineering Kumoh National Institute of Technology Korea

To seek for an efficient distributed offloading solution to the multi-task multi-helper (MTMH) problem in the fog computing networks, we model it as a matching game between a set of task nodes (TNs) having task computation needs and a set of helper nodes (HNs) having available computing resources. However, the uncertainty of computing resource availability of HNs as well as dynamics of QoS requirements of tasks result in the lack of preferences of TN side that mainly poses a critical challenge to obtain a stable and reliable matching outcome. To address this challenge, we apply a multi-armed bandit (MAB) learning using Thomson sampling (TS) mechanism to acquire better exploitation and exploration trade-off, allowing TNs to match with their corresponding HNs efficiently. Based on these, this paper proposes an efficient bandit learning based matching (BLM) for distributed task offloading in the fog computing networks. Extensive simulation results demonstrate the potential advantages of the TS-type algorithm over the ϵ-greedy and UCB based offloading algorithms.

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Proceedings of the 2022 33rd ieee international workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2022

Proceedings of the 2022 33rd IEEE International Workshop on ...

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33rd ieee international workshop on Rapid System Prototyping, RSP 2022

ISBN: (纸本)9798350398519

The proceedings contain 9 papers. The topics discussed include: marine objects detection using deep learning on embedded edge devices;TernaryNERF: quantizing voxel grid-based NERF models;enhancing embedded AI-based object detection using multi-view approach;ANN-based performance estimation of embedded software for RISC-V processors;a case for second-level software cache coherency on many-core accelerators;early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system;automatically restructuring HDL modules for improved reusability in rapid synthesis;a framework that enables systematic analysis of mixed-signal applications on FPGA;and machine learning-based hard/soft logic trade-offs in VTR.

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Seamless Cache Extension for FPGA-based multi-core RISC-V SoC

Seamless Cache Extension for FPGA-based Multi-Core RISC-V So...

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ieee international SOC Conference

作者： Ahmed Kamaleldin Matthias Nickel Sisi Wu Diana Göhringer Chair of Adaptive Dynamic Systems TU Dresden Germany

ISBN: (数字)9798350377569

ISBN: (纸本)9798350377576

Managing cache coherence is essential for optimizing computing performance and energy efficiency in modern multi-/many-core systems. Enabling cache coherence in scalable agile hardware architectures, particularly within RISC-V-based architectures, demands further optimizations regarding interconnect fabric, memory hierarchy, and core-level modifications. In this work, we present a modular and seamless data cache subsystem extension for RISC-V-based multi-core architectures. The proposed data cache sub-system features a full hardware method for cache coherence based on a snooping coherence scheme. The cache sub-system supports scalable multi-core architectures with different core counts. For evaluation, a coherent multi-core architecture with four RISC-V cores is implemented with the proposed data cache sub-system targeting an AMD/Xilinx Virtex Ultrascale+ FPGA device. Several benchmark kernels are used for performance evaluation in terms of memory access time, achievable execution time, and cache hit rate. The average achievable cache hit rate is greater than 90 % with a small hardware overhead.

关键词： Performance evaluation Protocols multicore processing Computer architecture Coherence Benchmark testing Hardware Software System-on-chip Kernel

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Towards Architecture-aware Hierarchical Communication Trees on Modern HPC systems 28

Towards Architecture-aware Hierarchical Communication Trees ...

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28th Annual ieee international Conference on High Performance computing, Data, and Analytics (HiPC)

作者： Ramesh, Bharath Hashmi, Jahanzeb Maqbool Xu, Shulei Shafi, Aamir Ghazimirsaeed, Mahdieh Bayatpour, Mohammadreza Subramoni, Hari Panda, Dhabaleswar K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9781665410168

Modern HPC systems built with emerging multi/many-core architectures have high core-counts and deep memory hierarchies. It is challenging to design communication libraries on these systems with the conventional wisdom of using OS processes as the basic building block to build communication algorithms. Instead, the next generation of communication libraries should treat hardware as the "first-class citizen" and utilize the underlying topology as the basic building block. Driven by this overarching principle, we present a framework for Optimized Shared Memory Processing (OSMP) and communication for these platforms. An abstract representation of the underlying hardware topology is maintained by OSMP in the form of a topology tree, which is later exploited by runtime libraries to execute communication operations in a topology-aware manner. This can be done by simply traversing the topology tree with an existing communication primitive as the base-case. OSMP does not mandate any changes to the original communication algorithm. We focus on collective operations such as barrier, reduction, and broadcast as candidate communication patterns. We demonstrate the efficacy of OSMP by decoupling the implementation of collective algorithms and system topology and evaluate it on four state-of-the-art multi-/many-core architectures : Intel Cascade Lake, AMD Rome, ARM A64fx and IBM POWER9. Results show that even the basic algorithms can be made topology-aware by exploiting OSMP. This provides significant benefits over state-of-the-art algorithm implementations for intra-node communication. Using various micro-benchmarks and applications, we demonstrate that our proposed designs can achieve up to 7.8x improvements at the micro-benchmark level, and 15% for applications over state-of-the-art intra-node collective communication designs employed by production MPI libraries.

关键词： multi-core many-core NUMA Cache Coherence SMP SMP topology Shared Memory MPI

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Automated quantum error mitigation based on probabilistic error reduction 3

Automated quantum error mitigation based on probabilistic er...

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ieee/ACM 3rd international workshop on Quantum computing Software (QCS)

作者： McDonough, Benjamin Mari, Andrea Shammah, Nathan Stemen, Nathaniel T. Wahl, Misty Zeng, William J. Orth, Peter P. Yale Univ Dept Phys & Astron New Haven CT 06511 USA Unitary Fund San Francisco CA 94104 USA Ames Natl Lab Ames IA 50011 USA Iowa State Univ Ames IA 50011 USA

ISBN: (纸本)9781665475365

Current quantum computers suffer from a level of noise that prohibits extracting useful results directly from longer computations. The figure of merit in many near-term quantum algorithms is an expectation value measured at the end of the computation, which experiences a bias in the presence of hardware noise. A systematic way to remove such bias is probabilistic error cancellation (PEC). PEC requires a full characterization of the noise and introduces a sampling overhead that increases exponentially with circuit depth, prohibiting high-depth circuits at realistic noise levels. Probabilistic error reduction (PER) is a related quantum error mitigation method that systematically reduces the sampling overhead at the cost of reintroducing bias. In combination with zero-noise extrapolation, PER can yield expectation values with an accuracy comparable to PEC. Noise reduction through PER is broadly applicable to near-term algorithms, and the automated implementation of PER is thus desirable for facilitating its widespread use. To this end, we present an automated quantum error mitigation software framework that includes noise tomography and application of PER to user-specified circuits. We provide a multi-platform Python package that implements a recently developed Pauli noise tomography (PNT) technique for learning a sparse Pauli noise model and exploits a Pauli noise scaling method to carry out PER. We also provide software tools that leverage a previously developed toolchain, employing PyGSTi for gate set tomography and providing a functionality to use the software Mitiq for PER and zero-noise extrapolation to obtain error-mitigated expectation values on a user-defined circuit.

关键词： quantum noise tomography quantum error mitigation noisy intermediate-scale quantum computing probabilistic error reduction zero noise extrapolation

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Contention-Free Scheduling Algorithm Using LET Paradigm for Clustered many-core Processor 25

Contention-Free Scheduling Algorithm Using LET Paradigm for ...

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25th ieee/ACM international Symposium on Distributed Simulation and Real Time Applications (DS-RT)

作者： Yano, Atsushi Igarashi, Shingo Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan

ISBN: (纸本)9781665433266

Self-driving systems require multi-/many-core platforms with high computing power and low power consumption. However, for hard real-time applications, multiple demands on shared resources can impede real-time performance. Therefore, making the timing of memory access deterministic is important. The logical execution time (LET) paradigm has gained attention as a means to achieve this purpose. However, this approach lacks scalability owing to the overhead caused because the LET paradigm is set longer than the actual execution time of the task. This paper proposes a theoretical scheduling method for a model applying the LET paradigm to the directed acyclic graph (DAG) nodes for a multi-/many-core platform. The proposed method considers communication timing and generates a schedule that does not cause communication contentions. In addition, the proposed method performs a parallel calculation of tasks to deal with the overhead caused by adopting the LET paradigm.

关键词： multi-rate DAG multi-/many-core communication contention list-scheduling logical execution time

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DAG Scheduling for Clustered many-core Processor Considering Execution-Time-Reduction Effectiveness

DAG Scheduling for Clustered Many-Core Processor Considering...

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international workshop/Symposium on Distributed Simulation and Real-Time Applications (DS-RT)

作者： Yutaro Nozaki Takuya Azumi Graduate School of Science and Engineering Saitama University

In recent years, there has been a surge in research on autonomous systems such as unmanned aerial vehicles and autonomous-driving systems. These systems require high computing power with low power consumption and strict real-time requirements. Correspondingly, clustered many-core processors are attracting attention as a solution to these requirements. In this study, we propose a core allocation method for DAG scheduling using clustered many-core processors. Specifically, we propose two methods for selecting nodes to be allocated based on the execution-time-reduction effectiveness, assuming that each node in the DAG can perform intra-node processing in parallel. In addition, we compared the response times obtained from scheduling using each of the two methods to determine which method is superior.

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Optimizing Batched Small Matrix multiplication on multi-core DSP Architecture

Optimizing Batched Small Matrix Multiplication on Multi-core...

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international Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Xiaohan Zuo Chunhua Xiao Qinglin Wang Chen Shi College of Computer Science Chongqing University China Key Laboratory of Dependable Service Computing in Cyber Physical Society Ministry of Education China National Key Laboratory of Parallel and Distributed Computing National University of Defense Technology Changsha China Laboratory of Digitizing Software for Frontier Equipment National University of Defense Technology Changsha China

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

General Matrix multiplication (GEMM) is a critical computational operation in scientific computing and machine learning domains. While traditional GEMM performs well on large matrices, it is inefficient in terms of data transfer and computation for small matrices. many High-Performance computing (HPC) tasks can be decomposed into large batches of small matrix multiplication operations. multi-core Digital Signal Processors (DSPs) are commonly used to accelerate high-performance computing. We present a design for batched fusion small matrix multiplication (BFMM) tailored for multi-core DSP architecture. To address the inefficiencies and redundancy in storage and computational operations associated with batch small matrix multiplications, we designed several strategies. We design a matrix fusion concatenation strategy, an access coordination mechanism, and a mechanism for fragment aggregation. BFMM supports an efficient K-dimension multi-core parallelization strategy. The parameter constraint model makes BFMM highly portable. BFMM also includes a performance evaluation model that facilitates assessment and verification. Experimental results demonstrate that, compared to traditional GEMM (TGEMM) on multi-core DSP and traditional GEMM with concatenated data access (TGEMM Op), BFMM exhibits superior performance. For large batches of small matrices, our design achieves 1.21x to 18x higher performance than TGEMM Op on single-core DSP, while on multi-core DSP, it outperforms TGEMM Op by 1.14x to 18.1x.

关键词： Performance evaluation Scientific computing High performance computing Digital signal processors Redundancy Batch production systems Signal processing algorithms Computer architecture Machine learning Matrix decomposition

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