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ieee international Symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Ajay Kattepur Manoj Nambiar Tata Consultancy Services Performance Engineering Research Center Mumbai India

ISBN: (纸本)9781467376853

multi-tiered transactional web applications are frequently used in enterprise based systems. Due to their inherent distributed nature, pre-deployment testing for high-availability and varying concurrency are important for post-deployment performance. Accurate performance modeling of such applications can help estimate values for future deployment variations as well as validate experimental results. In order to theoretically model performance of multi-tiered applications, we use queuing networks and Mean Value Analysis (MVA) models. While MVA has been shown to work well with closed queuing networks, there are particular limitations in cases where the service demands vary with concurrency. This is further contrived by the use of multi-server queues in multi-core CPUs, that are not traditionally captured in MVA. We compare performance of a multi-server MVA model alongside actual performance testing measurements and demonstrate this deviation. Using spline interpolation of collected service demands, we show that a modified version of the MVA algorithm (called MVASD) that accepts an array of service demands, can provide superior estimates of maximum throughput and response time. Results are demonstrated over multi-tier vehicle insurance registration and e-commerce web applications. The mean deviations of predicted throughput and response time are shown to be less the 3% and 9%, respectively. Additionally, we analyze the effect of spline interpolation of service demands as a function of throughput on the prediction results.

关键词： Throughput Servers Load modeling Testing Concurrent computing Analytical models Time factors

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Parallel computing of sequential MonteCarlo techniques for reliable operation of Smart Grids

Parallel computing of sequential MonteCarlo techniques for r...

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Eurocon

作者： M. Giuntoli P. Pelacchi D. Poli Dept. of Energy Systems University of Pisa - Italy Pisa Italy

Probabilistic methods based on Monte Carlo techniques are successfully employed, both in vertically integrated utilities and in deregulated markets, to assess the long-term adequacy of power systems. Unfortunately, the computational complexity of many time-consuming algorithms has constituted for years a crucial barrier to the use of probabilistic methods also for short-term reliability assessment and decision-support. Nowadays, the availability of cheap and fast computers discloses new opportunities also for on-line reliability calculations. In particular, parallel computing seems to have good chances to be successfully applied to the on-line operation of Smart Grids. In the present paper, a technique of parallel computing, applied to a sequential Monte Carlo algorithm that simulates a power system in a multi-core machine, is proposed and described. A case study based on the ieee Reliability Test System RTS-96 is shown and discussed, with particular emphasis to the speed-up and accuracy obtained as a function of number of employed cores.

关键词： Monte Carlo methods Reliability Instruction sets Power system reliability Probabilistic logic Convergence

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Buffer Allocation Based On-Chip Memory Optimization for many-core Platforms

Buffer Allocation Based On-Chip Memory Optimization for Many...

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ieee international Symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Maximilian Odendahl Andrés Goens Rainer Leupers Gerd Ascheid Tomas Henriksson Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Huawei Technologies Stockholm Sweden

ISBN: (纸本)9781467376853

The problem of finding an optimal allocation of logical data buffers to memory has emerged as a new research challenge due to the increased complexity of applications and new emerging Dynamic RAM (DRAM) interface technologies. This new opportunity of a large off-chip memory accessible by an ample bandwidth allows to reduce the on-chip Static RAM (SRAM) significantly and save production cost of future manycore platforms. We thus propose changes to an existing work that allows to uniformly reduce the on-chip memory size for a given application. We additionally introduce a novel linear programming model to automatically generate all necessary on chip memory sizes for a given application based on an optimal allocation of data buffers. An extension allows to further reduce the required on-chip memory in multi-application scenarios. We conduct a case study to validate all our models and show the applicability of our approach.

关键词： Resource management System-on-chip Random access memory Memory management Optimization Bandwidth Mathematical model

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Scalable mobile backhauling via information-centric networking

Scalable mobile backhauling via information-centric networki...

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ieee workshop on Local and Metropolitan Area Networks (LANMAN)

作者： Giovanna Carofiglio Massimo Gallo Luca Muscariello Diego Perino Cisco Systems Alcatel-Lucent Bell Labs Orange Labs Networks

The rapid traffic growth fueled by mobile devices spread and high speed network access calls for substantial innovation at network layer. The content-centric nature of Internet usage highlights the limitations of the host-centric model in coping with dynamic content-to-location binding, mobility, multicast, multi-homing, etc. If transmission capacity speedups in the backhaul may hide inefficiencies in the short term, the hostcentric communication model needs to be revisited to sustain future mobile demand. In this paper, we first identify and quantify the opportunities for backhaul evolution by analyzing a large set of traffic measurements collected between mobile core and backhaul of Orange France. The analysis reveals that 50% of HTTP requests are cacheable and traffic can be reduced from 60% to 95% during the peak hour by using 350GBs to 1TB of memory overall. Motivated by such significant opportunities for latency reduction and network cost savings, we present a solution based on Information-Centric Networking (ICN). First results of a large scale experimentation with 100 Linux servers and customized software, in a realistic network setting, provide a glimpse into ICN gains even under naive caching: a factor three reduction in delivery time and almost 40% bandwidth savings, when compared to existing alternatives.

关键词： Mobile communication Bandwidth Catalogs Mobile computing Servers IP networks Network topology

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ReCBuLC: Reproducing Concurrency Bugs Using Local Clocks 15

ReCBuLC: Reproducing Concurrency Bugs Using Local Clocks

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international Conference on Software Engineering (ICSE)

作者： Xiang Yuan Chenggang Wu Zhenjiang Wang Jianjun Li Pen-Chung Yew Jeff Huang Xiaobing Feng Yanyan Lan Yunji Chen Yong Guan University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering University of Minnesota at Twin-Cities Minneapolis USA Department of Computer Science and Engineering Texas A&M University Texas USA CAS Key Laboratory of Network Data Science and Technology Chinese Academy of Sciences Beijing China College of Information Engineering Capital Normal University Beijing China

ISBN: (纸本)9781479919345

multi-threaded programs play an increasingly important role in current multi-core environments. Exposing concurrency bugs and debugging such multi-threaded programs have become quite challenging due to their inherent non-determinism. In order to eliminate such non-determinism, many approaches such as record-and-replay and other similar bug reproducing systems have been proposed. However, those approaches often suffer significant performance degradation because they require a large amount of recorded information and/or long analysis and replay time. In this paper, we propose an effective approach, ReCBuLC, to take advantage of the hardware clocks available on modern processors. The key idea is to reduce the recording overhead and analyzing events' global order by using time stamps recorded in each thread. Those timestamps are used to determine the global orders of shared accesses. To avoid the large overhead incurred in accessing system-wide global clock, we opt to use local per-core clocks that incur much less access overhead. We then propose techniques to resolve differences among local clocks and obtain an accurate global event order. By using per-core clocks, state-of-the-art bug reproducing systems such as PRES and CLAP can reduce the recording overheads by 1% ~ 85%, and the analysis time by 84.66% ~ 99.99%, respectively.

关键词： Clocks Program processors Computer bugs Hardware Coherence Concurrent computing Debugging

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Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems

Pool directory: Efficient coherence tracking with dynamic di...

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ieee international Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Sudhanshu Shukla Mainak Chaudhuri Department of Computer Science and Engineering Indian Institute of Technology Kanpur INDIA

The coherence directory in a chip-multiprocessor keeps track of each memory block inside the cache hierarchy and plays a significant role in offering a scalable shared memory abstraction in many-core systems. multi-threaded applications typically require two types of directory entries, namely, limited pointer entries tracking a few sharers of a block and bitvector entries tracking larger number of sharers for widely shared blocks. Recent proposals aiming to optimize the average number of bits per directory entry have organized the directory as either a static mix of these two types of entries or a collection of relatively short bitvector entries that can encode either a limited number of sharer pointers or a larger number of sharers hierarchically. In this paper, we present a directory organization that facilitates allocation of two different types of directory entries dynamically. Our design maintains a pool of limited pointer entries, where each entry can also double as a segment directory entry encoding the sharers in a cluster of cores. Each tag in the primary sparse directory array has a pointer that can either represent a sharer or point to an entry in the pool. When multiple segment directory entries are needed to encode all the sharers of a block, our pool management protocol guarantees that all these entries are allocated contiguously so that maintaining a pointer to the head entry is enough. Such a design offers significant flexibility in sharer encoding and allows us to independently size the sparse directory array and the pool. Detailed simulation results show that our proposal incorporated in a 128-core system running multi-threaded applications drawn from scientific, general-purpose, and commercial computing domains can offer, on average, 5% improvement in performance and 20% savings in interconnect traffic compared to the state-of-the-art scalable coherence directory (SCD) proposal when using a 1/16 × sparse directory.

关键词： Proposals Coherence Organizations Resource management Protocols Dynamic scheduling Encoding

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Parallel online spatial and temporal aggregations on multi-core CPUs and many-core GPUs

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INFORMATION systems 2014年第Aug.期44卷 134-154页

作者： Zhang, Jianting You, Simin Gruenwald, Le CUNY Dept Comp Sci New York NY 10031 USA CUNY Grad Ctr Dept Comp Sci New York NY 10016 USA Univ Oklahoma Sch Comp Sci Norman OK 73071 USA

With the increasing availability of locating and navigation technologies on portable wireless devices, huge amounts of location data are being captured at ever growing rates. Spatial and temporal aggregations in an Online Analytical Processing (OLAP) setting for the large-scale ubiquitous urban sensing data play an important role in understanding urban dynamics and facilitating decision making. Unfortunately, existing spatial, temporal and spatiotemporal OLAP techniques are mostly based on traditional computing frameworks, i.e., disk-resident systems on uniprocessors based on serial algorithms, which makes them incapable of handling large-scale data on parallel hardware architectures that have already been equipped with commodity computers. In this study, we report our designs, implementations and experiments on developing a data management platform and a set of parallel techniques to support high-performance online spatial and temporal aggregations on multi-core CPUs and many-core Graphics Processing Units (CPUs). Our experiment results show that we are able to spatially associate nearly 170 million taxi pickup location points with their nearest street segments among 147,011 candidates in about 5-25 s on both an Nvidia Quadro 6000 GPU device and dual Intel Xeon E5405 quad-core CPUs when their Vector Processing Units (VPUs) are utilized for computing intensive tasks. After spatially associating points with road segments, spatial, temporal and spatiotemporal aggregations are reduced to relational aggregations and can be processed in the order of a fraction of a second on both CPUs and multi-core CPUs. In addition to demonstrating the feasibility of building a high-performance OLAP system for processing large-scale taxi trip data for real-time, interactive data explorations, our work also opens the paths to achieving even higher OLAP query efficiency for large-scale applications through integrating domain-specific data management platforms, novel parallel data structu

关键词： OLAP Parallel design GPU multi-core CPU Spatiotemporal aggregation Spatial indexing Spatial join Large-scale data

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A Preliminary Analysis on BLMAB-based Approximate Optimization Support for multi Agent Simulations on multi-core and GPU-based computing Environment 7

A Preliminary Analysis on BLMAB-based Approximate Optimizati...

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ieee 7th international Conference on Service-Oriented computing and Applications (SOCA)

作者： Sano, Yoshihito Kadono, Yoshiaki Fukuta, Naoki Shizuoka Univ Grad Sch Informat Shizuoka Japan

ISBN: (纸本)9781479968336

There are strong demands to utilize multi-core computing resources effectively for large-scale and highly detailed multi-agent simulations. We have proposed a framework to assist parameter tuning process of multi-core programming for simulation developers to utilize many parallel cores in their simulation programs efficiently. However, due to its massive computation costs, it is not easy task to seek the sufficient compilation and execution parameters and analyze their performance characteristics for various execution settings. In this paper, we present a preliminary analysis of parameter optimization based on BLMAB by utilizing our framework. We show how our BLMAB-based approach can effectively be used on the parameter optimization process.

关键词： digital simulation graphics processing units multi-agent systems multiprocessing systems parallel programming BLMAB GPU-based computing environment approximate optimization support budget-limited multiarmed bandits model multiagent simulations multicore computing environment parameter optimization process Computational modeling Graphics processing units multicore processing Optimization Programming Runtime Tuning Graphics Processing Unit multiprocessing systems Digital simulation Computer Simulation Runtime Parallel programming Computational modeling Programming tuning multi-agent systems simulating Parameter optimization

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On the evaluation of multi-core systems with SIMD engines for public-key cryptography 26

On the evaluation of multi-core systems with SIMD engines fo...

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26th ieee international Symposium on Computer Architecture and High Performance computing workshops, SBAC-PADW 2014

作者： Martins, Paulo Sousa, Leonel SiPS INESC-ID Instituto Superior Técnico Universidade de Lisboa Rua Alves Redol 9 Lisboa1000-029 Portugal

ISBN: (纸本)9781479970148

The acceleration of cryptographic applications on embedded devices is a topic of increasingly importance, due to their massive use. In this paper, the efficiency of these devices when operating as cryptographic accelerators is assessed, using a two-tiered parallelism model, where not only multi-core, but also Single Instruction multiple Data (SIMD) parallelism is exploited to increase the throughput of modular multiplications. In addition, the applicability of the developed parallel modular multiplications are tested for the Rivest-Shavir-Adleman (RSA) and Elliptic Curve (EC) cryptosystems. The relative efficiency of the two-tiered model for implementing cryptosystems on general purpose processors and embedded devices is analysed and experimentally evaluated. It can be concluded that it is possible to achieve the same levels of execution enhancement on both platforms. Moreover, speedups of upto 7.3 and 3.9 are obtained for the RSA and EC cryptosystems on the ARM A15 quad-core processor, respectively. © 2014 ieee.

关键词： Embedded systems

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The Performance Survey of in Memory Database

The Performance Survey of in Memory Database

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international Conference on Parallel and Distributed systems (ICPADS)

作者： Yinfeng Wang Guiquan Zhong Lin Kun Longxiang Wang Huang Kai Fuliang Guo Chengzhe Liu Xiaoshe Dong ShenZhen Institute of Information Technology Guangdong China ShenZhen Kingdom Limited by Share Ltd. Guangdong China Department of Computer Science Xi'an Jiaotong University Shaanxi China

To satisfy the ever-increasing performance demand of Big Data and critical applications the data management needs to offer the flexible schema, high availability, light weight replica, high volume and high scalability features so as to facilitate the transaction. The in memory database (IMDB) eliminates the I/O bottleneck by storing data in main memory. We give a deeper analysis of current main-stream IMDB systems performance which focuses on the data structure, architecture, volume, concurrency, availability and scalability. The V3 performance model is proposed to evaluate the Velocity, Volume and Varity of the 19 IMDB systems, in order to highlight the candidates with realtime transaction and high volume processing capacity coordinately. Test results clearly demonstrate that NewSQL is better at dealing with high-frequency trading models. To fully utilize the advantages of the multi-core and many-core processors capability improvements, a three-level optimization design strategy, which includes the memory-access level, the kernel-speedup level and the data-partition level also be proposed using the hardware parallelism for achieving task-level and data-level parallelism of IMDB programs, guarantees the IMDB could accelerate the real-time transaction in an efficient way. We believe that IMDB should become a compulsive option for enterprise users.

关键词： Databases Scalability Real-time systems Concurrent computing Random access memory Servers Memory management

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