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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 976 条记录，以下是411-420 订阅

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Improving Performance of Structured-Memory, Data-Intensive Applications on multi-core Platforms via a Space-Filling Curve Memory Layout

Improving Performance of Structured-Memory, Data-Intensive A...

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ieee international Symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： E. Wes Bethel David Camp David Donofrio Mark Howison Lawrence Berkeley National Laboratory Berkeley CA USA Lawrence Berkeley National Laboratory and Brown University Providence RI USA

ISBN: (纸本)9781467376853

many data-intensive algorithms -- particularly in visualization, image processing, and data analysis -- operate on structured data, that is, data organized in multidimensional arrays. While many of these algorithms are quite numerically intensive, by and large, their performance is limited by the cost of memory accesses. As we move towards the exascale regime of computing, one central research challenge is finding ways to minimize data movement through the memory hierarchy, particularly within a node in a shared-memory parallel setting. We study the effects that an alternative in-memory data layout format has in terms of runtime performance gains resulting from reducing the amount of data moved through the memory hierarchy. We focus the study on shared-memory parallel implementations of two algorithms common in visualization and analysis: a stencil-based convolution kernel, which uses a structured memory access pattern, and ray casting volume rendering, which uses a semi-structured memory access pattern. The question we study is to better understand to what degree an alternative memory layout, when used by these key algorithms, will result in improved runtime performance and memory system utilization. Our approach uses a layout based on a Z-order (Morton-order) space-filling curve data organization, and we measure and report runtime and various metrics and counters associated with memory system utilization. Our results show nearly uniform improved runtime performance and improved utilization of the memory hierarchy across varying levels of concurrency the applications we tested. This approach is complementary to other memory optimization strategies like cache blocking, but may also be more general and widely applicable to a diverse set of applications.

关键词： Layout Runtime Arrays Three-dimensional displays Algorithm design and analysis Indexes Data visualization

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Impact of serial scaling of multi-threaded programs in many-core era 26

Impact of serial scaling of multi-threaded programs in many-...

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26th ieee international Symposium on Computer Architecture and High Performance computing workshops, SBAC-PADW 2014

作者： Narayanan, Surya Swamy, Bharath N. Seznec, André INRIA Rennes France

ISBN: (纸本)9781479970148

Estimating the potential performance of parallel applications on the yet-to-be-designed future many cores is very speculative. The traditional laws used to predict performance of an application do not reflect on the various scaling behaviour of a multi-threaded (MT) application leading to optimistic estimation of performance in manycore era. In this paper, we study the scaling behavior of MT applications as a function of input workload size and the number of cores. For some MT applications in the benchmark suites we analysed, our study shows that the serial fraction in the program increases with input workload size and can be a scalability-limiting factor. Similar to previous studies [5] , we find that using a powerful core (heterogeneous architecture) to execute this serial part of the program can mitigate the impact of serial scaling and improve the overall performance of an application in many-core era. © 2014 ieee.

关键词： Benchmarking

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Metaprogramming Dense Linear Algebra Solvers Applications to multi and many-core Architectures

Metaprogramming Dense Linear Algebra Solvers Applications to...

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ieee international Conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Ian Masliah Marc Baboulin Joel Falcou University of Paris-Sud and Inria Orsay France

ISBN: (纸本)9781467379533

The increasing complexity of new parallel architectures has widened the gap between adaptability and efficiency of the codes. As high performance numerical libraries tend to focus more on performance, we wish to address this issue using a C++ library called NT 2 . By analyzing the properties of the linear algebra domain that can be extracted from numerical libraries and combining them with architectural features, we developed a generic approach to solve dense linear systems on various architectures including CPU and GPU. We have then extended our work with an example of a least squares solver based on semi-normal equations in mixed precision that cannot be found in current libraries. For the automatically generated solvers, we report performance comparisons with state-of-the-art codes, and show that it is possible to obtain a generic code with a high-level interface (similar to Matlab) which runs either on CPU or GPU without generating a significant overhead.

关键词： Libraries Linear algebra Graphics processing units Programming Computer architecture MATLAB DSL

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A multi-GPU Hitting Set Algorithm for GRNs Inference

A Multi-GPU Hitting Set Algorithm for GRNs Inference

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ieee/ACM international Symposium on Cluster computing and the Grid (CCGRID)

作者： Danilo Carastan-Santos Raphael Yokoingawa De Camargo David Correa Martins Siang Wun Song Luiz Carlos Silva Rozante Fabrizio Ferreira Borelli Universidade Federal do ABC Santo André Brazil Universidade Federal do ABC Santo Andre SP BR

Gene regulatory networks inference is one of the crucial problems of the systems Biology field. It is still an open problem, mainly because of its high dimensionality (thousands of genes) with a limited number of samples (dozens), making it difficult to estimate dependencies among genes. Besides the estimation problem, another important hindrance is the inherent computational complexity of GRN inference methods. In this work, we focus on circumventing performance issues of a technique based on signal perturbations to infer gene dependencies. One of its main steps consists in solving the Hitting Set problem (HSP), which is NP-Hard. There are many proposals to obtain approximate or exact solutions to this problem. One of these proposals consists of a Graphical Processing Unit (GPU) based algorithm to obtain exact solutions to the HSP. However, such method is not scalable for real size GRNs. We propose an extension of the HSP algorithm to deal with input sets containing thousands of variables by introducing innovations in the data structures and a sorting scheme to allow efficient discarding of Hitting Set non-solution candidates. We provide an implementation for multi-core CPUs and GPU clusters. Our experimental results show that the usage of the sorting scheme brings speedups of up to 3.5 in the CPU implementation. Moreover, using a single GPU, we could obtain an additional speedup of up to 4.7, in comparison with the multithreaded CPU implementation. Finally, usage of eight GPUs from a GPU cluster brought an additional speedup of up to 6.6. Combining all techniques, speedups above 60 were obtained for the parallel part of the algorithm.

关键词： Graphics processing units Silicon Sorting Gene expression Clustering algorithms Inference algorithms Approximation algorithms

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Holographic Algorithms for On-Chip, Non-Boolean computing

Holographic Algorithms for On-Chip, Non-Boolean Computing

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international workshop on Computational Electronics (IWCE)

作者： Csaba, G. Papp, A. Porod, W. Univ Notre Dame Ctr Nano Sci & Technol Notre Dame IN 46556 USA

ISBN: (纸本)9781479954339

t is widely believed that the established route of microelectronic scaling is approaching its end: further downscaling of semiconductor devices carries disproportionate penalties in power consumption and poses fundamental fabrication challenges. Instead of scaling of devices, Moore's law is now increasingly about scaling computing systems: single-core devices toward larger, multi-core systems. While there are known programming methodologies for parallelizing program codes to a few threads, only very few, special-purpose applications lend themselves to parallelization on very large numbers of cores. This motivates our quest for studying computing paradigms and algorithms that are inherently parallel [1]. Holographic / optical computing is a perfect example of such algorithms: the results of a computation are given by an interference pattern formation of many light rays (see Fig. 1 for an illustration [1]). Optical systems are impractical to realize on-chip. For this reason, we explore routes to design holographic algorithms that can be naturally integrated with microelectronic technologies and require no optical hardware. Two approaches will be discussed in this paper.

关键词： Fourier transforms Holographic optical components Holography Mirrors Optical films Optical filters Vectors Holographic optical components Holography Optical films OPTICAL FILTER Mirrors Fourier Transform Semiconductor devices Power consumption Scale formation Cloning Vectors

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Optimizing Power and Performance Trade-offs of MapReduce Job Processing with Heterogeneous multi-core Processors 7

Optimizing Power and Performance Trade-offs of MapReduce Job...

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7th ieee international Conference on Cloud computing (CLOUD)

作者： Yan, Feng Cherkasova, Ludmila Zhang, Zhuoyao Smirni, Evgenia Hewlett Packard Labs Palo Alto CA 94304 USA Coll William & Mary Williamsburg VA 23187 USA Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781479950638

Modern processors are often constrained by a given power budget that forces designers to consider different trade-offs, e.g., to choose between either many slow, power efficient cores, or fewer faster, power-hungry cores, or to select a combination of them. In this work, we design and evaluate a new Hadoop scheduler, called DyScale, that exploits capabilities offered by heterogeneous cores within a single multi-core processor for achieving a variety of performance objectives. A typical MapReduce workload contains jobs with different performance goals: large, batch jobs that are throughput oriented, and smaller interactive jobs that are response-time sensitive. Heterogeneous multi-core processors enable creating virtual resource pools based on the different core types for multi-class priority scheduling. These virtual Hadoop clusters, based on "slow" cores versus "fast" cores can effectively support different performance objectives that cannot be achieved in a Hadoop cluster with homogeneous processors. Using detailed measurements and extensive simulation study we argue in favor of heterogeneous multi-core processors as they provide performance means for "faster" processing of the small, interactive MapReduce jobs (up to 40% faster), while at the same time offer an improved throughput (up to 40% higher) for large, batch job processing.

关键词： MapReduce Hadoop heterogeneous systems scheduling performance power

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Unobtrusive Posture Recognition via Online Learning of multi-dimensional RFID Received Signal Strength

Unobtrusive Posture Recognition via Online Learning of Multi...

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international Conference on Parallel and Distributed systems (ICPADS)

作者： Lina Yao Quan Z. Sheng Wenjie Ruan Xue Li Sen Wang Zhi Yang School of Computer Science The University of Adelaide SA Australia School of ITEE The University of Queensland Australia

Activity recognition is a core component of ubiquitous computing applications (e.g., fall detection of elder people) since many of such applications require an intelligent environment to infer what a person is doing or attempting to do. Unfortunately, the success of existing approaches on activity recognition relies heavily on people's involvement such as wearing battery-powered sensors, which might not be practical in real-world situations (e.g., people may forget to wear sensors). In this paper, we propose a device-free, real-time posture recognition technique using an array of pure passive RFID tags. In particular, posture recognition is treated as a machine learning problem where a series of probabilistic model is built via learning how the Received Signal Strength Indicator (RSSI) from the tag array is distributed when a person performs different postures. We also design a segmentation algorithm to divide the continuous, multidimensional RSSI data stream into a set of individual segments by analyzing the shape of the RSSI data. Our approach for posture recognition eliminates the need for the monitored subjects to wear any devices. To the best of our knowledge, this work is the first on device-free posture recognition using low cost, unobtrusive RFID technology. Our experimental studies demonstrate the feasibility of the proposed approach for posture recognition.

关键词： Passive RFID tags Arrays Support vector machines Received signal strength indicator Monitoring

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Scaling and Analyzing the Stencil Performance on multi-core and many-core Architectures 20

Scaling and Analyzing the Stencil Performance on Multi-Core ...

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20th ieee international Conference on Parallel and Distributed systems (ICPADS)

作者： Gan, Lin Fu, Haohuan Xue, Wei Xu, Yangtong Yang, Chao Wang, Xinliang Lv, Zihong You, Yang Yang, Guangwen Ou, Kaijian Tsinghua Univ Minist Educ Key Lab Earth Syst Modeling Ctr Earth Syst Sci Beijing Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China Chinese Acad Sci Inst Software Beijing 100864 Peoples R China Chinese Acad Sci State Key Lab Comp Sci Beijing 100864 Peoples R China CSG Elect Power Res Inst Guangzhou Guangdong Peoples R China

ISBN: (纸本)9781479976157

Stencils are among the most important and time-consuming kernels in many applications. While stencil optimization has been a well-studied topic on CPU platforms, achieving higher performance and efficiency for the evolving numerical stencils on the more recent multi-core and many-core architectures is still an important issue. In this paper, we explore a number of different stencils, ranging from a basic 7-point Jacobi stencil to more complex high-order stencils used in finer numerical simulations. By optimizing and analyzing those stencils on the latest multi-core and many-core architectures (the Intel Sandy Bridge processor, the Intel Xeon Phi coprocessor, and the NVIDIA Fermi C2070 and Kepler K20x GPUs), we investigate the algorithmic and architectural factors that determine the performance and efficiency of the resulting designs. While multi-threading, vectorization, and optimization on cache and other fast buffers are still the most important techniques that provide performance, we observe that the different memory hierarchy and the different mechanism for issuing and executing parallel instructions lead to the different performance behaviors on CPU, MIC and GPU. With vector-like processing units becoming the major provider of computing power on almost all architectures, the compiler's inability to align all the computing and memory operations would become the major bottleneck from getting a high efficiency on current and future platforms. Our specific optimization of the complex WNAD stencil on GPU provides a good example of what the compiler could do to help.

关键词： Stencil multi-core architecture many-core architecture Optimizations

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ARCS 2014 - 2014 workshop Proceedings on Architecture of computing systems

ARCS 2014 - 2014 Workshop Proceedings on Architecture of Com...

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27th international Conference on Architecture of computing systems workshop, ARCS 2014

ISBN: (纸本)9783800735792

The proceedings contain 26 papers. The topics discussed include: the invasive network on chip - a multi-objective many-core communication infrastructure;FALP: a fault adaptive and low power method for network on chip router;an approach to enhance loop performance for multicluster VLIW DSP processor;improving efficiency of embedded multi-core platforms with scratchpad memories;towards actor-oriented programming on PGAS-based multicore architectures;multi-objective diagnosis of non-permanent faults in many-core systems;towards tight interaction of ASP and SMT solving for system-level decision making;hybrid parallelization of a seeded region growing segmentation of brain images for a GPU cluster;performance engineering for a medical imaging application on the Intel Xeon Phi Accelerator;and PBA2CUDA - a framework for parallelizing population based algorithms using CUDA.

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multi-core-GPUs-SRs platform Policy in Hard Real Time System (MCGSP)

Multi-Core-GPUs-SRs platform Policy in Hard Real Time System...

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ieee international Conference on Signal Processing, Communications and computing (ICSPCC)

作者： Rabee, Furkan Liao, Yong Yang, Maolin UESTC Sch Informat & Software Engn China 2006 Xiyuan Ave Chengdu 611731 Peoples R China Univ Kufa Comp Sci Dept Coll Math & Comp Sci Najaf Iraq

ISBN: (纸本)9781479952748

With rapid development of Graphics Processing Units (GPU) technologies, GPUs are strongly motivated to be adopted in many real-time applications, and to be online with that we present a new design for multi-core-GPUs platform system with different shared resources, where this platform divided into two part;fist: clustering the multi-core-GPUs-shared resources by a new method, where CPUs and GPUs with shared resources grouped in one cluster and scheduled it by partition scheduling with MPCP, and second;presenting an innovative mechanism for scheduling GPUs with shared resources in multi-core system. The GPU has been tested with many operations by OpenCL language and used the GPU performance with multi-core system depending on MPCP protocol evaluations and compare it with traditional system without GPU and the evaluations were very good.

关键词： Hard real-real time systems multi-core-GPUs-SRs platform global protocol MCGSP

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