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Exploratory analysis of raw data files through dataflows 26

Exploratory analysis of raw data files through dataflows

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26th ieee international Symposium on Computer Architecture and High Performance computing workshops, SBAC-PADW 2014

作者： Silva, Vitor De Oliveira, Daniel Mattoso, Marta Computer Science - COPPE Federal University of Rio de Janeiro Rio de Janeiro Brazil Institute of Computing Fluminense Federal University Niteroi Brazil

ISBN: (纸本)9781479970148

Scientific applications generate raw data files in very large scale. Most of these files follow a standard format established by the domain area application, like HDF5, NetCDF and FITS. These formats are supported by a variety of programming languages, libraries and programs. Since they are in large scale, analyzing these files require writing a specific program. Generic data analysis systems like database management systems (DBMS) are not suited because of data loading and data transformation in large scale. Recently there have been several proposals for indexing and querying raw data files without the overhead of using a DBMS, such as noDB, RAW and FastBit. Their goal is to offer query support to the raw data file after a scientific program has generated it. However, these solutions are focused on the analysis of one single large file. When a large number of files are all related and required to the evaluation of one scientific hypothesis, the relationships must be managed manually or by writing specific programs. The proposed approach takes advantage of existing provenance data support from Scientific Workflow Management systems (SWfMS). When scientific applications are managed by SWfMS, the data is registered along the provenance database at runtime. Therefore, this provenance data may act as a description of theses files. When the SWfMS is dataflow aware, it registers domain data all in the same database. This resulting database becomes an important access method to the large number of files that are generated by the scientific workflow execution. This becomes a complementary approach to the single raw data file analysis support. In this work, we present our dataflow approach for analyzing data from several raw data files and evaluate it with the Montage application from the astronomy domain. © 2014 ieee.

关键词： Data handling

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High-level dataflow programming for reconfigurable computing 26

High-level dataflow programming for reconfigurable computing

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26th ieee international Symposium on Computer Architecture and High Performance computing workshops, SBAC-PADW 2014

作者： Sérot, J. Berry, F. Institut Pascal Université Blaise Pascal / CNRS Clermont-Ferrand France

ISBN: (纸本)9781479970148

In many application domains, FPGAS are now promoted as a way of getting round the restrictions of specific CPU designs on system scalability. However, in the current state-of-the art, programming FPGAS remains essentially a hardware-oriented activity, relying on dedicated hardware description languages such as VHDL or Verilog. Using these languages requires expertise in digital design and in practice this limits the applicability of FPGA-based solutions. This is particulary true for stream-processing applications, in which some processing must be carried out "on the fly" on digital data streams. In this context, the dataflow programming model offers a very effective way to reduce the gap between high-level formulations and low-level implementations. To support this claim, the authors have recently introduced CAPH, a domain specific language, offering a fully-automated compilation path from high-level dataflow descriptions to FPGA configuration for stream-processing applications. This paper is a introduction to the CAPH language, giving its motivations and main design principles and exposing the basic features of its syntax, semantics and compilation. It also points to experimental results showing that, at least for stream-processing applications, the dataflow model of computation, used jointly as a programming model and an execution model, can offer a very effective way to conciliate abstraction and efficiency when programming FPGAS. © 2014 ieee.

关键词： Computer hardware description languages

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Introducing A-Cell for Scalable and Portable SIMD Programming 8

Introducing A-Cell for Scalable and Portable SIMD Programmin...

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8th ieee international Symposium on Embedded multicore/manycore systems-on-Chip (MCSoC)

作者： Khandan, Hamed RIKEN Adv Inst Computat Sci Adv Visualisat Res Team Kobe Hyogo Japan

ISBN: (纸本)9781479943050

A-Cell is a high-level abstraction of fine-grained parallelism specifically designed to be applicable to all range of parallel devices from super computers based on CPUs or GPUs, to network of embedded devices. To achieve this, A-Cell adopts a programming model called "connectionist computing" and with that takes a leap step away from Turing programming model. Also, in contrast with most common solutions like PGAS that are holistic, the philosophy of A-Cell is reductionist. An A-Cell encapsulates a fine-grained task with its related variables. A source-to-source compiler translates the program to a set of programs that are compilable to the target devices. Execution of the task is through massive instantiation of an A-Cell prototype. The runtime system takes the responsibility of distributing A-Cell instances between all available nodes, cores or multiprocessors (MPs). The runtime system also assures synchronization and consistency between A-Cell instances. This paper introduces the theoretical aspect of A-Cell, its semantics and its design logic, and reports the progress made for its materialization, including the A-Cell simulator, C/C++ runtime system, and precompiler.

关键词： multi-core Processing many-core Processing Parallel Programming Concurrency Control High-Performance computing Middleware

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Proceedings - 14th ieee/ACM international Symposium on Cluster, Cloud, and Grid computing, CCGrid 2014

Proceedings - 14th IEEE/ACM International Symposium on Clust...

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14th ieee/ACM international Symposium on Cluster, Cloud and Grid computing, CCGrid 2014

ISBN: (纸本)9781479927838

The proceedings contain 117 papers. The topics discussed include: a language support for cloud elasticity management;elastic MapReduce execution;JCatascopia: monitoring elastically adaptive applications in the cloud;towards a collective layer in the big data stack;flexpath: type-based publish/subscribe system for large-scale science analytics;transparent in situ data transformations in ADIOS;a flexible framework for asynchronous in situ and in transit analytics for scientific simulations;iteration based collective I/O strategy for parallel I/O systems;efficiently handling skew in outer joins on distributed systems;A PGAS execution model for efficient stencil computation on many-core processors;a branch-and-bound algorithm for autonomic adaptation of multi-cloud applications;decentralized scheduling and load balancing for parallel programs;multi-objective scheduling for heterogeneous server systems with machine placement;PLAStiCC: predictive look-ahead scheduling for continuous dataflows on clouds;and link-heterogeneous work stealing.

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4th international workshop on Performance Modeling, Benchmarking and Simulation of High-Performance computing systems, PMBS 2013

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4th international workshop on Performance Modeling, Benchmarking and Simulation of High-Performance computing systems, PMBS 2013

ISBN: (纸本)9783319102139

The proceedings contain 19 papers. The special focus in this conference is on comparing high-performance computing systems through performance modeling, benchmarking, or the use of tools such as simulators. The topics include: Quantifying architectural requirements of contemporary extreme-scale scientific applications;performance evaluation of the Intel sandy bridge based NASA Pleiades using scientific and engineering applications;analysis of Cray XC30 performance using Trinity-NERSC-8 benchmarks and comparison with Cray XE6 and IBM BG/Q;analysis of data reuse in task-parallel runtimes;using simulation to evaluate the performance of resilience strategies at scale;characterizing the impact of prefetching on scientific application performance;performance modeling of Gyrokinetic toroidal simulations for a many-tasking runtime system;toward better simulation of MPI applications on Ethernet/TCP networks;SESH framework;optimal checkpointing period;tuning HipGISAXS on multi and many core supercomputers;multi objective optimization of HPC kernels for performance, power, and energy;performance tuning of Fock matrix and two-electron integral calculations for NWChem on leading HPC platforms and performance analysis of the NWChem TCE for different communication patterns.

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A high-level analysis of a multi-core vision processor using SystemC and TLM2.0

A high-level analysis of a multi-core vision processor using...

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2014 international Conference on Reconfigurable computing and FAGAs

作者： Mori, Jones Y. Huebner, Michael Ruhr Univ Bochum Dept Elect Engn & Informat Technol Bochum Germany Univ Brasilia Dept Mech Engn BR-70910900 Brasilia DF Brazil

ISBN: (纸本)9781479959440

Vision Processors are integrated circuits with the aim to put together sensors and processing elements at the same chip. There are several constraints a designer may take into account when developing a vision processor: available technology, power consumption, thermal management, fault tolerance, speed, silicon area and application-specific needs. Most of these vision processors are based on analog circuits and can perform only low-level processing, like filtering and contrast adjustment. Digital processing elements can allow for more programmability in such systems, however, the approaches found in the literature do not explore the integration of sensor and processing elements in an efficient way. In addition, it is envisioned that vision processors can take advantage of the recent multi/many-core advances. In this work, a full integration is analyzed, exploring the spatial distribution of sensors and processors. All the design blocks were developed using SystemC language with TLM2.0 standard, in order to allow for a better ESL analysis. The exploration of pure LT and mixed LT/AT models is used for extract information about parallelism in data transfer and operations. An application with some well-known algorithms is analyzed for a variable number of cores, in order to validate the tool-set and the methodology used.

关键词： computer vision multiprocessing systems ESL analysis SystemC language TLM2.0 standard analog circuits integrated circuits low-level processing multicore vision processor processing elements sensors Algorithm design and analysis Analytical models Computer architecture Image processing Parallel processing Routing Sensors Sensors Algorithm design and analysis analog circuits multiprocessing systems Computer Architecture PARALLEL PROCESSING (COMPUTERS) ANALYSIS MODELS PROCESSOR Processing Element images computer vision Network routing Image processing Sight Integrated circuits

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PARMA-DITAM 2014 - Proc., 5th workshop on Parallel Programming and Run-Time Manage. Tech. for many-core Architect. and 3rd workshop on Design Tools and Architect. for multicore Embedded Comput. Platforms

PARMA-DITAM 2014 - Proc., 5th Workshop on Parallel Programmi...

引用

5th workshop on Parallel Programming and Run-Time Management Techniques for many-core Architectures and 3rd workshop on Design Tools and Architectures for multicore Embedded computing Platforms, PARMA-DITAM 2014

ISBN: (纸本)9781450326070

The proceedings contain 7 papers. The topics discussed include: an interactive tool based on Polly for detection and parallelization of loops;on expressing strategies for directive-driven multicore programming models;effective platform-level exploration for heterogeneous multicores exploiting simulation-induced slacks;a cycle-accurate synthesizable MIPS simulator in Simulink;extending a run-time resource management framework to support OpenCL and heterogeneous systems;exploiting performance counters for energy efficient co-scheduling of mixed workloads on multi-core platforms;and fine-grained link locking within power and latency transaction level modelling in wormhole switching non-preemptive networks on chip.

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An Efficient Implementation of PBKDF2 with RIPEMD-160 on multiple FPGAs 20

An Efficient Implementation of PBKDF2 with RIPEMD-160 on Mul...

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20th ieee international Conference on Parallel and Distributed systems (ICPADS)

作者： Abbas, Ayman Voss, Rian Wienbrandt, Lars Schimmler, Manfred Christian Albrechts Univ Kiel Dept Comp Sci D-24098 Kiel Germany

ISBN: (纸本)9781479976157

A weakness of many security systems is the strength of the chosen password or key derivation function. We show how FPGA technology can be used to effectively attack cryptographic applications with a password dictionary. We have implemented two independent PBKDF2 cores each using four HMAC cores with pipelines calculating a RIPEMD-160 hash to derive encryption keys together with one resource optimized AES-256 XTS core for direct decryption on a Xilinx Spartan6-LX150 FPGA. Our design targets TRUECRYPT containers, but may be applied to similar encryption tools with little adaption. In order to save resources and maximize speed, we have further optimized the RIPEMD-160 hash function for this purpose. Our design executed on the multi-FPGA system RIVYERA S6-LX150 containing 128 S6-LX150 FPGAs, finally reaches a peak performance of about 245,000 passwords per second.

关键词： known-plaintext dictionary attack AES-XTS RIPEMD-160 PBKDF2 FPGA reconfigurable high-performance computing

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Exploring DMA-assisted Prefetching Strategies for Software Caches on multicore Clusters

Exploring DMA-assisted Prefetching Strategies for Software C...

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ieee 25th international Conference on Application-Specific systems, Architectures and Processors (ASAP)

作者： Pinto, Christian Benini, Luca Univ Bologna DEI Deparment I-40126 Bologna Italy

ISBN: (纸本)9781479936090

Modern many-core programmable accelerators are often composed by several computing units grouped in clusters, with a shared per-cluster scratchpad data memory. The main programming challenge imposed by these architectures is to hide the external memory to on-chip scratchpad memory transfer latency, trying to overlap as much as possible memory transfers with actual computation. This problem is usually tackled using complex DMA-based programming patterns (e.g. double buffering), which require a heavy refactoring of applications. Software caches are an alternative to hand-optimized DMA programming. However, even if a software cache can reduce the programming effort, it is still relying on synchronous memory transfers. In fact in case of a cache miss, the new line is copied in cache and the requesting processor has to wait for the completion of the transfer. While waiting, processors are not able to perform any other computation. Cache lines prefetching can be used to reduce the number of synchronous memory transfers, and increase the active time of each processor, by loading cache lines before they are actually needed. In this work we explore various DMA-based prefetching techniques applied to a software cache implementation, presenting both automatic and programmer assisted prefetch mechanisms applied to computer vision kernels.

关键词： Cache memory prefetching multi-core processors double-buffer PROCESSOR effective time external memory line feed Programming scratchpad Computer personnel computer software ARCHITECTURE computer programs

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AdaPNet: Adapting Process Networks in Response to Resource Variations

AdaPNet: Adapting Process Networks in Response to Resource V...

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international Conference on Compilers, Architecture and Synthesis for Embedded systems (CASES)

作者： Schor, Lars Bacivarov, Iuliana Yang, Hoeseok Thiele, Lothar Swiss Fed Inst Technol Comp Engn & Networks Lab Zurich Switzerland Ajou Univ Dept ECE Suwon 441749 South Korea

ISBN: (纸本)9781450330503

A widely considered strategy to prevent interference issues on multi-processor systems is to isolate the execution of the individual applications by running each of them on a dedicated virtual guest machine. The amount of computing power available to a single application, however, depends on the other applications running on the system and may change over time. A promising approach to maximize the performance under such conditions is to adapt the application's degree of parallelism when the resources allocated to the application are changed. This enables an application to exploit not more parallelism than required, thereby reducing inter-process communication and scheduling overheads. In this paper, we introduce AdaPNet, a run-time system to execute streaming applications, which are modeled as process networks, efficiently on platforms with dynamic resource allocation. AdaPNet responds to changes in the available resources by first calculating a process network that maximizes the performance of the application on the new resources. Then, AdaPNet transparently transforms the application into the alternative network without discarding the program state. Targeting two many-core systems, we demonstrate that AdaPNet outperforms comparable run-time systems, which do not adapt the degree of parallelism, in terms of speed-up and memory usage.

关键词： Streaming applications process networks run-time adaptivity optimization multi-processor systems

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