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Performance Evaluation of Medical Image Similarity Analysis in a Heterogeneous Architecture

Performance Evaluation of Medical Image Similarity Analysis ...

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27th ieee international Symposium on Computer-Based Medical systems (CBMS)

作者： Ferreira Junior, Jose Raniery Oliveira, Marcelo Costa Freitas, Andre Lage Univ Fed Alagoas Inst Comp Univ Hosp HUPPA Lab Telemed & Med Informat BR-57072900 Maceio Alagoas Brazil

ISBN: (纸本)9781479944354

The volume of data has increased fast, particularly medical images, in big hospitals over the last years. This increase imposes a big challenge to medical specialists: the maintenance of high interpretation accuracy of image-based diagnosis. Computer-Aided Diagnosis software allied to the Content-Based Image Retrieval (CBIR) can provide decision support to specialists by allowing them to find images from a database that are similar to a reference image. However, a well known challenge of CBIR is the processing time that it takes to process all comparisons between the reference image and the image database. This paper proposes a performance evaluation of medical Image Similarity Analysis (ISA) in a heterogeneous single-, multi-and many-core architecture using the high performance parallel OpenCL framework. A CBIR algorithm was implemented to validate the proposal. The algorithm used a Lung Cancer image database with 131,072 Computed Tomography scans, Texture Attributes for image features and Euclidean Distance for image comparison metrics. The results showed that the OpenCL parallelism can increase the performance of ISA, especially using the GPU, with speedups of 3x, 36x and 64x. The results also showed that it is not worth the use of GPU local memory for the Euclidean Distance metrics due to its low performance improvement and high implementation complexity in comparison to the GPU global memory. That being said, GPU is a safer medical CBIR approach than further distributed environments as clusters, cloud and grid computing because GPU usage does not require the patient data to be transfered to other machines.

关键词： Content-based image retrieval medical image similarity analysis heterogeneous computing GPGPU OpenCL

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A Portable and Fast Stochastic Volatility Model Calibration Using multi and many-core Processors 7

A Portable and Fast Stochastic Volatility Model Calibration ...

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7th workshop on High Performance Computational Finance, WHPCF 2014 at the international Conference for High Performance computing, Networking, Storage and Analysis, SC 2014

作者： Dixon, Matthew Lotze, Jorg Zubair, Mohammad Department of Analytics University of San Francisco San FranciscoCA United States Xcelerit 28-32 Upper Pembroke Street Dublin Ireland Department of Computer Science Old Dominion University NorfolkVA United States

ISBN: (纸本)9781479970278

Financial markets change precipitously and on-demand pricing and risk models must be constantly recalibrated to reduce risk. However, certain classes of models are computationally intensive to robustly calibrate to intraday pricesstochastic volatility models being an archetypal example due to the non-convexity of the objective function. In order to accelerate this procedure through parallel implementation,nancial application developers are faced with an ever growing plethora of low-level high-performance computing frameworks such as OpenMP, OpenCL, CUDA, or SIMD intrinsics, and forced to make a trade-off between performance versus the portability,exibility and modularity of the code required to facilitate rapid in-house model development and *** paper describes the acceleration of stochastic volatility model calibration on multi-core CPUs and GPUs using the Xcelerit platform. By adopting a simple dataow programming model, the Xcelerit platform enables the application developer to write sequential, high-level C++ code, without concern for low-level high-performance computing frameworks. This platform provides the portability,exibility and modularity required by application developers. Speedups of up to 30x and 293x are respectively achieved on an Intel Xeon CPU and NVIDIA Tesla K40 GPU, compared to a sequential CPU implementation. The Xcelerit platform implementation is further shown to be equivalent in performance to a low-level CUDA version. Overall, we are able to reduce the entire calibration process time of the sequential implementation from 6;189 seconds to 183:8 and 17:8 seconds on the CPU and GPU respectively without requiring the developer to reimplement in low-level high performance computing frameworks. © 2014 ieee.

关键词： Program processors

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Proceedings - Symposium on Computer Architecture and High Performance computing

Proceedings - Symposium on Computer Architecture and High Pe...

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26th ieee international Symposium on Computer Architecture and High Performance computing workshops, SBAC-PADW 2014

ISBN: (纸本)9781479970148

The proceedings contain 24 papers. The topics discussed include: high-speed restoration of atomic force microscopy images using Tikhonov regularization in GPGPU;video processing on GPU: analysis of data transfer overhead;efficient virtual channel organization and congestion avoidance in multicore NoC systems;impact of serial scaling of multi-threaded programs in many-core era;evaluating performance of deterministic algorithms on a multicore processor of a public cloud;on the evaluation of multi-core systems with SIMD engines for public-key cryptography;energy evaluation for applications with different thread affinities on the Intel Xeon Phi;an introduction to DF-threads and their execution model;high-level dataflow programming for reconfigurable computing;a Hadoop extension to process mail folders and its application to a spam dataset;exploratory analysis of raw data files through dataflows;exploratory analysis of raw data files through dataflows;GBFs: efficient data-sharing on hybrid platforms: towards adding wan-wide elasticity to DFSEs;and BIGHYBRID-a toolkit for simulating MapReduce in hybrid infrastructures.

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Programmable systems-on-Chip for Information Processing 8

Programmable Systems-on-Chip for Information Processing

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8th ieee international Conference on Application of Information and Communication Technologies (AICT)

作者： Sklyarov, Valery Skliarova, Iouilia Univ Aveiro Dept Elect Telecommun & Informat IEETA Aveiro Portugal

ISBN: (纸本)9781479941209

Information processing is a very broad area in which many problems are computationally intensive and thus, they require parallelization and acceleration based on new technologies. The Xilinx Zynq-7000 all programmable system-on-chip can be seen as a very adequate platform permitting application-specific software and problem-targeted hardware to be coupled on a single configurable microchip. The tutorial is dedicated to multi-level software/hardware co-design techniques and system architectures that combine general-purpose computers, multi-core application-specific processing, and accelerators in reconfigurable hardware with emphasis on broad parallelism. Four projects from the scope of data processing, application informatics, parallel algorithms (mapped to hardware), and combinatorial search are briefly characterized and will be demonstrated in fully implemented and ready to test projects that include software and reconfigurable hardware linked with on-chip high-performance interfaces. Particular design examples, potential practical applications, experiments and comparisons will be demonstrated.

关键词： Information processing high-performance computing parallelism programmable systems-on-chip

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multi-CHANNEL IIR FILTERING OF AUDIO SIGNALS USING A GPU

MULTI-CHANNEL IIR FILTERING OF AUDIO SIGNALS USING A GPU

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ieee international Conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Belloch, Jose A. Bank, Balazs Savioja, Lauri Gonzalez, Alberto Valimaki, Vesa Univ Politecn Valencia iTeAm E-46071 Valencia Spain Budapest Univ Technol & Econom Budapest Hungary Aalto Univ Dept Media Technol Espoo Finland Aalto Univ Dept Signal Proc & Acoust Espoo Finland

ISBN: (纸本)9781479928934

In the audio signal processing field, multiple IIR filters are required in many applications. As an example, equalizing a Wave Field Synthesis system requires massive filter processing in real time. Graphics Processing Units (GPUs) are well known for their potential in highly parallel data processing. Up to now, the use of the GPUs for implementing IIR filters has not been clearly tackled in audio processing because of its feedback loop that prevents its total parallelization. However, using the Parallel form of IIR filters, this feedback is reduced, since every single sample is computed in a parallel way. This paper analyzes the performance of multiple IIR filters using GPUs and compares it with a powerful multi-core computer. The proposed GPU implementation can run up to 1256 concurrent IIR filters of order 256th in real time, which means 321,536 total filter order, with a latency time of 0.72 ms (sampling frequency of 44.1 kHz). This demonstrates that GPUs are well suited for computing massive IIR filtering.

关键词： Audio systems IIR filters parallel architectures parallel processing

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Work stealing strategies for multi-core parallel branch-and-bound algorithm using factorial number system

Work stealing strategies for multi-core parallel branch-and-...

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2014 international workshop on Programming Models and Applications for multicores and manycores, PMAM 2014

作者： Leroy, Rudi Mezmaz, Mohand Melab, Nouredine Tuyttens, Daniel LIFL Université Lille1 Villeneuve D'Ascq Inria Lille - Nord Europe France University of Mons Mons Belgium

ISBN: (纸本)9781450326551

many real-world problems in different industrial and economic fields are permutation combinatorial optimization problems. Solving to optimality large instances of these problems, such as the flowshop problem, is a challenge for multi-core computing. This paper proposes four work stealing strategies for the multithreaded factoradic-based branch-and-bound (B&B) algorithm to solve permutation combinatorial problems on multi-core processors. The factoradic, called also factorial number system, is amixed radix numeral system adapted to numbering permutations. In our new parallel strategies, the B&B is based on a matrix of integers instead of a pool of permutations, and work units exchanged between threads are intervals of factoradics instead of sets of nodes. The experiments show that the strategy based on selecting the largest interval is better than the three other strategies in terms of the number of interval sharing events. Furthermore, the worst factoradic-based strategy spends on average 7.2 times less time managing the pool of subproblems than a conventional pool-based parallel B&B algorithm. Categories and Subject Descriptors D.1.3 [Programming Techniques]: Concurrent Programming- Parallel programming;D.2.8 [Software Engineering]: Metrics-Performance measures;G.2.1 [Discrete Mathematics]: Combinatorics- Combinatorial algorithms, Permutations and combinations;G.2.2 [Discrete Mathematics]: Graph Theory-Trees General Terms Algorithms, Performance.

关键词： Parallel processing systems

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High-performance X-ray tomography reconstruction algorithm based on heterogeneous accelerated computing systems 16

High-performance X-ray tomography reconstruction algorithm b...

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16th ieee international Conference on Cluster computing, CLUSTER 2014

作者： Serrano, Estefania Bermejo, Guzman Blas, Javier Garcia Carretero, Jesus University Carlos III Avda. Universidad 30 Leganes28911 Spain

ISBN: (纸本)9781479955480

many medical image processing applications need high processing speed to achieve almost real-time image reconstruction features. Due to that, massively parallel architectures based on accelerators have become very popular in the area, specially GPGPUs. In this paper we show Mangoose++, an application to perform X-Ray Computed Tomography (CT) from medical image based on a new implementation of the FDK algorithm. Mangoose++ have been designed and implemented to exploit the parallelism existing on several hardware accelerators platforms, as GPGPUs and Intel Xeon Phi accelerators. In this paper we show the design and implementation of the application in three types of platforms, multi-core CPU, GPGPU, and Intel Xeon Phi, and the evaluation made to test the performance, resource utilization, and scalability of each platform. Moreover, to avoid hardware dependencies, we have also implemented the application using the OpenACC runtime to check portability and the overhead incurred when using runtimes. The evaluation results show that our solution is faster than recent related works and that, in terms of computation, Intel Xeon Phi and the CUDA-based GPU versions obtain similar results as the problem size increases. Moreover, the evaluation shows that using OpenACC, we have enhanced programmability because there is a single version of the source code. But it also shows that using OpenACC heavily affects performance of Mangoose++, which is reduced in a 50% when compared with the many-core versions, even when it is not so drastical when compared to the CPU version. © 2014 ieee.

关键词： Parallel architectures

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Propagation of Agents to Trusted Organizations

Propagation of Agents to Trusted Organizations

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ieee/WIC/ACM international Joint Conferences on Web Intelligence (WI) and Intelligent Agent Technologies (WI-IAT)

作者： Lawall, Alexander Reichelt, Dominik Schaller, Thomas Hof Univ Inst Informat Syst D-95028 Hof Germany

ISBN: (纸本)9781479941438

In cross-organizational transactions, resolving the responsible agent is always an issue. This is usually done using local address books, directories and similar information sources. The redundant maintenance of such external organizational information causes many discrepancies between the organizational models. This paper describes an approach to overcome this problem. It shows how organizational information of a business partner is stored consistently. Organizations propagate selected internal information to their trusted partners. This includes the organizational structure with its units, roles and agents, as well as relations and responsibilities. Which information is propagated can be adjusted on a fine level of granularity using language expressions.

关键词： business data processing multi-agent systems organisational aspects trusted computing agent propagation business partner cross-organizational transactions information sources language expressions local address books organizational information organizational models organizational structure redundant maintenance trusted organizations trusted partners Companies Customer relationship management Educational institutions Mathematical model Programming cross-organizational organizational meta-model organizational model propagation trust Organizational Models organization structure business data processing Information source Organizational aspects customer relationship management Educational institutions multi-agent systems Companies Programming partnerships Agents Nonprofit Organizations Mathematical Model trust

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Stack-tagged dataflow 26

Stack-tagged dataflow

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26th ieee international Symposium on Computer Architecture and High Performance computing workshops, SBAC-PADW 2014

作者： Santiago, Leandro Marzulo, Leandro A.J. Goldstein, Brunno F. Alves, Tiago A.O. França, Felipe M.G. Dep. de Informática e Ciência da Computação Instituto de Matemática e Estatística - IMe Universidade Do Estado Do Rio de Janeiro - UERJ Rio de Janeiro Brazil Programa de Engenharia de Sistemas e Computação COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro Brazil

ISBN: (纸本)9781479970148

Dynamic Dataflow allows simultaneous execution of instructions in different iterations of a loop, boosting parallelism exploitation. In this model, operands are tagged with their associated instance number, incremented as they go through the loop. Instruction execution is triggered when all input operand with the same tag become available. However, this traditional tagging mechanism often requires the generation of several control instructions to manipulate tags and guarantee the correct matching. To address this problem, this work presents Stack- Tagged Dataflow, a tagging mechanism that uses stacks of tags to reduce control overheads in dataflow, while isolating context from different nested loops. Push instructions at the beginning of loops will create a new context, while Pop instructions, at the end of the loop, will restore the original context tags. Experimental results show that Stack-Tagged Dataflow is a viable solution, suggesting that a hybrid compiling approach can be used to enable Stack- Tags only when needed. © 2014 ieee.

关键词： data flow computing program control structures context isolation dataflow control overhead reduction nested loops pop instructions push instructions stack-tagged dataflow tagging mechanism Assembly Computer architecture Context Libraries Parallel processing Tagging Virtual machining Dataflow Parallel Programming Stack Tag data flow TAGGING program control structures virtual machines Parallel programming Computer Architecture Furnace conveyors PARALLEL PROCESSING (COMPUTERS) Loops Libraries assemblies NESTED LOOPS virtual machining instruction

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HiTS: A high throughput memory scheduling scheme to mitigate denial-of-service attacks in multi-core systems 26

HiTS: A high throughput memory scheduling scheme to mitigate...

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26th international Symposium on Computer Architecture and High Performance computing, SBAC-PAD 2014

作者： Shafaei, Mansour Fei, Yunsi Electrical and Computer Engineering Department Northeastern University BostonMA02115 United States

ISBN: (纸本)9781479969043

Sharing DRAM memory by multiple cores in a computer system potentially exposes the running threads on cores to denial-of-service (DoS) attacks. This issue is usually addressed by memory scheduling schemes that rotate the memory service among threads according to a certain ranking mechanism. These ranking-based schemes, however, often incur many memory banks' row-buffer conflicts which reduce the throughput of DRAM and the entire system. This paper proposes a new ranking-based memory scheduling scheme, called HiTS, to mitigate DoS attacks in multicore systems with the lowest performance degradation. HiTS achieves these by ranking threads according to each thread's memory usage/requirement. HiTS then enforces the ranking in a way that minimum performance overhead would occur and fairness is also balanced. The effectiveness of HiTS is evaluated by simulations with 18 different workloads running on 8- and 16-core machines. The simulation results show up to 15.8% improvements in terms of unfairness reduction and 24.1% in system throughput compared with the best existing scheduling scheme. © 2014 ieee.

关键词： Dynamic random access storage

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