检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

954 篇 会议
20 篇 期刊文献
2 册 图书

馆藏范围

976 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

655 篇 工学
- 597 篇 计算机科学与技术...
- 238 篇 软件工程
- 190 篇 电气工程
- 76 篇 电子科学与技术（可...
- 62 篇 信息与通信工程
- 31 篇 控制科学与工程
- 23 篇 动力工程及工程热...
- 12 篇 仪器科学与技术
- 11 篇 机械工程
- 8 篇 生物医学工程（可授...
- 7 篇 力学（可授工学、理...
- 7 篇 环境科学与工程（可...
- 7 篇 安全科学与工程
- 6 篇 网络空间安全
- 5 篇 材料科学与工程（可...
- 5 篇 建筑学
- 5 篇 交通运输工程
- 5 篇 生物工程
92 篇 理学
- 53 篇 数学
- 27 篇 系统科学
- 19 篇 物理学
- 8 篇 生物学
- 6 篇 化学
- 6 篇 统计学（可授理学、...
89 篇 管理学
- 77 篇 管理科学与工程(可...
- 32 篇 工商管理
- 14 篇 图书情报与档案管...
10 篇 经济学
- 10 篇 应用经济学
8 篇 法学
- 7 篇 社会学
7 篇 医学
4 篇 教育学
- 4 篇 教育学
3 篇 文学
2 篇 农学
2 篇 军事学

主题

75 篇 computer archite...
62 篇 hardware
60 篇 parallel process...
55 篇 multicore proces...
48 篇 computational mo...
37 篇 concurrent compu...
36 篇 high performance...
34 篇 instruction sets
34 篇 multi-core
33 篇 graphics process...
31 篇 scalability
31 篇 cloud computing
30 篇 parallel program...
29 篇 programming
29 篇 program processo...
29 篇 graphics process...
27 篇 kernel
25 篇 embedded systems
24 篇 conferences
24 篇 resource managem...

机构

9 篇 ohio state univ ...
5 篇 saitama univ gra...
4 篇 ohio state univ ...
3 篇 saitama universi...
3 篇 vienna universit...
3 篇 oak ridge natl l...
3 篇 graduate school ...
3 篇 fraunhofer igd t...
3 篇 center for compu...
3 篇 karlsruhe instit...
3 篇 oak ridge natl l...
3 篇 beihang univ sch...
2 篇 penn state univ ...
2 篇 uppsala univ upp...
2 篇 seoul natl univ ...
2 篇 coll william & m...
2 篇 china university...
2 篇 waseda univ dept...
2 篇 tsinghua univers...
2 篇 national univers...

作者

6 篇 takuya azumi
6 篇 panda d. k.
6 篇 azumi takuya
5 篇 subramoni hari
5 篇 shingo igarashi
5 篇 benini luca
4 篇 tatsuya horiguch...
4 篇 tasuku ishigooka
4 篇 petiton serge
4 篇 el-ghazawi tarek
4 篇 sato mitsuhisa
4 篇 amano hideharu
3 篇 liu bo
3 篇 klasky scott
3 篇 dongarra jack
3 篇 varbanescu ana l...
3 篇 qian depei
3 篇 sriram krishnamo...
3 篇 weichslgartner a...
3 篇 alam sadaf r.

语言

967 篇 英文
8 篇 其他
1 篇 中文

检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 976 条记录，以下是451-460 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

An Implementation of Block Conjugate Gradient Algorithm on CPU-GPU Processors 1

An Implementation of Block Conjugate Gradient Algorithm on C...

引用

1st international workshop on Hardware-Software Co-Design for High Performance computing (Co-HPC)

作者： Ji, Hao Sosonkina, Masha Li, Yaohang Old Dominion Univ Dept Comp Sci Norfolk VA 23529 USA Old Dominion Univ Dept Modeling Simulat & Visualizat Engn Norfolk VA 23529 USA

ISBN: (纸本)9781479975648

In this paper, we investigate the implementation of the Block Conjugate Gradient (BCG) algorithm on CPU-GPU processors. By analyzing the performance of various matrix operations in BCG, we identify the main performance bottleneck in constructing new search direction matrices. Replacing the QR decomposition by eigendecomposition of a small matrix remedies the problem by reducing the computational cost of generating orthogonal search directions. Moreover, a hybrid (offload) computing scheme is designed to enables the BCG implementation to handle linear systems with large, sparse coefficient matrices that cannot fit in the GPU memory. The hybrid scheme offloads matrix operations to GPU processors while helps hide the CPU-GPU memory transaction overhead. We compare the performance of our BCG implementation with the one on CPU with Intel Xeon Phi coprocessors using the automatic offload mode. With sufficient number of right hand sides, the CPU-GPU implementation of BCG can reach speedup of 2.61 over the CPU-only implementation, which is significantly higher than that of the CPU-Intel Xeon Phi implementation.

关键词： Block Conjugate Gradient multi-core CPU Graphics Processing Unit Intel Xeon Phi Performance Evaluation

来源：评论

学校读者我要写书评

暂无评论

Analysis and Realization of Relaxed Consistency Memory Model for multi-core CPU or GPU 5th

Analysis and Realization of Relaxed Consistency Memory Model...

引用

5th international Conference on Confluence - The Next Generation Information Technology Summit (Confluence)

作者： Mohanty, Ramanarayan Behera, Dipti Prakash Routray, Aurobinda Indian Inst Technol Adv Technol Dev Ctr Kharagpur 721302 W Bengal India Indian Inst Technol Dept Reliabil Engg Kharagpur 721302 W Bengal India Indian Inst Technol Dept Elect Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781479942367

Parallel and distributed systems that support the shared memory paradigm are becoming widely accepted in many areas of computing. The memory consistency model of a shared-memory multiprocessor system influences both the performance and the programmability of the system. Under optimal condition it is found that multithreading contributes to more than 50 percent of performance improvement, while the improvement from Relaxed Consistency Memory (RCM) models varies between 30-40 percent of total performance gain. The relaxed consistency memory model has been realized on a Graphics Processing Unit (GPU) using Open computing Language (OpenCL) as the programming language. This memory model has been applied on a case study of high order matrix multiplication and their performance has been analysed in terms of two metrics: GPU Computation Percentage (GCP) and GPU Load Balance (GLB). With sufficient parallelism and high PCIe data transfer bandwidth, the RCM model on GPU gives the better performance in comparison to a sequential model on CPU.

关键词： Graphics Processing Unit GPU Computation Percentage GPU Load Balance OpenCL Relaxed Consistency Memory

来源：评论

学校读者我要写书评

暂无评论

Managing GPU Concurrency in Heterogeneous Architectures 47

Managing GPU Concurrency in Heterogeneous Architectures

引用

47th Annual ieee/ACM international Symposium on Microarchitecture (MICRO)

作者： Kayiran, Onur Nachiappan, Nachiappan Chidambaram Jog, Adwait Ausavarungnirun, Rachata Kandemir, Mahmut T. Loh, Gabriel H. Mutlu, Onur Das, Chita R. Penn State Univ University Pk PA 16802 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Adv Micro Devices Inc Sunnyvale CA 94088 USA

ISBN: (纸本)9781479969982

Heterogeneous architectures consisting of general-purpose CPUs and throughput-optimized GPUs are projected to be the dominant computing platforms for many classes of applications. The design of such systems is more complex than that of homogeneous architectures because maximizing resource utilization while minimizing shared resource interference between CPU and GPU applications is difficult. We show that GPU applications tend to monopolize the shared hardware resources, such as memory and network, because of their high thread-level parallelism (TLP), and discuss the limitations of existing GPU-based concurrency management techniques when employed in heterogeneous systems. To solve this problem, we propose an integrated concurrency management strategy that modulates the TLP in GPUs to control the performance of both CPU and GPU applications. This mechanism considers both GPU core state and system-wide memory and network congestion information to dynamically decide on the level of GPU concurrency to maximize system performance. We propose and evaluate two schemes: one (CM-CPU) for boosting CPU performance in the presence of GPU interference, the other (CM-BAL) for improving both CPU and GPU performance in a balanced manner and thus overall system performance. Our evaluations show that the first scheme improves average CPU performance by 24%, while reducing average GPU performance by 11%. The second scheme provides 7% average performance improvement for both CPU and GPU applications. We also show that our solution allows the user to control performance trade-offs between CPUs and GPUs.

关键词： concurrency control graphics processing units multi-threading parallel architectures performance evaluation resource allocation CM-BAL CM-CPU CPU performance GPU core state GPU interference GPU performance GPU-based concurrency management techniques TLP general-purpose CPU heterogeneous architectures heterogeneous systems homogeneous architectures integrated concurrency management strategy network congestion information resource utilization shared hardware resources shared resource interference minimization system-wide memory thread-level parallelism throughput-optimized GPU Bandwidth Central Processing Unit Computer architecture Concurrent computing Graphics processing units Resource management System performance CPU-GPU GPUs concurrency resource management scheduling central processing units Graphics Processing Unit Resource utilization management of resources GRAPPER PICK UP System performance Concurrency HETEROGENEOUS SYSTEM multithreading hardware resource Concurrency control Parallel architectures Computer Architecture Parallel programming Bandwidth

来源：评论

学校读者我要写书评

暂无评论

2014 international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014

2014 International Conference on Hardware/Software Codesign ...

引用

2014 international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014

ISBN: (纸本)9781450330510

The proceedings contain 35 papers. The topics discussed include: HEFT: a hybrid system-level framework for enabling energy-efficient fault-tolerance in NoC based MPSoCs;an efficient technique for computing importance measures in automatic design of dependable embedded systems;towards scalable symbolic routing for multi-objective networked embedded system design and optimization;hardware/software co-design for a wireless sensor network platform;a PCM translation layer for integrated memory and storage management;leveraging microarchitectural side channel information to efficiently enhance program control flow integrity;saving energy without defying deadlines on mobile GPU-based heterogeneous systems;prediction and control of bursty cloud workloads: a fractal framework;TSP: thermal safe power - efficient power budgeting for many-core systems in dark silicon;and flattening-based mapping of imperfect loop nests for CGRA.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Exploiting distributed and shared memory hierarchies with Hitmap

Exploiting distributed and shared memory hierarchies with Hi...

引用

international Conference on High Performance computing & Simulation (HPCS)

作者： Moreton-Fernandez, Ana Gonzalez-Escribano, Arturo Llanos, Diego R. Univ Valladolid Dept Informat Valladolid Spain

ISBN: (纸本)9781479953134

Current multicomputers are typically built as interconnected clusters of shared-memory multicore computers. A common programming approach for these clusters is to simply use a message-passing paradigm, launching as many processes as cores available. Nevertheless, to better exploit the scalability of these clusters and highly-parallel multicore systems, it is needed to efficiently use their distributed-and shared-memory hierarchies. This implies to combine different programming paradigms and tools at different levels of the program design. This paper presents an approach to ease the programming for mixed distributed and shared memory parallel computers. The coordination at the distributed memory level is simplified using Hitmap, a library for distributed computing using hierarchical tiling of data structures. We show how this tool can be integrated with shared-memory programming models and automatic code generation tools to efficiently exploit the multicore environment of each multicomputer node. This approach allows to exploit the most appropriate techniques for each model, easily generating multilevel parallel programs that automatically adapt their communication and synchronization structures to the target machine. Our experimental results show how this approach mimics or even improves the best performance results obtained with manually optimized codes using pure MPI or OpenMP models.

关键词： Computational modeling Indexes Layout Libraries Programming Synchronization Topology Programming Computational modeling layouts Libraries topology object computer Social Hierarchy multi-core processors memory hierarchy

来源：评论

学校读者我要写书评

暂无评论

High-Radix On-chip Networks with Low-Radix Routers 33

High-Radix On-chip Networks with Low-Radix Routers

引用

33rd ieee/ACM international Conference on Computer-Aided Design (ICCAD)

作者： Jain, Animesh Parikh, Ritesh Bertacco, Valeria Univ Michigan Dept Comp Sci & Engn Ann Arbor MI 48109 USA

ISBN: (纸本)9781479962785

Networks-on-chip (NoCs) have become increasingly widespread in recent years due to the extensive integration of many components in modern multicore processors and SoC designs. One of the fundamental tradeoffs in NoC design is the radix of its constituent routers. While high-radix routers enable a richly connected and low diameter network, low-radix routers allow for a small silicon area. Since the NoC consumes a significant portion of the on-chip resources, naively deploying an expensive high-radix network is not a practical option. In this work, we present a novel solution to provide high-radix like performance at a cost similar to that of a low-radix network. Our solution leverages the irregularity in runtime communication patterns to provide short low-latency paths between frequently communicating nodes, while infrequently communicating pairs rely on longer paths. To this end, it leverages a flexible topology reconfiguration infrastructure with abundantly available links between routers (in accordance to a high-radix topology) that are decoupled from scarcely available router ports (similar to a low-radix topology). Network links are bound to router ports at runtime to form connected and deadlock-free topologies. Binding selections are based on the traffic patterns observed, which are synthesized through a distributed statistics-collection framework. Our experiments on a 64-node CMP, running multiprogrammed workloads, show that we can reduce average network latency by 19% over an area-and power-comparable mesh NoC. The latency improvements for non-uniform synthetic traffic are above 30%.

关键词： chemical mechanical polishing multiprocessing systems network-on-chip CMP NoC design SoC designs deadlock-free topologies high-radix on-chip networks low-radix routers multicore processors networks-on-chip multiplexing Network topology Ports (Computers) Routing Runtime Three-dimensional displays Topology network-on-chip Chemical mechanical polishing Runtime three-dimensional displays multiprocessing systems Routers topology Basic metabolic panel cytidine monophosphate multi-core processors Network topology multiPLEXOR Network routing network delay traffic patterns

来源：评论

学校读者我要写书评

暂无评论

Holographic algorithms for on-chip, non-boolean computing

Holographic algorithms for on-chip, non-boolean computing

引用

international workshop on Computational Electronics

作者： G. Csaba A. Papp W. Porod Center for Nano Science and Technology University of Notre Dame Notre Dame IN USA

It is widely believed that the established route of microelectronic scaling is approaching its end: further downscaling of semiconductor devices carries disproportionate penalties in power consumption and poses fundamental fabrication challenges. Instead of scaling of devices, Moore's law is now increasingly about scaling computing systems: single-core devices toward larger, multi-core systems. While there are known programming methodologies for parallelizing program codes to a few threads, only very few, special-purpose applications lend themselves to parallelization on very large numbers of cores. This motivates our quest for studying computing paradigms and algorithms that are inherently parallel [1]. Holographic / optical computing is a perfect example of such algorithms: the results of a computation are given by an interference pattern formation of many light rays (see Fig. 1 for an illustration [1]). Optical systems are impractical to realize on-chip. For this reason, we explore routes to design holographic algorithms that can be naturally integrated with microelectronic technologies and require no optical hardware. Two approaches will be discussed in this paper.

关键词： Vectors Mirrors Optical filters Fourier transforms Holography Holographic optical components Optical films

来源：评论

学校读者我要写书评

暂无评论

Effects of structured parallelism by parallel design patterns on embedded hard real-time systems

Effects of structured parallelism by parallel design pattern...

引用

ieee international Conference on Embedded and Real-Time computing systems and Applications (RTCSA)

作者： Ralf Jahr Mike Gerdes Theo Ungerer Haluk Ozaktas Christine Rochange Pavel G. Zaykov University of Augsburg Augsburg Germany Université Paul Sabatier Toulouse France Honeywell International s.r.o. Brno Czech Republic

Parallel multi-threaded applications are needed to gain advantage from multi- and many-core processors. Such processors are more frequently considered for embedded hard real-time with defined timing guarantees, too. The static timing analysis, which is one way to calculate the worst-case execution time (WCET) of parallel applications, is complex and time-consuming due to the difficulty to analyze the interferences of threads and the high annotation effort to resolve it.

关键词： Synchronization Parallel processing Software Real-time systems Pipelines Message systems

来源：评论

学校读者我要写书评

暂无评论

Scaling and analyzing the stencil performance on multi-core and many-core architectures

Scaling and analyzing the stencil performance on multi-core ...

引用

international Conference on Parallel and Distributed systems (ICPADS)

作者： Lin Gan Haohuan Fu Wei Xue Yangtong Xu Chao Yang Xinliang Wang Zihong Lv Yang You Guangwen Yang Kaijian Ou Tsinghua University Beijing Beijing CN Institute of Software Chinese Academy of Sciences Beijing CN China Sciences Group Holding Co Ltd Beijing Beijing CN

Stencils are among the most important and time-consuming kernels in many applications. While stencil optimization has been a well-studied topic on CPU platforms, achieving higher performance and efficiency for the evolving numerical stencils on the more recent multi-core and many-core architectures is still an important issue. In this paper, we explore a number of different stencils, ranging from a basic 7-point Jacobi stencil to more complex high-order stencils used in finer numerical simulations. By optimizing and analyzing those stencils on the latest multi-core and many-core architectures (the Intel Sandy Bridge processor, the Intel Xeon Phi coprocessor, and the NVIDIA Fermi C2070 and Kepler K20x GPUs), we investigate the algorithmic and architectural factors that determine the performance and efficiency of the resulting designs. While multi-threading, vectorization, and optimization on cache and other fast buffers are still the most important techniques that provide performance, we observe that the different memory hierarchy and the different mechanism for issuing and executing parallel instructions lead to the different performance behaviors on CPU, MIC and GPU. With vector-like processing units becoming the major provider of computing power on almost all architectures, the compiler's inability to align all the computing and memory operations would become the major bottleneck from getting a high efficiency on current and future platforms. Our specific optimization of the complex WNAD stencil on GPU provides a good example of what the compiler could do to help.

关键词： Kernel Computer architecture Optimization Graphics processing units Microwave integrated circuits Registers Instruction sets

来源：评论

学校读者我要写书评

暂无评论

Enabling QoS support for multi-core message broker in Publish/Subscribe system

Enabling QoS support for multi-core message broker in Publis...

引用

ieee international Advance computing Conference, IACC

作者： Medha Shah D.B. Kulkarni Walchand College of Engineering Sangli Maharashtra India

ISBN: (纸本)9781479925735

Publish/Subscribe systems; establish a connection between subscribers (consumers) and publishers (producers) of events, behaving as a mediator between subscribers and publishers. So core functionality of this system is to match the events with the subscriptions and send these events to subscribers whose subscriptions are related to the events. Publish/Subscribe system is used in many application domains, ranging from smart grid to transportations. But, traditional Publish/Subscribe systems are unable to handle these emerging IoT (Internet of Things) applications due to its lack of QoS capability. To meet the requirements for QoS in IoT, modification in message broker is done which introduces the ability to schedule the computations resources. We propose two techniques of resource selection that makes better resource utilization. Performance of the system is measured by taking number of failures as a parameter. Experimental result shows that, performing good resource selection decreases the number of failures by 3%.

关键词： Quality of service Subscriptions Scheduling Vectors Processor scheduling Conferences Smart grids

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共98页 << < 42 43 44 45 46 47 48 49 50 51 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：