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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 976 条记录，以下是461-470 订阅

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Voltage Island Aware Energy Efficient Scheduling of Real-Time Tasks on multi-core Processors

Voltage Island Aware Energy Efficient Scheduling of Real-Tim...

引用

ieee international Conference on High Performance computing and Communications (HPCC)

作者： Jun Liu Jinhua Guo Department of Computer and Information Science University of Michigan at Dearborn USA

ISBN: (纸本)9781479961245

There have been many energy-efficient real-time task scheduling research works on multi-core processors. Most assume that the voltage/frequency level for each core can be individually controlled by using Dynamic Voltage and Frequency Scaling (DVFS). However, providing individual voltage for each core can be very complicated and expensive. Most modern processors adopt voltage islands, in which a group of cores in an island always operate at the same voltage level. We propose a Voltage Island Largest Capacity First (VILCF) algorithm for energy efficient scheduling of periodic real-time tasks on multi-core processors. It achieves great energy efficiency by fully utilizing the remaining capacity of an island before turning on more islands or increasing the voltage level of the current islands. We provide detailed theoretical analysis of the approximation ratio of the proposed VILCF algorithm in terms of energy efficiency. Furthermore, our experiment results show that VILCF significantly outperforms the existing algorithms when there are more than one cores in each voltage island.

关键词： multicore processing Energy consumption Schedules Indexes Real-time systems Power demand Processor scheduling

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Transforming Java programs for concurrency using Double-Checked Locking pattern

Transforming Java programs for concurrency using Double-Chec...

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ieee international Symposium on Performance Analysis of systems and Software

作者： Kazuaki Ishizaki Shahrokh Daijavad Toshio Nakatani IBM Research Tokyo IBM Research Almaden

Java provides a synchronized construct for multi-core programming with many workloads. However, naïve use of the synchronized construct causes performance scalability problems due to lock contention. One of the sources of lock contentions is a synchronized collection class. There are known concurrency code patterns to alleviate lock contentions such as a Concurrent Collection (CC), Read-Write Lock (RWL), and Double-Checked Locking (DCL). To date, there is no algorithm to transform a program using DCL. This paper describes steps on how to rewrite synchronized blocks using DCL.

关键词： Synchronization Java Scalability Concurrent computing Transforms Libraries Programming

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HiTS: A High Throughput Memory Scheduling Scheme to Mitigate Denial-of-Service Attacks in multi-core systems

HiTS: A High Throughput Memory Scheduling Scheme to Mitigate...

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international Symposium on Computer Architecture and High Performance computing (SBAC-PAD)

作者： Mansour Shafaei Yunsi Fei Electrical & Computer Engineering Department Northeastern University Boston Massachusetts

Sharing DRAM memory by multiple cores in a computer system potentially exposes the running threads on cores to denial-of-service (DoS) attacks. This issue is usually addressed by memory scheduling schemes that rotate the memory service among threads according to a certain ranking mechanism. These ranking-based schemes, however, often incur many memory banks' row-buffer conflicts which reduce the throughput of DRAM and the entire system. This paper proposes a new ranking-based memory scheduling scheme, called HiTS, to mitigate DoS attacks in multicore systems with the lowest performance degradation. HiTS achieves these by ranking threads according to each thread's memory usage/requirement. HiTS then enforces the ranking in a way that minimum performance overhead would occur and fairness is also balanced. The effectiveness of HiTS is evaluated by simulations with 18 different workloads running on 8- and 16-core machines. The simulation results show up to 15.8% improvements in terms of unfairness reduction and 24.1% in system throughput compared with the best existing scheduling scheme.

关键词： Instruction sets Random access memory Benchmark testing Switches Throughput Computer crime Message systems

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High-performance X-ray tomography reconstruction algorithm based on heterogeneous accelerated computing systems

High-performance X-ray tomography reconstruction algorithm b...

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ieee international Conference on Cluster computing

作者： Estefania Serrano Guzman Bermejo Javier Garcia Blas Jesus Carretero University Carlos III Leganes Spain

many medical image processing applications need high processing speed to achieve almost real-time image reconstruction features. Due to that, massively parallel architectures based on accelerators have become very popular in the area, specially GPGPUs. In this paper we show Mangoose++, an application to perform X-Ray Computed Tomography (CT) from medical image based on a new implementation of the FDK algorithm. Mangoose++ have been designed and implemented to exploit the parallelism existing on several hardware accelerators platforms, as GPGPUs and Intel Xeon Phi accelerators. In this paper we show the design and implementation of the application in three types of platforms, multi-core CPU, GPGPU, and Intel Xeon Phi, and the evaluation made to test the performance, resource utilization, and scalability of each platform. Moreover, to avoid hardware dependencies, we have also implemented the application using the OpenACC runtime to check portability and the overhead incurred when using runtimes. The evaluation results show that our solution is faster than recent related works and that, in terms of computation, Intel Xeon Phi and the CUDA-based GPU versions obtain similar results as the problem size increases. Moreover, the evaluation shows that using OpenACC, we have enhanced programmability because there is a single version of the source code. But it also shows that using OpenACC heavily affects performance of Mangoose++, which is reduced in a 50% when compared with the many-core versions, even when it is not so drastical when compared to the CPU version.

关键词： Programming Parallel processing Graphics processing units Instruction sets Image reconstruction Computed tomography Optimization

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DraMon: Predicting memory bandwidth usage of multi-threaded programs with high accuracy and low overhead

DraMon: Predicting memory bandwidth usage of multi-threaded ...

引用

ieee Symposium on High-Performance Computer Architecture

作者： Wei Wang Tanima Dey Jack W. Davidson Mary Lou Soffa Department of Computer Science University of Virginia

Memory bandwidth severely limits the scalability and performance of today's multi-core systems. Because of this limitation, many studies that focused on improving multi-core scalability rely on bandwidth usage predictions to achieve the best results. However, existing bandwidth prediction models have low accuracy, causing these studies to have inaccurate conclusions or perform sub-optimally. Most of these models make predictions based on the bandwidth usage samples of a few trial runs. many factors that affect bandwidth usage and the complex DRAM operations are overlooked. This paper presents DraMon, a model that predicts bandwidth usages for multi-threaded programs with low overhead. It achieves high accuracy through highly accurate predictions of DRAM contention and DRAM concurrency, as well as by considering a wide range of hardware and software factors that impact bandwidth usage. We implemented two versions of DraMon: DraMon-T, a memory-trace based model, and DraMon-R, a run-time model which uses hardware performance counters. When evaluated on a real machine with memory-intensive benchmarks, DraMon-T has average accuracies of 99.17% and 94.70% for DRAM contention predictions and bandwidth predictions, respectively. DraMon-R has average accuracies of 98.55% and 93.37% for DRAM contention and bandwidth predictions respectively, with only 0.50% overhead on average.

关键词： Random access memory Bandwidth Accuracy Predictive models Concurrent computing Instruction sets Mathematical model

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Harnessing Unreliable cores in Heterogeneous Architecture: The PyDac Programming Model and Runtime

Harnessing Unreliable Cores in Heterogeneous Architecture: T...

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international Conference on Dependable systems and Networks (DSN)

作者： Bin Huang Ron Sass Nathan Debardeleben Sean Blanchard Reconfigurable Computing Systems Laboratory University of North Carolina at Charlotte Charlotte North Carolina USA Ultrascale Systems Research Center Los Alamos National Laboratory Los Alamos NM USA

Heterogeneous many-core architectures combined with scratch-pad memories are attractive because they promise better energy efficiency than conventional architectures and a good balance between single-thread performance and multi-thread throughput. However, programmers will need an environment for finding and managing the large degree of parallelism, locality, and system resilience. We propose a Python-based task parallel programming model called PyDac to support these objectives. PyDac provides a two-level programming model based on the divide-and-conquer strategy. The PyDac runtime system allows threads to be run on unreliable hardware by dynamically checking the results without involvement from the programmer. To test this programming model and runtime, an unconventional heterogeneous architecture consisting of PowerPC and ARM cores was developed and emulated on an FPGA device. We inject faults during the execution of micro-benchmarks and show that through the use of double and triple modular redundancy we are able to complete the benchmarks with the correct results while only incurring a proportional performance penalty.

关键词： Runtime Programming Computer architecture Redundancy Resilience Hardware

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Quantifying the performance impacts of using local memory for many-core processors

Quantifying the performance impacts of using local memory fo...

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2013 ieee 6th international workshop on multi-/many-core computing systems, MuCoCoS 2013

作者： Fang, Jianbin Sips, Henk Varbanescu, Ana Lucia Delft University of Technology Netherlands University of Amsterdam Netherlands

ISBN: (纸本)9781479910106

Due to the increasing complexity of multi/many-core architectures (with their mix of caches and scratch-pad memories) and applications (with different memory access patterns), the performance of many workloads becomes increasingly variable. In this work, we address one of the main causes for this performance variability: the efficiency of the memory system. Specifically, based on an empirical evaluation driven by memory access patterns, we qualify and partially quantify the performance impact of using local memory in multi/many-core processors. To do so, we systematically describe memory access patterns (MAPs) in an application-agnostic manner. Next, for each identified MAP, we use OpenCL (for portability reasons) to generate two microbenchmarks: a 'naive' version (without local memory) and 'an optimized' version (using local memory). We further evaluate both of them on typically used multi-core and many-core platforms, and we log their performance. What we eventually obtain is a local memory performance database, indexed by various MAPs and platforms. To show how our database can be used to provide information on local memory usage, we demonstrate a scenario for performance prediction: given an application, its MAPs, and a platform, a query in the database can indicate the performance impact of using local memory for the given application. This indication can be used to either avoid the hassle of implementing optimizations with too little gain or, alternatively, give a rough prediction of the performance gain. © 2013 ieee.

关键词： Database systems

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Techniques for System of systems Engineering in Construction of a Smart Tourism Industry Information System

Techniques for System of Systems Engineering in Construction...

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16th international Conference on Advanced Communication Technology (ICACT)

作者： Bai, Liming Guangxi Univ Finance & Econ Coll Business Adm Nanning 530003 Guangxi Zhuang Peoples R China

ISBN: (纸本)9788996865032

Currently, as many disciplines begin to cultivate a set of core methodologies, system of systems engineering (SoSE), which has its root in context of military programming, becomes a significant research focus and provides a new perspective to solve the emerging "system of systems" challenges in industrial analysis. Meanwhile, modern communication and information technologies have provided greater possibilities for socio-economic sectors to execute smarter decisions, and these technologies may advance the industrial application of SoSE. Therefore, targeting the rareness of government-oriented intelligent decision support system (DSS), and guided by the underlying system of systems thinking, this paper proposes a technical framework for designing a policy maker-responsive smart information system which focuses: (1) system of systems structural architecting;(2) geographical simulation using time-series remotely sensed data, GIS instrument and simulation bodies such as cellular automata (CA) and multi-agent systems (MAS);(3) SoS evolution description through network analysis and intelligent computing;(4) measurement of SoS effectiveness with two-tier and four-grade method;and (5) SoSE program for industrial optimization. Its application in tourism analysis will provide a smarter base for industrial policy-making, planning and forecasting, and will help reduce risk and cost in industrial restructuring. For this relatively new field of SoSE application, tools and methods are not perfect, so it is important to draw together academia, government, industrial organizations and enterprises to collaborate for further valuable achievement.

关键词： System of systems engineering (SoSE) geographical simulation tourism smart industry information system intelligent computing

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Automatic extraction of multi-objective aware parallelism for heterogeneous MPSoCs

Automatic extraction of multi-objective aware parallelism fo...

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2013 ieee 6th international workshop on multi-/many-core computing systems, MuCoCoS 2013

作者： Cordes, Daniel Engel, Michael Neugebauer, Olaf Marwedel, Peter TU Dortmund University Dortmund Germany

ISBN: (纸本)9781479910106

Heterogeneous MPSoCs are used in a large fraction of current embedded systems. In order to efficiently exploit the available processing power, advanced parallelization techniques are required. In addition to consider performance variances between heterogeneous cores, these methods have to be multi-objective aware to be useful for resource restricted embedded systems. This multi-objective optimization requirement results in an explosion of the design space size. As a consequence, efficient approaches are required to find promising solution candidates. In this paper, we present the first portable genetic algorithm-based approach to speed up ANSI-C applications by combining extraction techniques for task-level and pipeline parallelism for heterogeneous multicores while considering additional objectives. Using our approach enables embedded system designers to select a parallelization of an application from a set of Pareto-optimal solutions according to the performance and energy consumption requirements of a given system. The evaluation of a large set of typical embedded benchmarks shows that our approach is able to generate solutions with low energy consumption, high speedup, low communication overhead or useful trade-offs between these three objectives. © 2013 ieee.

关键词： Embedded systems

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multi-CHANNEL IIR FILTERING OF AUDIO SIGNALS USING A GPU

MULTI-CHANNEL IIR FILTERING OF AUDIO SIGNALS USING A GPU

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ieee international Conference on Acoustics, Speech and Signal Processing

作者： Jose A. Belloch Balazs Bank Lauri Savioja Alberto Gonzalez Vesa Valimaki iTeAm Universitat Politecnica de Valencia Valencia Spain Budapest University of Technology and Economics Budapest Hungary Dept. of Media Technology Aalto University Espoo Finland

ISBN: (纸本)9781479928941

In the audio signal processing field, multiple IIR filters are required in many applications. As an example, equalizing a Wave Field Synthesis system requires massive filter processing in real time. Graphics Processing Units (GPUs) are well known for their potential in highly parallel data processing. Up to now, the use of the GPUs for implementing IIR filters has not been clearly tackled in audio processing because of its feedback loop that prevents its total parallelization. However, using the Parallel form of IIR filters, this feedback is reduced, since every single sample is computed in a parallel way. This paper analyzes the performance of multiple IIR filters using GPUs and compares it with a powerful multi-core computer. The proposed GPU implementation can run up to 1256 concurrent IIR filters of order 256th in real time, which means 321,536 total filter order, with a latency time of 0.72 ms (sampling frequency of 44.1 kHz). This demonstrates that GPUs are well suited for computing massive IIR filtering.

关键词： Graphics processing units Real-time systems Instruction sets multicore processing Acoustics Computers Signal processing

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