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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 976 条记录，以下是471-480 订阅

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Novel parallel method for mining frequent patterns on multi-core shared memory systems

Novel parallel method for mining frequent patterns on multi-...

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2013 international workshop on Data-Intensive Scalable computing systems, DISCS 2013

作者： Vu, Lan Alaghband, Gita Dept. of Computer Science and Engineering University of Colorado Denver 1380 Lawrence St. DenverCO80204 United States

ISBN: (纸本)9781450325066

Frequent pattern mining is an important problem in data mining with many practical applications. Current parallel methods for mining frequent patterns unstably perform for different database types and under-utilize the benefits of multi-core shared memory machines. We present ShaFEM, a novel parallel frequent pattern mining method, to address these issues. Our method can dynamically adapt to the data characteristics to efficiently perform on both sparse and dense databases. Its parallel mining lock free approach minimizes the synchronization needs and maximizes the data independence to enhance the scalability. Its structure lends itself well for dynamic job scheduling resulting in well-balanced load on new multi-core shared memory architectures. We evaluate ShaFEM on a 12-core multi-socket server and find that our method runs 2.1-5.8 times faster than the state-of-the-art parallel method. For some test cases, we have shown that ShaFEM saves 4.9 days and 12.8 hours of execution time over the compared method. Copyright 2013 ACM.

关键词： Database systems

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Parallel Mutual Information Based Construction of Whole-Genome Networks on the Intel (R) Xeon Phi (TM) Coprocessor

Parallel Mutual Information Based Construction of Whole-Geno...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： Sanchit Misra Kiran Pamnany Srinivas Aluru Parallel Computing Lab Intel Corporation Bangalore India School of Computational Science and Engineering Georgia Institute of Technology Atlanta USA

Construction of whole-genome networks from large-scale gene expression data is an important problem in systems biology. While several techniques have been developed, most cannot handle network reconstruction at the whole-genome scale, and the few that can, require large clusters. In this paper, we present a solution on the Intel (R) Xeon Phi (TM) coprocessor, taking advantage of its multi-level parallelism including many x86-based cores, multiple threads per core, and vector processing units. We also present a solution on the Intel (R) Xeon (R) processor. Our solution is based on TINGe, a fast parallel network reconstruction technique that uses mutual information and permutation testing for assessing statistical significance. We demonstrate the first ever inference of a plant whole genome regulatory network on a single chip by constructing a 15,575 gene network of the plant Arabidopsis thaliana from 3,137 microarray experiments in only 22 minutes. In addition, our optimization for parallelizing mutual information computation on the Intel Xeon Phi coprocessor holds out lessons that are applicable to other domains.

关键词： Vectors Joints Coprocessors Mutual information Optimization Splines (mathematics) Arrays

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Towards a Configurable many-core Accelerator for FPGA-based Embedded systems

Towards a Configurable Many-core Accelerator for FPGA-based ...

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8th international workshop on Reconfigurable and Communication-Centric systems-on-Chip (ReCoSoC)

作者： Ramirez, Marco Daneshtalab, Masoud Liljeberg, Pasi Plosila, Juha Univ Turku Dept Informat Technol SF-20500 Turku Finland

ISBN: (纸本)9781467361804

Hardware accelerators release the general purpose processor of a system from very compute-demanding tasks. This work presents a Configurable many-core Accelerator for FPGA-based systems, named CoMA. Its architecture combines an array of processing cores interconnected by an NoC, with an I/O interface based on the AXI protocol. CoMA provides the designer with a system abstraction layer that facilitates task partitioning and peripheral access. The implementation of the I/O interface was verified through simulation, and synthesized for an FPGA.

关键词： electronic engineering computing embedded systems field programmable gate arrays network-on-chip

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Cross Resource Optimisation of Database Functionality across Heterogeneous Processors

Cross Resource Optimisation of Database Functionality across...

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international Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Eoghan O'Neill John McGlone J.G.F Coutinho Andrew Doole Carmelo Ragusa O. Pell P. Sanders SAP HANA Cloud Comput. Syst. Eng. UK Systems Engineering SAP HANA Cloud Computing Belfast UK Imperial College London UK Maxeler Technologies UK

Significant application performance improvements can be achieved by heterogeneous compute technologies, such as multi-core CPUs, GPUs and FPGAs. The HARNESS project is developing architectural principles that enable the next generation cloud platforms to incorporate such devices thereby vastly increasing performance, reducing energy consumption, and lowering associated cost profiles. Along with management and integration of such devices in a cloud environment, a key issue is enabling enterprise-level software to make effective use of such compute devices. A major obstacle in adopting heterogeneous compute resources is the requirement that at design time the developer must decide on which device to execute portions of the application. For an interactive application, such as SAP HANA where there are many on-going tasks and processes, this type of decision is impossible to predict at design time. What is required is the ability to decide, at run-time, the optimal compute device to execute a task. This paper extends upon existing work on SHEPARD to support non-OpenCL devices. SHEPARD decouples application development from the target platform and enables the required run-time allocation of tasks to heterogeneous computing devices. This paper establishes SHEPARD's capability to: (1) select the appropriate compute device to execute tasks, (2) dynamically load the device application code at runtime, and (3) execute the application logic. Experiments demonstrate how SHEPARD optimises the execution of a SAP HANA database management function across heterogeneous compute devices and perform automatic run-time task allocation.

关键词： Runtime Performance evaluation Resource management Field programmable gate arrays Databases Dictionaries Kernel

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Safe Virtual Interrupts Leveraging Distributed Shared Resources and core-to-core Communication on many-core Platforms

Safe Virtual Interrupts Leveraging Distributed Shared Resour...

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19th ieee Pacific Rim international Symposium on Dependable computing (PRDC)

作者： Motruk, Boris Diemer, Jonas Axer, Philip Buchty, Rainer Berekovic, Mladen Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Braunschweig Germany Tech Univ Carolo Wilhelmina Braunschweig Inst Comp & Network Engn Braunschweig Germany

ISBN: (纸本)9780769551302

Modern many-core platforms offer sufficient redundant resources for increasing availability and fault-tolerance of multiple applications, also of different criticality (mixed-criticality). A suitable platform must allow remapping applications and replacing peripherals dynamically. Mapping to distributed resources but also communication among resources ideally is transparent and flexible to allow changes at run time. Communication additionally has to be predictable, especially for safety-critical applications, and can be efficiently implemented by the use of interrupt requests. This paper presents a scalable interrupt translation mechanism supporting flexible and transparent communication among resources. Our contribution is of particular benefit for legacy applications but also eases development of new applications. A fast and predictable monitoring and control mechanism enforces specified behavior of applications and peripherals communicating with critical applications at run time. This significantly reduces integration effort for mixed-critical applications on a shared platform, and thus makes many-core platforms more attractive for embedded and safety-critical systems.

关键词： communication embedded systems dependability fault-tolerance interrupts isolation many-core mixed-criticality monitoring multi-core real-time reliability safety virtualization

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Erlang as a Language for Cloud computing and its Integration with many-core Coprocessor

Erlang as a Language for Cloud Computing and its Integration...

引用

international Conference on Cloud and Service computing (CSC)

作者： Zheng, Siyao Long, Xiang Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China

ISBN: (纸本)9780769551579

Erlang programming language is developed for programming concurrent, distributed and fault-tolerant systems. The native support for concurrency makes Erlang an efficient language for multi-core and even many-core programming. The support for large number of light-weight processes in distributed computing environment makes Erlang a good choice for cloud computing. Building more cores on a single chip is a trend in processor design. Intel Xeon Phi coprocessor, which is equipped with at least 60 cores, is the first commercial many-core product released by Intel. Xeon Phi coprocessor is encapsulated in a PCIe card and communicates with host operating system through a specialized interface library called SCIF. This paper introduces the architecture of Xeon Phi coprocessor and analyses the internals of SCIF programming interface first. Then this paper proposes a solution that integrates the computing power of multi-core host machine and Xeon Phi many-core coprocessor transparently. The solutions implements a high efficient SCIF-based Erlang distribution carrier as a plugin into Erlang virtual machine, and extends Erlang VM itself to support remote port access in order to support process location policy defined in this solution. In the end, this paper shows a practical use case of the proposed solution in cloud service environment: improve web server capacity without modifying user program. The performance evaluation shows that the capacity of a web server is improved at least 4 times.

关键词： Erlang Cloud computing Intel Xeon Phi many-core Coprocessor computing Integration

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Evaluating the Performance and Energy Efficiency of N-Body Codes on multi-core CPUs and GPUs

Evaluating the Performance and Energy Efficiency of <i>N</i>...

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32nd ieee international Performance, computing, and Communications Conference (IPCCC)

作者： Zecena, Ivan Burtscher, Martin Jin, Tongdan Zong, Ziliang Texas State Univ Dept Comp Sci Round Rock TX 78665 USA Texas State Univ Ing Sch Engn San Marcos TX 78666 USA

ISBN: (纸本)9781479932146;9781479932139

N-body simulations are computation-intensive applications that calculate the motion of a large number of bodies under pair-wise forces. Although different versions of n-body codes have been widely used in many scientific fields, the performance and energy efficiency of various n-body codes have not been comprehensively studied, especially when they are running on newly released multi-core CPUs and GPUs (e.g., Tesla K20). In this paper, we evaluate the performance and energy efficiency of five parallel n-body implementations on two different multi-core CPU systems and on two different types of GPUs. Our experimental results show that up to 71% of the energy can be saved by using all cores of a Xeon E5620 CPU instead of only one. We find hyper-threading to be able to further reduce the energy usage and runtime, but not by as much as adding more cores does. Finally, our experiments illustrate that GPU-based acceleration using a Tesla K20c can boost the performance and energy efficiency by orders of magnitude.

关键词： performance energy efficiency multi-core CPUs GPUs hyper-threading n-body simulation

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Proposing a new task model towards many-core architecture 13

Proposing a new task model towards many-core architecture

引用

1st international workshop on many-core Embedded systems, MES 2013, in Conjunction with the 40th Annual ieee/ACM international Symposium on Computer Architecture, ISCA 2013

作者： Shimada, Akio Gero, Balazs Hori, Atsushi Ishikawa, Yutaka RIKEN Advanced Institute for Computational Science Japan University of Tokyo Japan

ISBN: (纸本)9781450320634

many-core processors are gathering attention in the areas of embedded systems due to their power-performance ra- tios. To utilize cores of a many-core processor in parallel, programmers build multi-task applications that use the task models provided by operating systems. However, the con- ventional task models cause some scalability problems when multi-task applications are executed on many-core proces- sors. In this paper, a new task model named Partitioned Virtual Address Space (PVAS), which solves the problems, is proposed. PVAS enhances inter-task communications of multi-task applications and averts serialization of concurrent virtual memory operations. Preliminary evaluations by us- ing micro benchmarks showed that PVAS has the potential to promote the performance of multi-task applications that run on many-core processors. Copyright 2013 ACM.

关键词： Embedded systems

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1st international workshop on many-core Embedded systems, MES 2013 - In Conjunction with the 40th Annual ieee/ACM international Symposium on Computer Architecture, ISCA 2013

1st International Workshop on Many-Core Embedded Systems, ME...

引用

1st international workshop on many-core Embedded systems, MES 2013, in Conjunction with the 40th Annual ieee/ACM international Symposium on Computer Architecture, ISCA 2013

ISBN: (纸本)9781450320634

The proceedings contain 11 papers. The topics discussed include: improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP;co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs;many-core acceleration for model predictive control systems;a code generation method for system-level synthesis;directory based cache coherence verification logic in CMPs cache system;design of high-throughput inter-PE communication with application-level flow control protocol for many-core architecture;proposing a new task model towards many-core architecture;performance analysis of multi-threaded multi-core CPUs;extending dataflow programs for guaranteed throughput;transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs;and autopilot: message passing parallel programming for a cache incoherent embedded manycore processor.

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Achieving high-throughput State Machine Replication in multi-core systems

Achieving high-throughput State Machine Replication in multi...

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33rd ieee international Conference on Distributed computing systems (ICDCS)

作者： Santos, Nuno Schiper, Andre Ecole Polytech Fed Lausanne CH-1015 Lausanne Switzerland

ISBN: (纸本)9780769550008

The traditional architecture used by implementations of Replicated State Machines (RSM) does not fully exploit modern multi-core CPUs. This is increasingly the limiting factor in their performance, because network speeds are increasing much faster than the single-thread performance of CPUs. Thus, when deployed on Gigabit-class networks and exposed to a workload of small to medium size client requests, RSMs are often CPU-bound, as they are only able to leverage a few cores, even though many more may be available. In this work, we revisit the traditional architecture of a RSM implementation, showing how it can be parallelized so that its performance scales with the number of cores in the nodes. We do so by applying several good practices of concurrent programming to the specific case of state machine replication, including staged execution, workload partitioning, actors, and non-blocking data structures. We describe and test a Java prototype of our architecture, based on the Paxos protocol. With a workload consisting of small requests, we achieve a six times improvement in throughput using eight cores. More generally, in all our experiments we have consistently reached the limits of the network subsystem by using up to 12 cores, and do not observe any degradation when using up to 24 cores. Furthermore, the profiling results of our implementation show that even at peak throughput contention between threads is minimal, suggesting that the throughput would continue scaling given a faster network.

关键词： Paxos multicore scalability

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