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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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Performance analysis of current parallel programming models for many-core systems

Performance analysis of current parallel programming models ...

引用

8th international Conference on Computer Science and Education, ICCSE 2013

作者： Cao, Yangjie Wu, Baodong Tao, Yongcai Shi, Lei School of Software Technology Zhengzhou University Zhengzhou China School of Information Engineering Zhengzhou University Zhengzhou China

ISBN: (纸本)9781467344623

Recent developments in microprocessor design show a clear rend towards multi-core and many-core architectures. Nowadays, processors consisting of dozens of general-purpose cores are already available in the market, and with the rapid development of semiconductor technology and increasing computing demand, it will be very common to have a processor consisting of hundreds or even thousands of cores in the near future. This kind of processors is commonly referred as many-core processors. In the many-core processor era, however, exploiting all the advantages offered by these processors will not be trivial. In this paper, we focus on studying and analyzing several typical parallel programming models for many-core systems, and summarize the common performance-optimized problems faced by current parallel programming models. © 2013 ieee.

关键词： Parallel processing systems

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Accounting for secondary uncertainty: Efficient computation of portfolio risk measures on multi and many core architectures

Accounting for secondary uncertainty: Efficient computation ...

引用

6th workshop on High Performance Computational Finance, WHPCF 2013 - Held in Conjunction with the international Conference for High Performance computing, Networking, Storage and Analysis, SC 2013

作者： Varghese, Blesson Rau-Chaplin, Andrew Faculty of Computer Science Dalhousie University Halifax NS Canada

ISBN: (纸本)9781450325073

Aggregate Risk Analysis is a computationally intensive and a data intensive problem, thereby making the application of high-performance computing techniques interesting. In this paper, the design and implementation of a parallel Aggregate Risk Analysis algorithm on multi-core CPU and many-core GPU platforms are explored. The efficient computation of key risk measures, including Probable Maximum Loss (PML) and the Tail Value-at-Risk (TVaR) in the presence of both primary and secondary uncertainty for a portfolio of property catastrophe insurance treaties is considered. Primary Uncertainty is the the uncertainty associated with whether a catastrophe event occurs or not in a simulated year, while Secondary Uncertainty is the uncertainty in the amount of loss when the event occurs. A number of statistical algorithms are investigated for computing secondary uncertainty. Numerous challenges such as loading large data onto hardware with limited memory and organising it are addressed. The results obtained from experimental studies are encouraging. Consider for example, an aggregate risk analysis involving 800,000 trials, with 1,000 catastrophic events per trial, a million locations, and a complex contract structure taking into account secondary uncertainty. The analysis can be performed in just 41 seconds on a GPU, that is 24x faster than the sequential counterpart on a fast multi-core CPU. The results indicate that GPUs can be used to efficiently accelerate aggregate risk analysis even in the presence of secondary uncertainty. © 2013 ACM.

关键词： Risk management

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Towards High-Performance and Cost-Effective Distributed Storage systems with Information Dispersal Algorithms

Towards High-Performance and Cost-Effective Distributed Stor...

引用

15th ieee international Conference on Cluster computing (CLUSTER)

作者： Zhao, Dongfang Burlingame, Kent Debains, corentin Alvarez-Tabio, Pedro Raicu, Ioan IIT Chicago IL 60616 USA

ISBN: (纸本)9781479908981

Reliability is one of the most fundamental challenges for high performance computing (HPC) and cloud computing. Data replication is the de facto mechanism to achieve high reliability, even though it has been criticized for its high cost and low efficiency. Recent research showed promising results by switching the traditional data replication to a software-based RAID. In order to systematically study the effectiveness of this new method, we built two storage systems from the ground up: a POSIX-compliant distributed file system (FusionFS) and a distributed key-value store (IStore), both supporting information dispersal algorithms (IDA) for data redundancy. FusionFS is crafted to have excellent throughput and scalability for HPC, whereas IStore is architected mainly as a light-weight key-value storage in cloud computing. We evaluated both systems with a large number of parameter combinations. Results show that, for both HPC and cloud computing communities, IDA-based methods with current commodity hardware could outperform data replication in some cases, and would completely surpass data replication with the growing computational capacity through multi/many-core processors (e.g. Intel Xeon Phi, NVIDIA GPU).

关键词： cloud computing multiprocessing systems parallel processing redundancy storage management

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many-core acceleration for model predictive control systems 13

Many-core acceleration for model predictive control systems

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1st international workshop on many-core Embedded systems, MES 2013, in Conjunction with the 40th Annual ieee/ACM international Symposium on Computer Architecture, ISCA 2013

作者： Kawakami, Satoshi Iwanaga, Akihito Inoue, Koji School of Information Science and Electrical Engineering Kyushu University Japan School of Integrated Frontier Sciences Kyushu University Japan Faculty of Information Science and Electrical Engineering Kyushu University Japan

ISBN: (纸本)9781450320634

This paper proposes a novel many-core execution strategy for real-time model predictive controls. The key idea is to exploit predicted input values, which are produced by the model predictive control itself, to speculatively solve an op- timal control problem. It is well known that control appli- cations are not suitable for multi- or many-core processors, because feedback-loop systems inherently stand on sequen- tial operations. Since the proposed scheme does not rely on conventional thread-/data-level parallelism, it can be easily applied to such control systems. An analytical evaluation using a real application demonstrates the potential of per- formance improvement achieved by the proposed speculative executions. Copyright 2013 ACM.

关键词： Model predictive control

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Applications of many-core Technologies to On-line Event Reconstruction in High Energy Physics Experiments

Applications of Many-Core Technologies to On-line Event Reco...

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60th ieee Nuclear Science Symposium (NSS) / Medical Imaging Conference (MIC) / 20th international workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors

作者： Gianelle, A. Amerio, S. Bastieri, D. Corvo, M. Ketchum, W. Liu, T. Lonardo, A. Lucchesi, D. Poprocki, S. Rivera, R. Tosoratto, L. Vicini, P. Wittich, P. INFN Padova Padua Italy

ISBN: (纸本)9781479905348

Interest in many-core architectures applied to real time selections is growing in High Energy Physics (HEP) experiments. In this paper we describe performance measurements of many-core devices when applied to a typical HEP online task: the selection of events based on the trajectories of charged particles. We use as benchmark a scaled-up version of the algorithm used at CDF experiment at Tevatron for online track reconstruction - the SVT algorithm - as a realistic test-case for low-latency trigger systems using new computing architectures for LHC experiment. We examine the complexity/performance trade-off in porting existing serial algorithms to many-core devices. We measure performance of different architectures (Intel Xeon Phi and AMD GPUs, in addition to NVidia GPUs) and different software environments (OpenCL, in addition to NVidia CUDA). Measurements of both data processing and data transfer latency are shown, considering different I/O strategies to/from the many-core devices.

关键词： Data transfer

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Proc. of UltraVis 2013: 8th Int. workshop on Ultrascale Visualization - Held in Conjunction with SC 2013: The Int. Conference for High Performance computing, Networking, Storage and Analysis

Proc. of UltraVis 2013: 8th Int. Workshop on Ultrascale Visu...

引用

8th international workshop on Ultrascale Visualization, UltraVis 2013 - Held in Conjunction with the international Conference for High Performance computing, Networking, Storage and Analysis, SC 2013

ISBN: (纸本)9781450325004

The proceedings contain 6 papers. The topics discussed include: an analytical framework for particle and volume data of large?scale combustion simulations;a classification of scientific visualization algorithms for massive threading;on-demand unstructured mesh translation for reducing memory pressure during in situ analysis;a model for optimizing file access patterns using spatio-temporal parallelism;ray tracing and volume rendering large molecular data on multi-core and many-core architectures;and GPU-accelerated molecular visualization on petascale supercomputing platforms.

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Performance analysis of multi-threaded multi-core CPUs 13

Performance analysis of multi-threaded multi-core CPUs

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1st international workshop on many-core Embedded systems, MES 2013, in Conjunction with the 40th Annual ieee/ACM international Symposium on Computer Architecture, ISCA 2013

作者： Saravanan, Vijayalakshmi Kaushik, S. Sai, Krishna P. Kothari, D.P. VIT University India SASTRA University India IIT Guwahati India IIT Delhi India

ISBN: (纸本)9781450320634

Processors are constantly changing and becoming more ad- vanced. They incorporate new concepts and ideas into the architecture with each evolution. One such concept is multi- threading. It aims at increasing the processors performance by reducing its idle time. It is the ability of the processor to execute multiple threads simultaneously on different cores present inside. multi-threading concepts have also been incorporated in embedded systems which employ either a single-core or multi-core architecture. The aim of this study is to evaluate how effectively multi-threading improves pro- cessor utilization on multiple cores by taking both single and dual core processors and evaluating the performance of each by comparing the number of instructions executed per second. The results of this study give an edge to multi- threading in a single-core processor when compared to a dual-core processor when performance aspects are consid- ered. Our analysis helps us to design the processor architec- ture in such a way that we utilize both the concepts of multi- threading and multi-core architecture to achieve maximum performance. The results of Simultaneous multi-threading (SMT) performance improvement is encouraging when com- pared with dual-core processors. Copyright 2013 ACM.

关键词： Program processors

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GSNoC - The comprehensive design platform for 3-dimensional Networks-on-Chip based many core embedded systems

GSNoC - The comprehensive design platform for 3-dimensional ...

引用

2013 11th international Conference on High Performance computing and Simulation, HPCS 2013

作者： Ying, Haoyuan Hollstein, Thomas Hofmann, Klaus Integrated Electronic Systems Lab TU Darmstadt Germany Tallinn University of Technology Estonia

ISBN: (纸本)9781479908363

As the embedded system design focus moving from computation-centric to communication-centric, Networks-on-Chip (NoCs) have been selected as the next generation interconnect components for multi/many core systems due to the scalability and high bandwidth. However, the NoCs design has reached the bottleneck in terms of power consumption, data communication latency and chip area nowadays. 3D chip technologies have been brought into the NoCs design field to reduce the communication cost but increase the performance. A comprehensive design platform - Generic Scalable Networks-on-Chip (GSNoC) will be demonstrated in this paper, which can handle the 3D NoCs design at different design levels (application, architecture and circuit). Application generator, NoCs design framework, comprehensive cycle accurate system simulator and an user-friendly Graphic User Interface (GUI) have been developed in the platform. The entire platform is programmed in C++ and the hardware simulation part is programmed in SystemC. © 2013 ieee.

关键词： Network-on-chip

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Run-time adaption for highly-complex multi-core systems

Run-time adaption for highly-complex multi-core systems

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11th ACM/ieee international Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013

作者： Henkel, Jörg Narayanan, Vijaykrishnan Parameswaran, Sri Teich, Jürgen Karlsruhe Institute of Technology Germany Pennsylvania State University United States University of New South Wales Australia University of Erlangen-Nuremberg Germany

ISBN: (纸本)9781479914173

As embedded on-chip systems grow more and more complex and are about to be deployed in automotive and other demanding application areas (beyond the main-stream of consumer electronics), run-time adaptation is a prime design consideration for many reasons: i) reliability is a major concern when migrating to technology nodes of 32nm and beyond, ii) efficiency i.e. computational power per Watt etc. is a challenge as computing models do not keep up with hardware-provided computing capabilities, iii) power densities increase rapidly as Dennard Scaling fails resulting in what is dubbed "Dark Silicon", iv) highly complex embedded applications are hard to predict etc. All these scenarios (and further not listed here) make proactive and sophisticated run-time adaption techniques a prime design consideration for generations of multi-core architectures to come. The intend of this paper is to present problems and solutions of top research initiatives from diverse angels with the common denominator of the dire need for run-time adaption: The first part tackles the thermal problem i.e. high power densities and the related short and long-term effects it has on the reliability and it presents scalable techniques to cope the related problems. The second section demonstrates the potential of steep slope devices on thread scheduling of multi-cores. The third approach presents embedded pipelined architectures running complex multi-media applications whereas the fourth section introduces the paradigm of invasive computing i.e. a novel computing approach promising high efficiency through a highly-adaptive hardware/software architecture. In summary, the paper presents snapshots on four highlyadaptive solutions and platforms from different angles for challenges of complex future multi-core systems. © 2013 ieee.

关键词： Embedded systems

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TOWARDS A many-core ARCHITECTURE FOR HPC

TOWARDS A MANY-CORE ARCHITECTURE FOR HPC

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23rd international Conference on Field Programmable Logic and Applications (FPL)

作者： Wyngaard, Janet Inggs, Michael Collins, John Farrimond, Brian Univ Cape Town Dept Elect Engn ZA-7700 Rondebosch South Africa SimCon Ltd London England

ISBN: (纸本)9781479900046

many-core architectures are a current avenue of research, seeking alternative higher efficiency computing, and HPC is one domain which may benefit most from such a model. While at an initial prototyping stage we present here the design of a MIMD many-core processor, Fynbos and, considering the problems of programmability, an autoparallelising Fortran pipeline. Our initial operating results demonstrate functionality, and the effectiveness of the compiler as the system efficiency increases with problem size in a test case multi-body simulation. The test case also serves to highlight system weaknesses. We conclude that the demonstration offers sufficient motivation for the future work discussed.

关键词： FORTRAN multiprocessing systems parallel processing pipeline processing program compilers

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