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ieee 27th international Parallel and Distributed Processing Symposium (IPDPS)

作者： Whelihan, David Hughes, Jeffrey J. Sawyer, Scott M. Robinson, Eric Wolf, Michael Mohindra, Sanjeev Mullen, Julie Klein, Anna Beard, Michelle Bliss, Nadya T. Chan, Johnnie Hendry, Robert Bergman, Keren Carloni, Luca P. MIT Lincoln Lab 244 Wood St Lexington MA 02173 USA Columbia Univ Dept Elect Engn New York NY 10027 USA Columbia Univ Dept Comp Sci New York NY 10027 USA

ISBN: (纸本)9780769549712

Communication in multi-and many-core processors has long been a bottleneck to performance due to the high cost of long-distance electrical transmission. This difficulty has been partially remedied by architectural constructs such as caches and novel interconnect topologies, albeit at a steep cost in terms of complexity. Unfortunately, even these measures are rendered ineffective by certain kinds of communication, most notably scatter and gather operations that exhibit highly non-local data access patterns. Much work has gone into examining how the increased bandwidth density afforded by chip-scale silicon photonic interconnect technologies affects computing, but photonics have additional properties that can be leveraged to greatly accelerate performance and energy efficiency under such difficult loads. This paper describes a novel synchronized global photonic bus and system architecture called P-sync that uses photonics' distance independence to greatly improve performance on many important applications previously limited by electronic interconnect. The architecture is evaluated in the context of a non-local yet common application: the distributed Fast Fourier Transform. We show that it is possible to achieve high efficiency by tightly balancing computation and communication latency in P-sync and achieve upwards of a 6x performance increase on gather patterns, even when bandwidth is equalized.

关键词： computer architecture fast Fourier transforms multiprocessing systems multiprocessor interconnection networks network topology optical computing optical interconnections power aware computing synchronisation

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The demand for consistent web-based workflow editors 8

The demand for consistent web-based workflow editors

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8th workshop on Workflows in Support of Large-Scale Science, WORKS 2013

作者： Gesing, Sandra Atkinson, Malcolm Klampanos, Iraklis Galea, Michelle Berthold, Michael R. Barbera, Roberto Scardaci, Diego Terstyanszky, Gabor Kiss, Tamas Kacsuk, Peter University of Notre Dame Ctr for Research Computing University of Edinburgh Informatics Forum 111 Information Technology Center Notre DameIN46556 United States University of Edinburgh Informatics Forum EdinburghEH8 9AB United Kingdom Universität Konstanz FB Informatik and Informationswissenschaft Box 712 Konstanz78457 Germany Italian National Institute of Nuclear Physics Catania95123 Italy University of Westminster 115 New Cavendish Street LondonW1W 6UW United Kingdom Laboratory of Parallel and Distributed Systems MTA SZTAKI Kende Street 13-17 Budapest1111 Hungary

ISBN: (纸本)9781450325028

This paper identifies the high value to researchers in many disciplines of having web-based graphical editors for scientific workflows and draws attention to two technological transitions: good quality editors can now run in a browser and workflow enactment systems are emerging that manage multiple workflow languages and support multi-lingual workflows. We contend that this provides a unique opportunity to introduce multi-lingual graphical workflow editors which in turn would yield substantial benefits: workflow users would find it easier to share and combine methods encoded in multiple workflow languages, the common framework would stimulate conceptual convergence and increased workflow component sharing, and the many workflow communities could share a substantial part of the effort of delivering good quality graphical workflow editors in browsers. The paper examines whether such a common framework is feasible and presents an initial design for a web-based editor, tested with a preliminary prototype. It is not a fait accompli but rather an urgent rallying cry to explore collaboratively a generic web-based framework before investing in many divergent individual implementations.

关键词： Interoperability

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ASCOS: an Asymmetric Network Structure COntext Similarity Measure

ASCOS: an Asymmetric Network Structure COntext Similarity Me...

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ieee/ACM international Conference on Advances in Social Networks Analysis and Mining (ASONAM)

作者： Chen, Hung-Hsuan Giles, C. Lee Penn State Univ Comp Sci & Engn University Pk PA 16802 USA Penn State Univ Informat Sci & Technol University Pk PA 16802 USA

ISBN: (纸本)9781450322409

Discovering similar objects in a social network has many interesting issues. Here, we present ASCOS, an Asymmetric Structure COntext Similarity measure that captures the similarity scores among any pairs of nodes in a network. The definition of ASCOS is similar to that of the well-known SimRank since both define score values recursively. However, we show that ASCOS outputs a more complete similarity score than SimRank because SimRank (and several of its variations, such as P-Rank and SimFusion) on average ignores half paths between nodes during calculation. To make ASCOS tractable in both computation time and memory usage, we propose two variations of ASCOS: a low rank approximation based approach and an iterative solver Gauss-Seidel for linear equations. When the target network is sparse, the run time and the required computing space of these variations are smaller than computing SimRank and ASCOS directly. In addition, the iterative solver divides the original network into several independent sub-systems so that a multi-core server or a distributed computing environment, such as MapReduce, can efficiently solve the problem. We compare the performance of ASCOS with other global structure based similarity measures, including SimRank, Katz, and LHN. The experimental results based on user evaluation suggest that ASCOS gives better results than other measures. In addition, the asymmetric property has the potential to identify the hierarchical structure of a network. Finally, variations of ASCOS (including one distributed variation) can also reduce computation both in space and time.

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Proceedings of the 2013 ieee international Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology systems, DFTS 2013

Proceedings of the 2013 IEEE International Symposium on Defe...

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2013 26th ieee international Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology systems, DFTS 2013

ISBN: (纸本)9781479915835

The proceedings contain 50 papers. The topics discussed include: classes of difficult-to-diagnose transition fault clusters;a low power architecture for online detection of execution errors in SMT processors;a data mining approach to incremental adaptive functional diagnosis;CFEDR: control-flow error detection and recovery using encoded signatures monitoring;sat-based code synthesis for fault-secure circuits;DaemonGuard: O/S-assisted selective software-based self-testing for multi-core systems;run-time mapping for reliable many-cores based on energy/performance trade-offs;a cross-layer fault-tolerant design method for high manufacturing yield and system reliability;analysing degradation effects in charge-redistribution SAR ADCs;fault injection framework for embedded memories;a fast TCAD-based methodology for variation analysis of emerging nano-devices;approximate simulation of circuits with probabilistic behavior;and shielding heterogeneous MPSoCs from untrustworthy 3pips through security-driven task scheduling.

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Grid Authorization Graph

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FUTURE GENERATION COMPUTER systems-THE international JOURNAL OF ESCIENCE 2013年第8期29卷 1909-1918页

作者： Kaiiali, Mustafa Wankar, Rajeev Rao, C. R. Agarwal, Arun Buyya, Rajkumar Univ Hyderabad Dept Comp & Informat Sci Hyderabad 500134 Andhra Pradesh India Univ Melbourne Dept Comp Sci & Software Engn Cloud Comp & Distributed Syst CLOUDS Lab Melbourne Vic 3010 Australia Mevlona Univ Dept Comp Engn Konya Turkey

The heterogeneous and dynamic nature of a grid environment demands a scalable authorization system. This brings out the need for a fast fine-grained access control mechanism for authorizing grid resources. Existing grid authorization systems adopt inefficient mechanisms for storing resources' security policies. This leads to a large number of repetitions in checking security rules. One of the efficient mechanisms that handle these repetitions is the Hierarchical Clustering Mechanism (HCM). HCM reduces the redundancy in checking security rules compared to the Brute Force Approach (BFA) as well as the Primitive Clustering Mechanism (PCM). Further enhancement is done to HCM to increase the scalability of the authorization process. However, HCM is not totally free of repetitions and cannot easily describe the OR-based security policies. A novel Grid Authorization Graph (GAG) is proposed to overcome HCM limitations. GAG introduces special types of edges named "Correspondence Edge"/"Discrepancy Edge" which can be used to entirely eliminate the redundancy and handle the cases where a set of security rules are mutually exclusive. Comparative studies are made in a simulated environment using the Grid Authorization Simulator (GAS) developed by the authors. It simulates the authorization process of the existing mechanisms like BFA, PCM, HCM and the proposed novel GAG. It also enables a comparative analysis to be done between these approaches. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Grid computing Grid authorization Access control Hierarchical Clustering Mechanism Grid Authorization Graph

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AutoPilot: Message passing parallel programming for a cache incoherent embedded manycore processor 13

AutoPilot: Message passing parallel programming for a cache ...

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1st international workshop on many-core Embedded systems, MES 2013, in Conjunction with the 40th Annual ieee/ACM international Symposium on Computer Architecture, ISCA 2013

作者： Kelly, Ben Gardner, William B. Kyo, Shorin Google Canada 151 Charles St. W. Kitchener ON N2G 1H6 Canada School of Computer Science University of Guelph Guelph ON N1G 2W1 Canada Renesas Electronics 1763 Shimonumabe Makahara-ku Kawasaki Kanagawa Japan

ISBN: (纸本)9781450320634

The Renesas Electronics IMAPCAR2 embedded realtime image processor combines a single core with a 128-way SIMD array. At runtime, sections of the SIMD array can be reconfigured as additional CPU cores, interconnected via a message ring. Effective use is made difficult by the low-level message passing API and lack of cache coherency between processors. The AutoPilot library addresses this by providing a high-level message-oriented parallel programming model mirroring that of Pilot, itself a wrapper around the Message Passing Interface (MPI) for cluster computing. AutoPilot shows that Pilot's processes-and-channels architecture is a viable choice for parallel programming on cache-incoherent multicore and manycore architectures. It provides a simpler API for programmers, with built-in safety checks that eliminate some common sources of errors. Since the IMAPCAR2 is targeted chiefly at automotive applications, open source AutoPilot has a large degree of MISRA-C compliance. Copyright 2013 ACM.

关键词： Cluster computing

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Performance evaluation of NAS parallel benchmarks on intel-R Xeon PhiTM

Performance evaluation of NAS parallel benchmarks on intel-R...

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42nd Annual international Conference on Parallel Processing, ICPP 2013

作者： Ramachandran, Arunmoezhi Vienne, Jerome Van Der Wijngaart, Rob Koesterke, Lars Sharapov, Ilya University of Texas at Dallas United States Texas Advanced Computing Center University of Texas at Austin United States Intel Corporation Santa Clara CA United States

ISBN: (纸本)9780769551173

NAS parallel benchmarks (NPB) are a set of applications commonly used to evaluate parallel systems. We use the NPB-OpenMP version to examine the performance of the Intel's new Xeon Phi co-processor and focus specially on the many-core aspect of the Xeon Phi architecture. A first analysis studies the scalability up to 244 threads on 61 cores, the impact of affinity settings on scaling and compare performance characteristics of Xeon Phi and traditional Xeon CPUs. The application of several well-established optimization techniques allows us to identify common bottlenecks that can specifically impede performance on the Xeon Phi but are not as severe on multi-core CPUs. We also find that many of the OpenMP-parallel loops are too short (in terms of the number of loop iterations) for a balanced execution by 244 threads. New, or redesigned benchmarks will be needed to accommodate the greatly increased number of cores and threads. At the end, we summarize our findings in a set recommendations for performance optimization for Xeon Phi. © 2013 ieee.

关键词： Parallel programming

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PROTON: An Automatic Place-and-Route Tool for Optical Networks-on-Chip

PROTON: An Automatic Place-and-Route Tool for Optical Networ...

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32nd ieee/ACM international Conference on Computer-Aided Design (ICCAD)

作者： Boos, Anja Ramini, Luca Schlichtmann, Ulf Bertozzi, Davide Tech Univ Munich Inst Elect Design Automat D-80290 Munich Germany Univ Ferrara Dept Engn I-44121 Ferrara Italy

ISBN: (纸本)9781479910717

Optical Networks-on-Chip (ONoCs) are considered a promising way of improving power and bandwidth limitations in next generation multi-and many-core integrated systems. Today, most related research acknowledges the key role of the physical layer in assessing ONoC topologies (e. g., insertion loss), but overlooks the placement and routing stage in the design process, hence applying physical design considerations to topology logic schemes. Such a mismatch is fundamentally due to the lack of mature CAD tools for placement and routing of optical NoCs. The objective of this work is to bridge this gap: We propose PROTON, a fast tool for automatic placement and routing of ONoC topologies, which can support designers in quantifying the degradation of design quality metrics when moving from topology logic schemes to their physical implementation. This gap is especially relevant for Wavelength-Routed ONoCs (WRONoCs), where logic schemes typically make unrealistic assumptions about the placement of initiators and targets. For this reason, we put PROTON to work with the most promising WRONoC topologies and explore their physical design space given the placement and routing constraints of a 3D stacked system. We also compare automatically generated layouts with handcrafted ones reported in the literature for the same topologies and target system, and prove an insertion loss improvement by up to 150x. With PROTON the exploration of the physical design space of ONoC topologies is possible as well as their scalability analysis considering the layout.

关键词： CAD integrated optics network routing network-on-chip optical engineering computing optical logic three-dimensional integrated circuits

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Hardware models for automated partitioning and mapping in multi-core systems

Hardware models for automated partitioning and mapping in mu...

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ieee international workshop on Intelligent Data Acquisition and Advanced computing systems: Technology and Applications

作者： Lukas Krawczyk Erik Kamsties University of Applied Sciences Fachhochschule Dortmund Germany

multi-core CPUs offer several major benefits in mobile and embedded systems. For instance, they provide better energy efficiency and more computing power at the same clock speed compared to single-core CPUs. These benefits do not come for free: A program has to be divided into tasks, which can be executed in parallel on different cores. Partitioning of software and mapping on cores are nontrivial activities that require detailed knowledge about the multi-core CPU, e.g., if shared memories are available, their size, and other properties. Such programmers' information about a CPU is typically stored in processor handbooks. If this information would be available in a machine readable model, we call it hardware model, the partitioning and mapping activities can be automated. In this paper, we propose a hardware model and illustrate it using an example of a Freescale multi-core CPU. We then discuss a small case study, which illustrates the use of the hardware model in partitioning, mapping, and code generation.

关键词： Hardware Embedded systems Data models System-on-chip Unified modeling language multicore processing

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Calibration of stochastic volatility models on a multi-core CPU cluster

Calibration of stochastic volatility models on a multi-core ...

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6th workshop on High Performance Computational Finance, WHPCF 2013 - Held in Conjunction with the international Conference for High Performance computing, Networking, Storage and Analysis, SC 2013

作者： Dixon, Matthew Zubair, Mohammad Department of Computer Science University of San Francisco San Francisco CA United States Department of Computer Science Old Dominion University Norfolk VA United States

ISBN: (纸本)9781450325073

Low-latency real-time option analytics feeds provide tick-by-tick implied volatilities and greeks based on exchange data. In order for the Black-Scholes implied volatility surface to exhibit the empirically observed skew or smile, a stochastic volatility model can be used to compute the option greeks. Because the European price under many stochastic volatility models only exists in semi-analytic form, frequent robust calibration of the model is computationally prohibitive. This paper explores three parallelization approaches for calibrating stochastic volatility models deployed on a multicore CPU cluster. The contribution of this paper is to provide benchmarks demonstrating hybrid shared and distributed memory parallelization techniques using Python packages for robust calibration of stochastic volatility models. The focus here will be on the Heston and Bates models, but the results in this paper generalize to any of the exponential Levy models incorporating stochastic volatility and jumps and whose characteristic function can be expressed in closed form. We evaluated the performance for our implementation on a cluster of 32 dual socket Dell PowerEdge R410 nodes providing 256 cores in total. Using distributed memory parallelization, we obtain a speedup of up to 139x against the sequential version of the calibration error function evaluation and reduce the overall time taken to calibrate a chain of 1024 SPX options by a factor of 37x. © 2013 ACM.

关键词： Calibration

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