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ieee workshop on High Performance Switching and Routing

作者： Haojun Luo Joseph Y. Hui Ayman G. Fayoumi Nuon Laboratories Arizona State University Tempe AZ USA Department of Information Systems King Abdulaziz University Jeddah Saudi Arabia

Data centers connect a larger number of servers requiring IO and switches with low power and delay. Virtualization of IO and network is crucial for these servers, which run virtual processes for computing, storage, and applications. We propose using the PCI Express (PCIe) protocol and a new PCIe switch fabric for IO and switch virtualization. The switch fabric has little data buffering, allowing up to 512 physical 10 Gb/s PCIe 2.0 lanes to be connected via a switch fabric on a chip. The switch is scalable with adapters running multiple adaptation protocols, such as Ethernet over PCIe, PCIe over Internet, or FibreChannel over Ethernet. Such adaptation protocols allow integration of IO often required for disjoint data center applications such as storage and networking. The novel switch fabric based on space-time carrier sensing facilitates high bandwidth, low power, and low delay multiprotocol switching. To achieve Terabit switching, both time (high transmission speed) and space (multi-stage interconnection network) technologies are required. In this paper, we present the design of an up to 256 lanes Close-network of multistage crossbar switch fabric for PCIe system. The switch core consists of 32 16x16 crossbar sub-switches. We also propose a new output contention resolution algorithm utilizing an out-of-band protocol of Request-To-Send (RTS), Clear-To-Send (CTS) before sending PCIe packets through the switch fabric. Preliminary power and delay estimates are provided.

关键词： Optical switches Ports (Computers) Silicon Routing Protocols

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Parallelized Benchmark-Driven Performance Evaluation of SMPs and Tiled multi-core Architectures for Embedded systems

Parallelized Benchmark-Driven Performance Evaluation of SMPs...

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31st ieee international Performance computing and Communications Conference (IPCCC)

作者： Munir, Arslan Gordon-Ross, Ann Ranka, Sanjay Rice Univ Dept Elect & Comp Engn POB 1892 Houston TX 77251 USA Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA Univ Florida Dept Comp & Informat Sci & Engn Gainesville FL 32611 USA

ISBN: (纸本)9781467348836;9781467348812

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, there exists a plethora of multi-core architectures and the suitability of these multi-core architectures for different embedded domains (e. g., distributed, real-time, reliability-constrained) requires investigation. Despite the diversity of embedded domains, one of the critical applications in many embedded domains (especially distributed embedded domains) is information fusion. Furthermore, many other applications consist of various kernels, such as Gaussian elimination (used in network coding), that dominate the execution time. In this paper, we evaluate two embedded systems multi-core architectural paradigms: symmetric multiprocessors (SMPs) and tiled multi-core architectures (TMAs). We base our evaluation on a parallelized information fusion application and benchmarks that are used as building blocks in applications for SMPs and TMAs. We compare and analyze the performance of an Intel-based SMP and Tilera's TILEPro64 TMA based on our parallelized benchmarks for the following performance metrics: runtime, speedup, efficiency, cost, scalability, and performance per watt. Results reveal that TMAs are more suitable for applications requiring integer manipulation of data with little communication between the parallelized tasks (e. g., information fusion) whereas SMPs are more suitable for applications with floating point computations and a large amount of communication between processor cores.

关键词： multi-core embedded systems performance evaluation

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Concurrent FFT computing on multicore processors

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2012年第1期24卷 29-44页

作者： Barhen, J. Humble, T. Mitra, P. Imam, N. Schleck, B. Kotas, C. Traweek, M. Oak Ridge Natl Lab Comp Sci & Math Div CESAR Oak Ridge TN 37831 USA Univ Notre Dame Notre Dame IN 46556 USA Coherent Logix Inc Austin TX 78746 USA Off Naval Res Maritime Sensing Branch Arlington VA 22203 USA

The emergence of streaming multicore processors with multi-SIMD (single-instruction multiple-data) architectures and ultra-low power operation combined with real-time compute and I/O reconfigurability opens unprecedented opportunities for executing sophisticated signal processing algorithms faster and within a much lower energy budget. Here, we present an unconventional Fast Fourier Transform (FFT) implementation scheme for the IBM Cell, named transverse vectorization. It is shown to outperform (both in terms of timing and GFLOP throughput) the fastest FFT results reported to date for the Cell in the open literature. We also provide the first results for multi-FFT implementation and application on the novel, ultra-low power Coherent Logix HyperX processor. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： multicore processors FFT HyperX IBM cell transverse vectorization

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multi-GPU algorithm for k-nearest neighbor problem

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2012年第1期24卷 45-53页

作者： Kato, Kimikazu Hosino, Tikara Nihon Unisys Ltd Tokyo Japan

The recommendation system is a mechanism which automatically recommends items that are likely to be of interest to the user. In the recommendation system, customers' preferences are encoded into vectors, and finding the nearest vectors to each vector is an essential part. This vector-searching part of the problem is called a k-nearest neighbor problem. We give an effective algorithm to solve this problem on multiple graphics processor units (GPUs). Our algorithm consists of two parts: the N-body problem and the partial sort. For an algorithm of the N-body problem, we applied the idea of a known algorithm, although another trick is needed to overcome the problem of small-sized shared memory. For the partial sort, we give a novel GPU algorithm which is effective for small k. In our partial sort algorithm, a heap is accessed in parallel by threads with a low cost of synchronization. We show through an experiment that when the size of the problem is large, an implementation of the algorithm on two GPUs runs more than 330 times faster than a single core implementation on a latest CPU. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： GPGPU data mining

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dOpenCL: Towards a Uniform Programming Approach for Distributed Heterogeneous multi-/many-core systems

dOpenCL: Towards a Uniform Programming Approach for Distribu...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Kegel, Philipp Steuwer, Michel Gorlatch, Sergei Univ Munster Dept Math & Comp Sci Munster Germany

ISBN: (纸本)9780769546766

Modern computer systems are becoming increasingly heterogeneous by comprising multi-core CPUs, GPUs, and other accelerators. Current programming approaches for such systems usually require the application developer to use a combination of several programming models (e. g., MPI with OpenCL or CUDA) in order to exploit the full compute capability of a system. In this paper, we present dOpenCL (Distributed OpenCL) - a uniform approach to programming distributed heterogeneous systems with accelerators. dOpenCL extends the OpenCL standard, such that arbitrary computing devices installed on any node of a distributed system can be used together within a single application. dOpenCL allows moving data and program code to these devices in a transparent, portable manner. Since dOpenCL is designed as a fully-fledged implementation of the OpenCL API, it allows running existing OpenCL applications in a heterogeneous distributed environment without any modifications. We describe in detail the mechanisms that are required to implement OpenCL for distributed systems, including a device management mechanism for running multiple applications concurrently. Using three application studies, we compare the performance of dOpenCL with MPI+OpenCL and a standard OpenCL implementation.

关键词： OpenCL Heterogeneous systems Distributed systems GPU computing dOpenCL

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A RTRM proposal for multi/many-core platforms and reconfigurable applications

A RTRM proposal for multi/many-core platforms and reconfigur...

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7th international workshop on Reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Bellasi, Patrick Massari, Giuseppe Fornaciari, William DEI Politecn Milano Milan Italy

ISBN: (纸本)9781467325721

Emerging multi/many-core architectures, targeting both High Performance computing (HPC) and mobile devices, increase the interest for self-adaptive systems, where both applications and computational resources could smoothly adapt to the changing of the working conditions. In these scenarios, an efficient Run-Time Resource Manager (RTRM) framework can provide a valuable support to identify the optimal trade-off between the Quality-of-Service (QoS) requirements of the applications and the time varying resources availability. This paper introduces a new approach to the development of a system-wide RTRM featuring: a) a hierarchical and distributed control, b) the exploitation of design-time information, c) a rich multi-objective optimization strategy and d) a portable and modular design based on a set of tunable policies. The framework is already available as an Open Source project, targeting a NUMA architecture and a new generation multi/many-core research platform. First tests show benefits for the execution of parallel applications, the scalability of the proposed multi-objective resources partitioning strategy, and the sustainability of the overheads introduced by the framework.

关键词： multiobjective optimization

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Parallel Circuit Simulation on multi/many-core systems

Parallel Circuit Simulation on Multi/Many-core Systems

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Chen, Xiaoming Wang, Yu Yang, Huazhong Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9780769546766

SPICE is widely used for transistor-level circuit simulation. However, with the growing complexity of the VLSI at nano-scale, the traditional SPICE simulator has become inefficient to provide accurate verifications. This thesis tries to accelerate transistor-level simulation on multi/many-core systems, and we will solve 3 problems: 1) develop a parallel sparse LU factorization algorithm for circuit simulation;2) implement the matrix solver on GPU to further accelerate the solver;3) develop a circuit partitioning based parallel simulation approach on distributed machines to obtain better scalability. The experimental results show that the proposed parallel LU factorization algorithm effectively accelerates the matrix solver for circuit simulation on both CPU and GPU.

关键词： Parallel Circuit Simulation Parallel LU Factorization GPU Acceleration

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FPGA Implementation of Heterogeneous multicore Platform with SIMD/MIMD Custom Accelerators

FPGA Implementation of Heterogeneous Multicore Platform with...

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ieee international Symposium on Circuits and systems

作者： Waidyasooriya, Hasitha Muthumala Takei, Yasuhiro Hariyama, Masanori Kameyama, Michitaka Tohoku Univ Grad Sch Informat Sci Aoba Ku Sendai Miyagi 9808579 Japan

ISBN: (纸本)9781467302197

Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve power-efficient computing in various areas from low-power embedded processing to high-performance computing. Since the optimal architecture is different from application to application, it is important to explore suitable architectures for different applications. In this paper, we propose an FPGA-based heterogeneous multi-core platform with custom accelerators for power-efficient computing. Our platform allows to select the most suitable accelerator according to the requirements of an application. Moreover, we optimize the number of ALUs, memory and interconnection network of the selected accelerators to increase the performance and to reduce the power consumption. Experimental results with simple media processing applications show that the proposed platform with SIMD accelerators is 15 times power-efficient compared to the GPu.

关键词： Heterogeneous computing system-on-chip

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Cooperative multitasking for GPU-accelerated grid systems

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2012年第1期24卷 96-107页

作者： Ino, Fumihiko Ogita, Akihiro Oita, Kentaro Hagihara, Kenichi Osaka Univ Grad Sch Informat Sci & Technol Suita Osaka 5650871 Japan NEC SOFT Ltd Koto Ku Tokyo 1360082 Japan

This paper presents a cooperative multitasking method for concurrent execution of scientific and graphics applications on the graphics processing unit (GPU). Our method is designed to accelerate compute unified device architecture-based applications using idle GPU cycles in the office. To prevent significant slow-down of graphics applications, the method divides scientific tasks into smaller pieces, which are then sequentially executed at the appropriate intervals. The method also has flexibility in finding the best tradeoff point between scientific applications and graphics applications. Experimental results show that the proposed method is useful to control the frame rate of the graphics application and the throughput of the scientific application. For example, biological sequence alignment can be processed at approximately 30% of the dedicated throughput while achieving interactive rendering at 58 frames per second. We also show that matrix multiplication can be efficiently processed at 60% of the dedicated throughput during word processing and web browsing. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： multitasking GPU CUDA grid computing

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Optimizing Process-to-core Mappings for Application Level multi-dimensional MPI Communications

Optimizing Process-to-Core Mappings for Application Level Mu...

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ieee international Conference on Cluster computing

作者： Karlsson, Christer Davies, Teresa Chen, Zizhong Colorado Sch Mines Golden CO 80401 USA Univ Calif Riverside Riverside CA 92521 USA

ISBN: (纸本)9781467324229

multi-dimensional MPI communications, where MPI communications have to be performed in each dimension of a Cartesian communicator, have been frequently used in many of today's high performance computing applications. While individual MPI collective communications for regular communicators with a one-dimensional linear-ranking of processes have been extensively studied and optimized, little optimizations have been performed for multi-dimensional MPI collective communications on multi-dimensional Cartesian topology. In this paper, we optimize multi-dimensional MPI collective communications for SMP and multi-core systems at the application level. We show that the default Cartesian topology built by the state-of-the-art MPI implementations produce sub-optimal performance for multi-dimensional MPI collective communications. We design optimal process-to-core mapping schemes for Cartesian communicators to minimize the total inter-node communications. The proposed technique improves the performance by up to 80% over the default Cartesian topology built by Cray's MPI implementation MPT 3.1.02 on the world's current second fastest supercomputer Jaguar at Oak Ridge National Laboratory.

关键词： Message Passing Interface (MPI) multicore Process-to-core Mapping Collective Communication Cartesian Topology

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