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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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Exploring HPC Parallelism with Data-Driven multithreating

Exploring HPC Parallelism with Data-Driven Multithreating

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2nd international workshop on Data-Flow Execution Models (DFM) for Extreme Scale computing

作者： Christofi, Constantinos Michael, George Trancoso, Pedro Evripidou, Paraskevas Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9780769549545

The switch to multi-core systems has ended the reliance on the single processor for increase in performance and moved into Parallelism. However, the exponential growth in performance of the single processor in the 80's and 90's had overshadowed the drive for efficient Parallelism and relegate it into a niche research area, mostly for High Performance computing (HPC). Parallelism now is in the forefront and holds the burden for utilising the extra resources of Moore's law to maintain the exponential growth of the computing systems. In the drive to utilise parallel models of computation, Data-Flow models have recently been "re-visited" for exploiting parallelism in the multi and many core systems. Data-Driven multithreading (DDM) is one such model which is based on Dynamic Data-Flow principles, that can expose the maximum parallelism of an application. DDM schedules Threads based on Data availability driven by a producer consumer graph. DDM enforces single assignments semantics on the data passed from producer to consumer. In this paper we present a preliminary evaluation of whether DDM can be viable candidate for HPC. We study the scalability of a small subset of the LINPACK benchmark using the Data-Driven multithreading for a system with a 48 cores. We implement three test case operations: Matrix multiplication, LU and Cholesky decompositions and use them to test their scalability and performance. We use optimized linear algebra kernel operation for the basic operations performed in the threads. We compare our DDM implementations against PLASMA, a state-of-the-art linear algebra library for HPC computing, and show that applications using the DDM model can scale efficiently and observe a performance improvement of up to 2x.

关键词： matrix multiplication multi-threading

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ALWP: A Workload Partition Method for the Efficient Parallel Simulation of manycores

ALWP: A Workload Partition Method for the Efficient Parallel...

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Jiao, Shuai Wang, Da Ye, Xiaochun Xu, Weizhi Zhang, Hao Sun, Ninghui Chinese Acad Sci ICT Key Lab Comp Syst & Architecture Beijing 100190 Peoples R China

ISBN: (纸本)9780769547497

this paper addresses the workload partition strategies in simulating many-core architectures. The key observation behind this paper is: compared to multicore, manycore features with more non-uniform memory access and unpredictable network traffic;these features degrade simulation speed and accuracy of parallel discrete event simulators (PDES) in cases of static workload partition schemes. Based on the observation, an adaptive workload partition method is proposed: Adaptive Link-based Workload Partition (ALWP). The proposed method can deliver more speedup and accuracy than traditional static partition schemes. It achieves this ability by placing the partitioning border prior on less interactive links. Using a PDES simulator, we evaluate the performance of ALWP in simulating a 256-core general purpose many-core processor. Running SPLASH2 benchmark applications, the experimental results demonstrate that, compared to static scheme, ALWP can deliver speed improvement by 14%similar to 42% and reduce more timing errors (>50%) in relaxed cases.

关键词： Parallel Discret Event Simulation many-core multi-core Workload Partition

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ENERGY AND PERFORMANCE CHARACTERIZATION OF MOBILE HETEROGENEOUS computing

ENERGY AND PERFORMANCE CHARACTERIZATION OF MOBILE HETEROGENE...

引用

ieee workshop on Signal Processing systems (SiPS)

作者： Wang, Yi-Chu Cheng, Kwang-Ting (Tim) Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

ISBN: (纸本)9780769548562;9781467329866

A modern mobile application processor is a heterogeneous multi-core SoC which integrates CPU and application-specific accelerators such as GPU and DSP. It provides opportunity to accelerate other compute-intensive applications;yet mapping an algorithm to such a heterogeneous platform is not a straightforward task and has many design decisions to make. In this paper, we evaluate the performance and energy benefits of utilizing the integrated GPU and DSP cores to offload or share CPU's compute-intensive tasks. The evaluation is conducted on three representative mobile platforms, TI's OMAP3530, Qualcomn's Snapdragon S2, and Nvidia's Tegra2, using common computation tasks in mobile applications. We identify key factors that should be considered in energy-optimized mobile heterogeneous computing. Our evaluation results show that, by effectively utilizing all the computing cores concurrently, an average of 3.7X performance improvement can be achieved with the cost of 33% more power consumption, in comparison with the case of utilizing CPU only. This stands for 2.8X energy saving.

关键词： digital signal processing chips graphics processing units mobile computing multiprocessing systems performance evaluation power aware computing system-on-chip

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An OpenCL runtime library for embedded multi-core accelerator

An OpenCL runtime library for embedded multi-core accelerato...

引用

18th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2012

作者： Sakamoto, Ryuichi Sato, Mikiko Koizumi, Yusuke Amano, Hideharu Namiki, Mitaro Tokyo University of Agriculture and Technology Japan Keio University Japan

ISBN: (纸本)9781467330176

In recent years, improvements of energy efficiency and computational performance have become a major issue, because smartphones and tablets become popular. To implement high performance, multi-core accelerator consists of general purpose processors and accelerators are often used. But to use these multi-core accelerator efficiently, programmers have to consider synchronization and data transfer between accelerators, memory and I/O. Therefore frameworks such as OpenCL have been proposed for effective use of parallel computing resources of multi-core processors. OpenCL frameworks for GPGPU, Intel multi-core and many other kind of multi-core processors have been developed on Linux. However, in order to use those multi-core accelerators effectively, it is necessary to control accelerators with software environment aiming effective use of accelerators. Generally user mode application program calls OS to synchronize of accelerator's data transfer and termination of the its execution with overhead. In this paper, accelerators are controlled from collaborated OS and OpenCL library, instead of user mode application program. Our feature of these methods is that OS cooperates with library to reduce overhead of control accelerators. The proposed framework in this paper integrates the execution and data transfer control in an OpenCL library and an embedded OS. The OpenCL library creates task automaticity generated from the description of the user program. The OpenCL library gives scheduling information such as execution order about tasks to the scheduler of the embedded OS. The embedded OS's scheduler handles events of execution, termination and synchronization of data transfer via interrupts from accelerators. The scheduler determines to execute next task from the scheduling information passed by the OpenCL library. By the schemes to control accelerators are managed in OS, accelerators can be worked efficiently. The poster presentation shows the implemented OpenCL and OS framew

关键词： Energy efficiency

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Thermal-constrained energy-aware partitioning for heterogeneous multi-core multiprocessor real-time systems

Thermal-constrained energy-aware partitioning for heterogene...

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18th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2012

作者： Saha, Shivashis Lu, Ying Deogun, Jitender S. Department of Computer Science and Engineering University of Nebraska-Lincoln Lincoln NE 68588-0115 United States

ISBN: (纸本)9781467330176

Next-generation multi-core multiprocessor real-time systems consume less energy at the cost of increased power density. This increase in power-density results in high heat density and may affect the reliability and performance of real-time systems. Thus, incorporating maximum temperature constraints in scheduling of real-time task sets is an important challenge. This paper investigates thermal-constrained energy-aware partitioning of periodic real-time tasks in heterogeneous multi-core multiprocessor systems. We adopt a power model which considers the impact of temperature and voltage on a processor's static power consumption. Two types of thermal models are used to respectively capture negligible and non-negligible amount of heat transfer among cores. We develop a novel genetic-algorithm based approach to solve the heterogeneous multi-core multiprocessor partitioning problem. Extensive simulations were performed to validate the effectiveness of the approach. Experimental results show that integrating a worst-fit based partitioning heuristic with the genetic algorithm can significantly reduce the total energy consumption of a heterogeneous multi-core multiprocessor real-time system. © 2012 ieee.

关键词： Real time systems

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PartitionSim: A Parallel Simulator for many-cores

PartitionSim: A Parallel Simulator for Many-cores

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Jiao, Shuai Wang, Da Ye, Xiaochun Xu, Weizhi Zhang, Hao Sun, Ninghui Chinese Acad Sci Key Lab Comp Syst & Architecture ICT Beijing Peoples R China

ISBN: (纸本)9780769547497

This paper introduces PartitionSim, a parallel simulator for future thousand-core processors. The purpose of PartitionSim is to improve the simulation performance of many-core architectures at the expense of little accuracy sacrifice. To achieve this goal, we propose a novel technique: timing partition. Timing partition is based on such an observation: in a target system, interacting components communicate with each other and impose simulation synchronization while non-interacting components don't communicate with each other and allow asynchronous simulation. It divides the target timing models into two groups: non-interacting group and interacting group. Non-interacting timing models are simulated by host threads that synchronize little with each other to improve speed and hurt little accuracy, while interacting timing models are simulated by host threads that synchronize strictly with each other to preserve accuracy. Using PartitionSim, We have simulated a target composed of thousands of cores on a 16-core SMP machine. The evaluation results show that timing partition scales well with near linear speedup and has considerable performance at the expense of little accuracy sacrifice.

关键词： Parallel Simulation many-core multi-core

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PGAS for Distributed Numerical Python Targeting multi-core Clusters

PGAS for Distributed Numerical Python Targeting Multi-core C...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Kristensen, Mads Ruben Burgdorff Zheng, Yili Vinter, Brian Univ Copenhagen Niels Bohr Inst DK-1168 Copenhagen Denmark Lawrence Berkeley Natl Lab Berkeley CA 94720 USA

ISBN: (纸本)9780769546759

In this paper we propose a parallel programming model that combines two well-known execution models: Single Instruction, multiple Data (SIMD) and Single Program, multiple Data (SPMD). The combined model supports SIMD-style data parallelism in global address space and supports SPMD-style task parallelism in local address space. One of the most important features in the combined model is that data communication is expressed by global data assignments instead of message passing. We implement this combined programming model into Python, making parallel programming with Python both highly productive and performing on distributed memory multi-core systems. We base the SIMD data parallelism on DistNumPy, an auto-parallelizing version of the Numerical Python (NumPy) package that allows sequential NumPy programs to run on distributed memory architectures. We implement the SPMD task parallelism as an extension to DistNumPy that enables each process to have direct access to the local part of a shared array. To harvest the multi-core benefits in modern processors we exploit multi-threading in both SIMD and SPMD execution models. The multi-threading is completely transparent to the user - it is implemented in the runtime with OpenMP and by using multi-threaded libraries when available. We evaluate the implementation of the combined programming model with several scientific computing benchmarks using two representative multi-core distributed memory systems - an Intel Nehalem cluster with Infiniband interconnects and a Cray XE-6 supercomputer - up to 1536 cores. The benchmarking results demonstrate scalable good performance.

关键词： Parallel Programming Parallel computing Python Scientific computing

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A design of hybrid operating system for a parallel computer with multi-core and many-core processors

A design of hybrid operating system for a parallel computer ...

引用

2nd international workshop on Runtime and Operating systems for Supercomputers, ROSS 2012 - In Conjunction with: ICS 2012

作者： Sato, Mikiko Fukazawa, Go Nagamine, Kiyohiko Sakamoto, Ryuichi Namiki, Mitaro Yoshinaga, Kazumi Tsujita, Yuichi Hori, Atsushi Ishikawa, Yutaka Tokyo University of Agriculture and Technology Japan Kinki University Japan Advanced Institute for Computational Science RIKEN Japan University of Tokyo Japan

ISBN: (纸本)9781450314602

This paper describes the design of an operating system to manage the hybrid computer system architecture with multi-core and many-core processors for Exa-scale computing. In this study, a host operating system (Host OS) on a multi-core processor performs some functions of a lightweight operating system (LWOS) on a many-core processor, in order to dedicate to executing the application program on a many-core processor. In particular, to ensure that LWOS execution does not disturb the application program executed on the many-core processor, the functions such as process management, memory management, and I/O management are delegated to the Host OS. To demonstrate this design, we made an prototype system of a computer equipped with a multi-core processor and a many-core processor using an Intel Xeon dual-core processor system. The Linux and original LWOS were loaded on to each processor and the overhead for executing the program for LWOS from Linux was evaluated. Using this prototype system, the LWOS process can be started with at least 110 μsec overhead for the many-core program. © 2012 ACM.

关键词： Linux

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Cooperative multitasking for GPU-accelerated grid systems 10

Cooperative multitasking for GPU-accelerated grid systems

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workshop on Frontiers of GPU, multi-and many-core systems/10th ieee/ACM international Symposium on Cluster, Cloud and Grid computing (CCGrid)

作者： Ino, Fumihiko Ogita, Akihiro Oita, Kentaro Hagihara, Kenichi Osaka Univ Grad Sch Informat Sci & Technol Suita Osaka 5650871 Japan NEC SOFT Ltd Koto Ku Tokyo 1360082 Japan

ISBN: (纸本)9780769540399

This paper presents a cooperative multitasking method for concurrent execution of scientific and graphics applications on the graphics processing unit (GPU). Our method is designed to accelerate compute unified device architecture-based applications using idle GPU cycles in the office. To prevent significant slow-down of graphics applications, the method divides scientific tasks into smaller pieces, which are then sequentially executed at the appropriate intervals. The method also has flexibility in finding the best tradeoff point between scientific applications and graphics applications. Experimental results show that the proposed method is useful to control the frame rate of the graphics application and the throughput of the scientific application. For example, biological sequence alignment can be processed at approximately 30% of the dedicated throughput while achieving interactive rendering at 58 frames per second. We also show that matrix multiplication can be efficiently processed at 60% of the dedicated throughput during word processing and web browsing. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： multitasking GPU CUDA grid computing

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MR-PBGP: A multi-Root Tree Model for Parallel BGP

MR-PBGP: A Multi-Root Tree Model for Parallel BGP

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Liu, Yaping Zhang, Shuo Wang, Baosheng Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9780769547497

BGP protocol has been confronted with many performance problems caused by large scale networks, and have raised great concerns of industry and academia. In this paper, we present a multi-root tree model called MR-PBGP for parallel BGP in the context of a multi-core platform with shared memory. This model is an integrated model of the neighbor-based division and data division. We prove that threads of BGP constructed by a multi-root tree with binary bough excluding the first-level branch nearest leaves will achieve optimal performance with unlimited number of cores (ideal case) in a router. However, with limited number of cores (actual case), we proposed an approximation algorithm to solve this nonlinear programming problem. Simulation results show that (i) the approximation algorithm can get a good performance speedup and parallel efficiency w.r.t. the increase of its neighbors. (ii) 50% of the optimal performance can be reached by using only 5% of the ideal number of cores. Comparing with other researches, MR-PBGP is a more effective model for parallel BGP.

关键词： parallel BGP multi-core routing convergence time queue theory

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