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Active cells - A computing model for rapid construction of on-chip multi-core systems

Active cells - A computing model for rapid construction of o...

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2012 ieee/ACIS 11th international Conference on Computer and Information Science, ICIS 2012

作者： Friedrich, Felix Liu, Ling Gutknecht, Jürg ETH Zurich Computer Systems Institute Zurich Switzerland

ISBN: (纸本)9780769546940

We present a novel computing model that allows to conveniently construct multi-core systems with different computer architectures, ranging from homogeneous many-core architectures to networks of heterogeneous general purpose processor cores or signal processing engines. A hardware library implemented on Field Programmable Gate Arrays (FPGAs) and a compiler provide a platform for prototyping and constructing distributed systems on a chip. A number of case studies have been carried out to prove the concept conveyed by the computing model. © 2012 ieee.

关键词： Computer architecture

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High-Performance Distributed multi-Model/multi-Kernel Simulations: A Case-Study in Jungle computing

High-Performance Distributed Multi-Model/Multi-Kernel Simula...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Drost, Niels Maassen, Jason van Meersbergen, Maarten A. J. Bal, Henri E. Pelupessy, F. Inti Zwart, Simon Portegies Kliphuis, Michael Dijkstra, Henk A. Seinstra, Frank J. Vrije Univ Amsterdam Dept Comp Sci Amsterdam Netherlands

ISBN: (纸本)9780769546766

High-performance scientific applications require more and more compute power. The concurrent use of multiple distributed compute resources is vital for making scientific progress. The resulting distributed system, a so-called Jungle computing System, is both highly heterogeneous and hierarchical, potentially consisting of grids, clouds, stand-alone machines, clusters, desktop grids, mobile devices, and supercomputers, possibly with accelerators such as GPUs. One striking example of applications that can benefit greatly of Jungle computing systems are multi-Model / multi-Kernel simulations. In these simulations, multiple models, possibly implemented using different techniques and programming models, are coupled into a single simulation of a physical system. Examples include the domain of computational astrophysics and climate modeling. In this paper we investigate the use of Jungle computing systems for such multi-Model / multi-Kernel simulations. We make use of the software developed in the Ibis project, which addresses many of the problems faced when running applications on Jungle computing systems. We create a prototype Jungle-aware version of AMUSE, an astrophysical simulation framework. We show preliminary experiments with the resulting system, using clusters, grids, stand-alone machines, and GPUs.

关键词： Distributed computing Jungle computing High-Performance computing multi-Model Simulations

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IDAMC: A many-core platform with run-time monitoring for mixed-criticality

IDAMC: A many-core platform with run-time monitoring for mix...

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ieee 14th international Symposium on High-Assurance systems Engineering, HASE 2012

作者： Motruk, Boris Diemer, Jonas Buchty, Rainer Ernst, Rolf Berekovic, Mladen Institute of Computer and Network Engineering Technische Universität Braunschweig Germany Department of Chip Design for Embedded Computing Technische Universität Braunschweig Germany

ISBN: (纸本)9780769549125

On a multi- or many-core platform that runs applications of different safety criticality (mixed-criticality), all applications have to be certified to the highest level of criticality, unless they are sufficiently isolated. Isolation enables individual certification of applications and cost-efficient re-certification of single applications after an update. We introduce a parameterizable and synthesizable many-core platform with a fast and scalable monitoring and control mechanism that supports safe sharing of resources. Our contribution is a step towards exploiting the benefits of multi- and many-core platforms for mixed-critical applications. © 2012 ieee.

关键词： Criticality (nuclear fission)

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A Performance Study of Traversing Spatial Indexing Structures in Parallel on GPU

A Performance Study of Traversing Spatial Indexing Structure...

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Kim, Jinwoong Hong, Sumin Nam, Beomseok Ulsan Natl Inst Sci & Technol Sch Elect & Comp Engn Ulsan 689798 South Korea

ISBN: (纸本)9780769547497

CUDA is a parallel programming environment that enables significant performance improvement by lever-aging the massively parallel processing capability of the GPU. Inherently spatial indexing structures such as R-Trees are not well suited for CUDA environment due to its irregular tree traversal for range queries. Traversing irregular tree search paths makes it hard to maximize the utilization of many-core architectures. In this paper, we propose assigning an individual sub-tree to each SMP (streaming multi-processor) in GPGPU, such that CUDA cores in the same SMP co-operate to navigate tree index nodes. This parallel partitioned-indexing improves the utilization of many cores in GPGPU significantly. Also, we propose a new range query search algorithm -three-phase-search that avoids non-sequential random access to tree nodes and accelerates the search performance of spatial indexing structures on GPU. Our experimental results show that GPU-based parallel spatial indexing scheme on NVIDA Tesla M2090 GPGPU outperforms the CPU-based multi-threaded R-trees on AMD Opteron 6128HE processor by two times.

关键词： multi-dimensional indexing multi-dimensional range query GPGPU indexing

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Proceedings - 18th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2012 - 2nd workshop on Cyber-Physical systems, Networks, and Applications, CPSNA 2012

Proceedings - 18th IEEE International Conference on Embedded...

引用

18th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2012

The proceedings contain 60 papers. The topics discussed include: schedulability analysis for processors with aging-aware autonomic frequency scaling;an optimal real-time voltage and frequency scaling for uniform multiprocessors;real-time scheduling of energy harvesting embedded systems with timed automata;thermal-constrained energy-aware partitioning for heterogeneous multi-core multiprocessor real-time systems;MinMax: a sampling interval control algorithm for process control systems;the split-phase synchronisation technique: reducing the pessimism in the WCET analysis of parallelised hard real-time programs;MCFlow: a real-time multi-core aware middleware for dependent task graphs;partitioned scheduling of implicit-deadline sporadic task systems under multiple resource constraints;a parallel algorithm for EDF-schedulability analysis of multi-modal real-time systems;and optimizing data allocation for loops on embedded systems with scratch-pad memory.

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NUMA Aware Iterative Stencil Computations on many-core systems

NUMA Aware Iterative Stencil Computations on Many-Core Syste...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Shaheen, Mohammed Strzodka, Robert Max Planck Inst Informat Integrat Sci Comp Grp Saarbrucken Germany

ISBN: (纸本)9780769546759

Temporal blocking in iterative stencil computations allows to surpass the performance of peak system bandwidth that holds for a single stencil computation. However, the effectiveness of temporal blocking depends strongly on the tiling scheme, which must account for the contradicting goals of spatio-temporal data locality, regular memory access patterns, parallelization into many independent tasks, and data-to-core affinity for NUMA-aware data distribution. Despite the prevalence of cache coherent non-uniform memory access (ccNUMA) in todays many-core systems, this latter aspect has been largely ignored in the development of temporal blocking algorithms. Building upon previous cache-aware [1] and cache-oblivious [2] schemes, this paper develops their NUMA-aware variants, explaining why the incorporation of data-to-core affinity as an equally important goal necessitates also new tiling and parallelization strategies. Results are presented on an 8 socket dual-core and a 4 socket oct-core systems and compared against an optimized naive scheme, various peak performance characteristics, and related schemes from literature.

关键词： stencil computation temporal blocking NUMA-aware data distribution affinity cache-oblivious cache-aware parallelism and locality

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Hybridizing S3D into an Exascale Application using OpenACC An approach for moving to multi-Petaflops and Beyond

Hybridizing S3D into an Exascale Application using OpenACC A...

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25th ACM/ieee international Conference for High Performance computing, Networking, Storage and Analysis (SC)

作者： Levesque, John M. Sankaran, Ramanan Grout, Ray Cray Inc CTO Off Knoxville TN 37932 USA Oak Ridge Natl Lab Sci Comp Grp Oak Ridge TN USA Natl Renewable Energy Lab Computat Sci Ctr Golden CO USA

ISBN: (纸本)9781467308052;9781467308045

Hybridization is the process of converting an application with a single level of parallelism to an application with multiple levels of parallelism. Over the past 15 years a majority of the applications that run on High Performance computing systems have employed MPI for all of the parallelism within the application. In the Peta-Exascale computing regime, effective utilization of the hardware requires multiple levels of parallelism matched to the macro architecture of the system to achieve good performance. A hybridized code base is performance portable when sufficient parallelism is expressed in an architecture agnostic form to achieve good performance on a range of available systems. The hybridized S3D code is performance portable across today's leading many core and GPU accelerated systems. The OpenACC framework allows a unified code base to be deployed for either (manycore CPU or manycore CPU+GPU) while permitting architecture specific optimizations to expose new dimensions of parallelism to be utilized.

关键词： component OpenMP OpenACC Accelerators MPI Directives multi-core Communication overlap Hybrid Architectures Hybrid Programming

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Classification of Massively Parallel Computer Architectures

Classification of Massively Parallel Computer Architectures

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Shami, Muhammad Ali Hemani, Ahmed Royal Inst Technol Dept ES S-16440 Stockholm Sweden

ISBN: (纸本)9780769546766

Faced with slowing performance and energy benefits of technology scaling, VLSI/Computer architectures have turned from parallel to massively parallel machines for personal and embedded applications in the form of multi and many core architectures. Additionally, in the pursuit of finding the sweet spot between engineering and computational efficiency, massively parallel Coarse Grain Reconfigurable Architectures(CRGAs) have been researched. While these articles have been surveyed, they have not been rigorously classified to enable objective differentiation and comparison for performance, area and flexibility. In this paper, we extend the well known Skillicorn taxonomy to create new classes, present a scoring system to rate these classes on flexibility, and present equations for early estimation of area and configuration overheads. Furthermore, we use this extended classification scheme to classify and compare 25 different massively parallel architectures that covers most of the reported CGRAs and other well known multi and many core architectures.

关键词： ARCHITECTURE scoring system MASSIVELY-PARALLEL COMPUTERS Application Document embedded application core construction New classes classification scheme

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Performance Benefits of Heterogeneous computing in HPC Workloads

Performance Benefits of Heterogeneous Computing in HPC Workl...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Lee, Victor W. Grochowski, Ed Geva, Robert Intel Corp Santa Clara CA 95054 USA

ISBN: (纸本)9780769546766

Chip multi-processors (CMPs) with increasing number of processor cores are now becoming widely available. To take advantage of many-core CMPs, applications must be parallelized. However, due to the nature of algorithm / programming model, some parts of the application would remain serial. According to Amdahl's law, the speedup of a parallel application is limited by the amount of serial execution it has. For a CMP with many cores, this can be a serious limitation. To take full advantage of the increasing number of cores, one must try to reduce the execution time of the serial portion of a parallel program. However, rewriting an application takes time and often the return on the effort invested may not justify parallelizing every part of the program. Heterogeneous many-core CMP design is one possible solution to support massive parallel execution and to provide a reasonable single-thread performance. In this paper, we use a simple spreadsheet model to evaluate homogeneous and heterogeneous CMP designs using execution profiles of real HPC applications. Evaluated on 12 parallel HPC applications, we show that heterogeneous CMPs can outperform homogeneous CMPs by up to 1.35x with an average speedup of 1.06x when both the heterogeneous CMPs and homogeneous CMPs are constrained to use the same power budget. Our study found the heterogeneous CMPs can take advantage of serial portion of execution that is as little as 2% of total run time to provide performance benefit. This suggests heterogeneous computing can help mitigate the effect of not parallelizing some portions of an application due to return on investment concern on programming efforts.

关键词： Chip multi-processors (CMPs) HPC parallel programs heterogeneous computing

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Implementation of Motion Estimation Based On Heterogeneous Parallel computing System with OpenCL

Implementation of Motion Estimation Based On Heterogeneous P...

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Zhang, Jinglin Nezan, Jean-Francois Cousin, Jean-Gabriel Univ Europeenne Bretagne Rennes France CNRS INSA IETR UMR 6164 F-35708 Rennes France

ISBN: (纸本)9780769547497

Heterogeneous computing system increases the performance of parallel computing in many domain of general purpose computing with CPU, GPU and other accelerators. Open computing Language (OpenCL) is the first open, royalty-free standard for heterogenous computing on multi hardware platforms. In this paper, we propose a parallel Motion Estimation (ME) algorithm implemented using OpenCL and present several optimization strategies applied in our OpenCL implementation of the motion estimation. In the same time, we implement the proposed algorithm on our heterogeneous computing system which contains one CPU and one GPU, and propose one method to determine the balance to distribute the workload in heterogeneous computing system with OpenCL. According to experiments, our motion estimator with achieves 100x to 150x speed-up compared with its implementation with C code executed by single CPU core and our proposed method obtains obviously enhancement of performance in based on our heterogeneous computing system.

关键词： Motion Estimation OpenCL Heterogeneous Parallel CPU GPU

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