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共 976 条记录，以下是581-590 订阅

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Deriving a Methodology for Code Deployment on multi-core Platforms via Iterative Manual Optimizations

Deriving a Methodology for Code Deployment on Multi-Core Pla...

引用

26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： McCool, Stuart Milligan, Peter Sage, Paul Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast Antrim North Ireland

ISBN: (纸本)9780769546766

In recent years, there has been what can only be described as an explosion in the types of processing devices one can expect to find within a given computer system. These include the multi-core CPU, the General Purpose Graphics Processing Unit (GPGPU) and the Accelerated Processing Unit (APU), to name but a few. The widespread uptake of these systems presents would-be users with at least two problems. Firstly, each device exposes a complex underlying architecture which must be appreciated in order to attain optimal performance. This is coupled with the fact that a single system can support an arbitrary number of such devices. Consequently, fully leveraging the performance capabilities of such a system must come at a cost - increasingly prolonged development times. Adhering to a methodology will have the significant industrial impact of reducing these development times. This paper describes the continued formulation of such a novel methodology. Two real world scientific programs are optimized for execution on the CUDA platform. Double precision accuracy and optimized speedups (which include PCI-E transfer times) of 15x and 17x are achieved.

关键词： heterogeneous computing GPGPU methodology toolset artificial intelligence characterization Racah Slater

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multithreaded Clustering for multi-level Hypergraph Partitioning

Multithreaded Clustering for Multi-level Hypergraph Partitio...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Catalyuerek, Uemit V. Deveci, Mehmet Kaya, Kamer Ucar, Bora Ohio State Univ Dept Biomed Informat Columbus OH 43210 USA CNRS & LIP ENS Lyon F-69364 Lyon France

ISBN: (纸本)9780769546759

Requirements for efficient parallelization of many complex and irregular applications can be cast as a hypergraph partitioning problem. The current-state-of-the art software libraries that provide tool support for the hypergraph partitioning problem are designed and implemented before the game-changing advancements in multi-core computing. Hence, analyzing the structure of those tools for designing multithreaded versions of the algorithms is a crucial tasks. The most successful partitioning tools are based on the multi-level approach. In this approach, a given hypergraph is coarsened to a much smaller one, a partition is obtained on the the smallest hypergraph, and that partition is projected to the original hypergraph while refining it on the intermediate hypergraphs. The coarsening operation corresponds to clustering the vertices of a hypergraph and is the most time consuming task in a multi-level partitioning tool. We present three efficient multithreaded clustering algorithms which are very suited for multi-level partitioners. We compare their performance with that of the ones currently used in today's hypergraph partitioners. We show on a large number of real life hypergraphs that our implementations, integrated into a commonly used partitioning library PaToH, achieve good speedups without reducing the clustering quality.

关键词： multi-level hypergraph partitioning coarsening multithreaded clustering algorithms multicore programming

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Massively Parallel X-ray Scattering Simulations

Massively Parallel X-ray Scattering Simulations

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25th ACM/ieee international Conference for High Performance computing, Networking, Storage and Analysis (SC)

作者： Sarje, Abhinav Li, Xiaoye S. Chourou, Slim Chan, Elaine R. Hexemer, Alexander Lawrence Berkeley Natl Lab Computat Res Div Berkeley CA 94720 USA Lawrence Berkeley Natl Lab Adv Light Source Berkeley CA 94720 USA

ISBN: (纸本)9781467308052;9781467308045

Although present X-ray scattering techniques can provide tremendous information on the nano-structural properties of materials that are valuable in the design and fabrication of energy-relevant nano-devices, a primary challenge remains in the analyses of such data. In this paper we describe a high-performance, flexible, and scalable Grazing Incidence Small Angle X-ray Scattering simulation algorithm and codes that we have developed on multi-core/CPU and many-core/GPU clusters. We discuss in detail our implementation, optimization and performance on these platforms. Our results show speedups of similar to 125x on a Fermi-GPU and similar to 20x on a Cray-XE6 24-core node, compared to a sequential CPU code, with near linear scaling on multi-node clusters. To our knowledge, this is the first GISAXS simulation code that is flexible to compute scattered light intensities in all spatial directions allowing full reconstruction of GISAXS patterns for any complex structures and with high-resolutions while reducing simulation times from months to minutes.

关键词： X-ray scattering data analysis design engineering graphics processing units materials science computing multiprocessing systems nanofabrication

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Parametric Utilization Bounds for Fixed-Priority multiprocessor Scheduling

Parametric Utilization Bounds for Fixed-Priority Multiproces...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Guan, Nan Stigge, Martin Yi, Wang Yu, Ge Uppsala Univ Uppsala Sweden Northeastern Univ Shenyang Peoples R China

ISBN: (纸本)9780769546759

Future embedded real-time systems will be deployed on multi-core processors to meet the dramatically increasing high-performance and low-power requirements. This trend appeals to generalize established results on uniprocessor scheduling, particularly the various utilization bounds for schedulability test used in system design, to the multiprocessor setting. Recently, this has been achieved for the famous Liu and Layland utilization bound by applying novel task splitting techniques. However, parametric utilization bounds that can guarantee higher utilizations (up to 100%) for common classes of systems are not yet known to be generalizable to multiprocessors as well. In this paper, we solve this problem for most parametric utilization bounds by proposing new task partitioning algorithms based on exact response time analysis. In addition to the worst-case guarantees, as the exact response time analysis is used for task partitioning, our algorithms significantly improve average-case utilization over previous work.

关键词： multiprocessor Bound time series analysis Land use Fixed Priority scheduling of multiprocessor multi-core processors Parametric Reaction Time

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Compression speed enhancements to LZO for multi-core systems

Compression speed enhancements to LZO for multi-core systems

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24th international Symposium on Computer Architecture and High Performance computing, SBAC-PAD 2012

作者： Kane, Jason Yang, Qing Department of Electrical Computer and Biomedical Engineering University of Rhode Island Kingston RI 02881 United States

ISBN: (纸本)9781467347907

This paper examines several promising throughput enhancements to the Lempel-Ziv-Oberhumer (LZO) 1x-1-15 data compression algorithm. Of many algorithm variants present in the current library version, 2.06, LZO 1x-1-15 is considered to be the fastest, geared toward speed rather than compression ratio. We present several algorithm modifications tailored to modern multi-core architectures in this paper that are intended to increase compression speed while minimizing any loss in compression ratio. On average, the experimental results show that on a modern quad core system, a 3.9x speedup in compression time is achieved over the baseline algorithm with no loss to compression ratio. Allowing for a 25% loss in compression ratio, up to a 5.4x speedup in compression time was observed. © 2012 ieee.

关键词： Real time systems

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Scheduling OR-parallelism in YapOr and ThOr on multi-core Machines

Scheduling OR-parallelism in YapOr and ThOr on Multi-Core Ma...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Dutra, Ines Rocha, Ricardo Costa, Vitor Santos Silva, Fernando Santos, Joao Univ Porto CRACS Rua Campo Alegre 1021-1055 P-4169007 Oporto Portugal Univ Porto INESC Porto TEC Fac Sci Dept Comp Sci P-4169007 Oporto Portugal

ISBN: (纸本)9780769546766

In this work we perform a detailed study of different or-scheduling strategies varying several parameters in two or-parallel systems, YapOr and ThOr, running on multi-core machines. Our results show that some kinds of applications are sensitive to the choice of scheduling strategy adopted. In particular, the choice of scheduling parameters mostly affect applications that have short execution times, which, despite having speedups, have their performance significantly affected. Our results also show that topmost dispatching can be more advantageous than bottommost dispatching, a finding that contradicts previous works in this area. One last finding is that YapOr and ThOr are affected differently by changes in scheduling with ThOr performing significantly better than YapOr in several applications.

关键词： Scheduling strategies Parallelism Prolog implementation

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Accelerating string matching for bio-computing applications on multi-core CPUs

Accelerating string matching for bio-computing applications ...

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2012 ieee 7th international Conference on Industrial and Information systems, ICIIS 2012

作者： Herath, Damayanthi Lakmali, Chathurika Ragel, Roshan Department of Computer Engineering University of Peradeniya Peradeniya Sri Lanka

ISBN: (纸本)9781467326056

Huge amount of data in the form of strings are being handled in bio-computing applications and searching algorithms are quite frequently used in them. many methods utilizing on both software and hardware are being proposed to accelerate processing of such data. The typical hardware-based acceleration techniques either require special hardware such as generalpurpose graphics processing units (GPGPUs) or need building a new hardware such as an FPGA based design. On the other hard, software-based acceleration techniques are easier since they only require some changes in the software code or the software architecture. Typical software-based techniques make use of computers connected over a network, also known as a network grid to accelerate the processing. In this paper, we test the hypothesis that multi-core architectures should provide better performance in this kind of computation, but still it would depend on the algorithm selected as well as the programming model being utilized. We present the acceleration of a string-searching algorithm on a multi-core CPU via a POSIX thread based implementation. Our implementation on an 8-core processor (that supports 16-threads) resulted in 9x throughput improvement compared to a single thread implementation. © 2012 ieee.

关键词： Program processors

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Acceleration of Monte-Carlo Molecular Simulations on Hybrid computing Architectures

Acceleration of Monte-Carlo Molecular Simulations on Hybrid ...

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30th ieee international Conference on Computer Design (ICCD)

作者： Braun, Claus Holst, Stefan Wunderlich, Hans-Joachim Castillo, Juan Manuel Gross, Joachim Univ Stuttgart Inst Comp Architecture & Comp Engn D-70569 Stuttgart Germany

ISBN: (纸本)9781467330527

Markov-Chain Monte-Carlo (MCMC) methods are an important class of simulation techniques, which execute a sequence of simulation steps, where each new step depends on the previous ones. Due to this fundamental dependency, MCMC methods are inherently hard to parallelize on any architecture. The upcoming generations of hybrid CPU/GPGPU architectures with their multi-core CPUs and tightly coupled many-core GPGPUs provide new acceleration opportunities especially for MCMC methods, if the new degrees of freedom are exploited correctly. In this paper, the outcomes of an interdisciplinary collaboration are presented, which focused on the parallel mapping of a MCMC molecular simulation from thermodynamics to hybrid CPU/GPGPU computing systems. While the mapping is designed for upcoming hybrid architectures, the implementation of this approach on an NVIDIA Tesla system already leads to a substantial speedup of more than 87x despite the additional communication overheads.

关键词： Hybrid Computer Architectures GPGPU Markov-Chain Monte-Carlo Molecular Simulation Thermodynamics

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MATE-CG: A MapReduce-Like Framework for Accelerating Data-Intensive Computations on Heterogeneous Clusters

MATE-CG: A MapReduce-Like Framework for Accelerating Data-In...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Jiang, Wei Agrawal, Gagan Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9780769546759

Clusters of GPUs have rapidly emerged as the means for achieving extreme-scale, cost-effective, and power-efficient high performance computing. At the same time, high-level APIs like map-reduce are being used for developing several types of high-end and/or data-intensive applications. Map-reduce, originally developed for data processing applications, has been successfully used for many classes of applications that involve a significant amount of computations, such as machine learning, image processing, and data mining applications. Because such applications can be accelerated using GPUs (and other accelerators), there has been interest in supporting map-reduce-like APIs on GPUs. However, while the use of map-reduce for a single GPU has been studied, developing map-reduce-like models for programming a heterogeneous CPU-GPU cluster remains an open challenge. This paper presents the MATE-CG system, which is a map-reduce-like framework based on the generalized reduction API. We develop support for enabling scalable and efficient implementation of data-intensive applications in a heterogeneous cluster of multi-core CPUs and many-core GPUs. Our contributions are three folds: 1) we port the generalized reduction model on clusters of modern GPUs with a map-reduce-like API, dealing with very large datasets;2) we further propose three schemes to better utilize the computing power of CPUs and/or GPUs and develop an auto-tuning strategy to achieve the best-possible heterogeneous configuration for iterative applications;3) we show how analytical models can be used to optimize important parameters in our system. We evaluate our system using three representative data-intensive applications and report results on a heterogeneous cluster of 128 CPU cores and 16 GPUs (7168 GPU cores). We show an average speedup of 87x on this cluster over execution with 2 CPU-cores. Our applications also achieve an average improvement of 25% by using CPU cores and GPUs simultaneously, over the best pe

关键词： Data-Intensive computing GPUs Heterogeneous systems

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Implementation and Evaluation of Large Interconnection Routers for Future many-core Networks on Chip

Implementation and Evaluation of Large Interconnection Route...

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14th ieee international Conference on High Performance computing and Communications (HPCC) / ieee 9th international Conference on Embedded Software and systems (ICESS)

作者： Zaytoun, Amir H. M. Fahmy, Hossam A. H. Elsayed, Khaled M. F. Cairo Univ Cairo 12613 Egypt

ISBN: (纸本)9780769547497

As the number of processing elements in the future Networks on Chip (NoC) increases from multi-cores to many-cores, the role of the interconnection communications becomes more critical. The number of cores on a System on Chip (SoC) will reach thousands in the near future as predicted by the international Technology Roadmap for Semiconductors (ITRS). Currently, NoC interconnections are mostly implemented with mxn 2-D mesh topology connecting small size routers. This will represent the bottleneck to the communication latency for the increasing number of cores where the average number of hops the data have to pass will increase. In this paper, we propose an alternative NoC interconnecting scheme by using large routers interconnecting large number of cores in star topology. This interconnection scheme can be scaled up by using hierarchical-star or fat-tree topologies. We present the implementation and performance evaluation of three large router architectures and compare their efficiency to the small 5x5 router used in the mesh topology. We develop a simulating environment that resembles the real NoC conditions to test the routers throughput and average latency on different buffer sizes and under different traffic loads. We also synthesize them to estimate the area and power consumption. Then, routers efficiencies are calculated with respect to the area and power consumption.

关键词： System-on-chip (SoC) Networks-on-chip (NoC) Crossbar Batcher-Banyan

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