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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 976 条记录，以下是601-610 订阅

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Task Scheduling for GPU Accelerated Hybrid OLAP systems with multi-core Support and Text-to-Integer Translation

Task Scheduling for GPU Accelerated Hybrid OLAP Systems with...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Malik, Maria Riha, Lubomir Shea, Colin El-Ghazawi, Tarek George Washington Univ Dept Elect & Comp Engn Washington DC 20052 USA

ISBN: (纸本)9780769546766

OLAP (On-Line Analytical Processing) is a powerful method for analyzing the excessive amount of data related to business intelligence applications. OLAP utilizes the efficient multidimensional data structure referred to as the OLAP cube to answer multi-faceted analytical queries. As queries become more complex and the dimensionality and size of the cube grows, the processing time required to aggregate queries increases. In this paper, we are proposing: (1) a parallel implementation of MOLAP cube using OpenMP;(2) a text-to-integer translation method to allow effective string processing on GPU;and (3) a new scheduling algorithm that support these new features. To be able to process string queries on the GPU, we are introducing a text-to-integer translation method which works with multiple dictionaries. The translation is necessary only for the GPU side of the system. To support the translation and parallel CPU implementation, a new scheduling algorithm is proposed. The scheduler divides multi-core processor(s) of a shared memory system into a processing partition and a preprocessing (or translation) partition. The performance of the new system is evaluated. The text-to-integer translation adds a new vital functionality to our system;however it also slows down the GPU processing by 7% when compare to original implementation without string support. The performance measurements indicate that due to the parallel implementation, the processing rate of the CPU partition improves from 12 to 110 queries per second. Moreover, the CPU partition is now able to process OLAP cubes of size 32 GB at rate of 11 queries per second. The total performance of the entire hybrid system (CPU + GPU) increased from 102 to 228 queries per second.

关键词： OLAP GPU acceleration OpenMP scheduling

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Proc. of the 1st Int. workshop on Secure and Resilient Architectures and Syst., SRAS 2012 - Held in Conjunction with the 21st Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2012

Proc. of the 1st Int. Workshop on Secure and Resilient Archi...

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1st international workshop on Secure and Resilient Architectures and systems, SRAS 2012 - Held in Conjunction with the 21st international Conference on Parallel Architectures and Compilation Techniques, PACT 2012

ISBN: (纸本)9781450317771

The proceedings contain 5 papers. The topics discussed include: impact of compiler optimizations on voltage droops and reliability of an SMT, multi-core processor;a secure role-based administration model for attributes;enhanced boosting-based algorithm for intrusion detection in virtual machine environments;securing cloud storage systems through a virtual machine monitor;and towards provenance and risk-awareness in social computing.

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A Reconfigurable computing Approach for Efficient and Scalable Parallel Graph Exploration

A Reconfigurable Computing Approach for Efficient and Scalab...

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23rd ieee international Conference on Application-Specific systems, Architectures and Processors (ASAP)

作者： Betkaoui, Brahim Wang, Yu Thomas, David B. Luk, Wayne Univ London Imperial Coll Sci Technol & Med Dept Comp London England Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing Peoples R China Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

ISBN: (纸本)9780769547688

In many application domains, data are represented using large graphs involving millions of vertices and billions of edges. Graph exploration algorithms, such as breadth-first search (BFS), are largely dominated by memory latency and are challenging to process efficiently. In this paper, we present a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration problems. Our methodology is based on a reconfigurable hardware architecture which decouples computation and communication while keeping multiple memory requests in flight at any given time, taking advantage of the hardware capabilities of both FPGAs and the parallel memory subsystem. To validate our methodology, we provide a detailed design description of the Breadth-First Search algorithm on an FPGA-based high performance computing system. Using graph data based on the power-law graphs found in real-word problems, we are able to achieve performance results that are superior to those of high performance multi-core systems in the recent literature for large graph instances, and a throughput in excess of 2.5 billion traversed edges per second on RMAT graphs with 16 million vertices and over a billion edges. Using four Virtex-5 LX330 FPGAs based on 65nm technology and running at 75MHz, our BFS design achieves more than twice the speed of a 32-core Xeon X7560 based on 45nm technology and running at 2.26GHz.

关键词： Line graph memory latency breadth first search Exploration graph data reconfigurable hardware PARALLEL PROCESSING (COMPUTERS) Running Power law

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Designing Network Failover and Recovery in MPI for multi-Rail InfiniBand Clusters

Designing Network Failover and Recovery in MPI for Multi-Rai...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Raikar, S. Pai Subramoni, H. Kandalla, K. Vienne, J. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9780769546766

The emerging trends of designing commodity-based supercomputing systems have a severe detrimental impact on the Mean-Time-Between-Failures (MTBF). The MTBF for typical HEC installations is currently estimated to be between eight hours and fifteen days [1]. Failures in the interconnect fabric account for a fair share of the total failures occurring in such systems. This will continue to degrade as system sizes become larger. Thus, it is highly desirable that next generation system architectures and software environments provide sophisticated network level fault-tolerance and fault-resilient solutions. In the past few years, the number of cores on processors has increased dramatically. To make efficient use of these machines it is necessary to provide the required bandwidth to all the cores. To keep up with the multi-core trend, current generation supercomputers and clusters are designed with multiple network cards (rails) to provide enhanced data transfer capabilities. Besides providing enhanced performance, such multi-rail networks can also be leveraged to provide network level fault resilience. This paper presents a design for a failover mechanism in a multi-rail scenario, for handling network failures and their recovery without compromising on performance. In a general message passing scenario, whenever there is a network failure, the entire job aborts. Our design allows the job to continue even when a network failure occurs, by using the remaining rails for communication. Once the rail recovers from the failure, we also propose a protocol to re-establish connections on that rail and resume normal operations. We experimentally demonstrate that our implementation adds very little overhead and is able to deliver good performance which is comparable to that of the other rails running in isolation. We also show that the recovery is immediate and is associated with no additional overhead. We also depict sustenance and reliability of the design by running application be

关键词： Failover Fault Tolerance MPI

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Designing a Collaborative Filtering Recommender on the Single Chip Cloud Computer

Designing a Collaborative Filtering Recommender on the Singl...

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25th ACM/ieee international Conference for High Performance computing, Networking, Storage and Analysis (SC)

作者： Tripathy, Aalap Patra, Atish Mohan, Suneil Mahapatra, Rabi Texas A&M Univ Dept Comp Sci & Engn College Stn TX 77843 USA

ISBN: (纸本)9780769549569;9781467362184

Fast response requirements for big-data applications on cloud infrastructures continues to grow. At the same time, many cores on-chip have now become a reality. These developments are set to redefine infrastructure nodes of cloud data centers in the future. For this to happen, parallel programming runtimes need to be designed for many-cores on chip as the target architecture. In this paper, we show that the commonly used MapReduce programming paradigm can be adapted to run on Intel's experimental single chip cloud computer (SCC) with 48-cores on chip. We demonstrate this using a Collaborative Filtering (CF) recommender system as an application. This is a widely used technique for information filtering to predict user's preference towards an unknown item from their past ratings. These systems are typically deployed in distributed clusters and operate on large apriori datasets. We address scalability with data partitioning, combining and sorting algorithms, maximize data locality to minimize communication cost within the SCC cores. We demonstrate similar to 2x speedup, similar to 94% lower energy consumption for benchmark workloads as compared to a distributed cluster of single and multi-processor nodes.

关键词： component Recommendation system Mapreduce Collaborative Filtering many-core Single Chip Cloud Computer Scalability personalization

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LPFSC: A Light Weight Parallel Framework for Super computing

LPFSC: A Light Weight Parallel Framework for Super Computing

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13th international Conference on Parallel and Distributed computing, Applications, and Technologies (PDCAT)

作者： Ou, Yulong Li, Bo Yuan, Zheng Hao, Qiang Luan, Zhongzhi Qian, Depei Beihang Univ Sino German Joint Software Inst Dept Comp Sci & Engn Beijing 100191 Peoples R China

ISBN: (纸本)9780769548791

Supercomputing on the heterogeneous architectures that integrate multi-core or many-cores processors has been developed at a dramatically speed. It is widely used in theoretical physics, theoretical chemistry, climate modeling, biology simulation and medicine research for high-performance and energy-efficient computing. Yet it is still a big challenge to users when trying to run their scientific applications efficiently on large-scale supercomputers constructed by using heterogeneous multiprocessors. On the other hand, overhead cost issues of a large supercomputer for its resource managements, job scheduling, and system reliability become more and more important. In this paper, LPFSC, a light weight parallel framework for supercomputing, is presented, which helps programmers in planning their tasks on a supercomputer. In a huge supercomputer system, there might be a hundred of thousands of nodes, over a million processor cores and many other kinds of processors, general main-slave computing mode can hardly handle the huge amount of heterogeneous processors. LPFSC consists of modules for multiple master-slave support, load balance among huge amount computing tasks, and reliability support. Additional features will be added in the near future and it is supposed to provide good support for large heterogeneous computer systems. Finally, large amount tasks of 2D-FFT in varying size are tested under the framework for evaluation, which can scale to more than 300 processors.

关键词： LPSFC heterogeneous architecture supercomputing

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Proceedings - 24th international Symposium on Computer Architecture and High Performance computing, SBAC-PAD 2012

Proceedings - 24th International Symposium on Computer Archi...

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24th international Symposium on Computer Architecture and High Performance computing, SBAC-PAD 2012

The proceedings contain 36 papers. The topics discussed include: the network adapter: the missing link between MPI applications and network performance;on the efficiency of register file versus broadcast interconnect for collective communications in data-parallel hardware accelerators;network endpoints for clusters of SMPs;assessing energy efficiency of fault tolerance protocols for HPC systems;using heterogeneous networks to improve energy efficiency in direct coherence protocols for many-core CMPs;energy savings via dead sub-block prediction;scalable thread scheduling in asymmetric multicores for power efficiency;divergence analysis with affine constraints;exploiting concurrent GPU operations for efficient work stealing on multi-GPUs;sparse fast Fourier transform on GPUs and multi-core CPUs;cloud workload analysis with SWAT;and scalable algorithms for distributed-memory adaptive mesh refinement.

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Hierarchical QR factorization algorithms for multi-core cluster systems

Hierarchical QR factorization algorithms for multi-core clus...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Dongarra, Jack Faverge, Mathieu Herault, Thomas Langou, Julien Robert, Yves Univ Tennessee Knoxville Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Manchester Manchester M13 9PL Lancs England Univ Colorado Denver CO USA Ecole Normale Superieure Lyon Lyon France

ISBN: (纸本)9780769546759

This paper describes a new QR factorization algorithm which is especially designed for massively parallel platforms combining parallel distributed multi-core nodes. These platforms make the present and the foreseeable future of high-performance computing. Our new QR factorization algorithm falls in the category of the tile algorithms which naturally enables good data locality for the sequential kernels executed by the cores (high sequential performance), low number of messages in a parallel distributed setting (small latency term), and fine granularity (high parallelism). Each tile algorithm is uniquely characterized by its sequence of reduction trees. In the context of a cluster of multicores, in order to minimize the number of inter-processor communications (aka, "communication-avoiding" algorithm), it is natural to consider two-level hierarchical trees composed of an "inter-node" tree which acts on top of "intra-node" trees. At the intra-node level, we propose a hierarchical tree made of three levels: (0) "TS level" for cache-friendliness, (1) "low level" for decoupled highly parallel inter-node reductions, (2) "coupling level" to efficiently resolve interactions between local reductions and global reductions. Our hierarchical algorithm and its implementation are flexible and modular, and can accommodate several kernel types, different distribution layouts, and a variety of reduction trees at all levels, both inter-cluster and intra-cluster. Numerical experiments on a cluster of multicore nodes (1) confirm that each of the four levels of our hierarchical tree contributes to build up performance and (2) build insights on how these levels influence performance and interact within each other. Our implementation of the new algorithm with the DAGUE scheduling tool significantly outperforms currently available QR factorization softwares for all matrix shapes, thereby bringing a new advance in numerical linear algebra for petascale and exascale platforms.

关键词： QR factorization numerical linear algebra hierarchical architecture distributed memory cluster multicore

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Fast and Efficient Graph Traversal Algorithm for CPUs: Maximizing Single-Node Efficiency

Fast and Efficient Graph Traversal Algorithm for CPUs: Maxim...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Chhugani, Jatin Satish, Nadathur Kim, Changkyu Sewall, Jason Dubey, Pradeep Intel Corp Parallel Comp Lab Santa Clara CA 95051 USA

ISBN: (纸本)9780769546759

Graph-based structures are being increasingly used to model data and relations among data in a number of fields. Graph-based databases are becoming more popular as a means to better represent such data. Graph traversal is a key component in graph algorithms such as reachability and graph matching. Since the scale of data stored and queried in these databases is increasing, it is important to obtain high performing implementations of graph traversal that can efficiently utilize the processing power of modern processors. In this work, we present a scalable Breadth-First Search Traversal algorithm for modern multi-socket, multi-core CPUs. Our algorithm uses lock- and atomic-free operations on a cache-resident structure for arbitrary sized graphs to filter out expensive main memory accesses, and completely and efficiently utilizes all available bandwidth resources. We propose a work distribution approach for multi-socket platforms that ensures load-balancing while keeping cross-socket communication low. We provide a detailed analytical model that accurately projects the performance of our single- and multi-socket traversal algorithms to within 5-10% of obtained performance. Our analytical model serves as a useful tool to analyze performance bottlenecks on modern CPUs. When measured on various synthetic and real-world graphs with a wide range of graph sizes, vertex degrees and graph diameters, our implementation on a dual-socket Intel (R) Xeon (R) X5570 (Intel microarchitecture code name Nehalem) system achieves 1.5X-13.2X performance speedup over the best reported numbers. We achieve around 1 Billion traversed edges per second on a scale-free R-MAT graph with 64M vertices and 2 Billion edges on a dual-socket Nehalem system. Our optimized algorithm is useful as a building block for efficient multi-node implementations and future exascale systems, thereby allowing them to ride the trend of increasing per-node compute and bandwidth resources.

关键词： bandwidth efficient Graph traversal multi-socket single node

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Scalable parallel event-driven HDL simulation for multi-cores

Scalable parallel event-driven HDL simulation for multi-core...

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2012 international Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2012

作者： Ahmad, Tariq Bashir Kim, Namdo Min, Byeong Kalia, Apurva Ciesielski, Maciej Yang, Seiyang University of Massachusetts Amherst ECE Department United States Samsung Electronics Korea Republic of Cadence Design Systems India Pusan National University CE Department Busan Korea Republic of

ISBN: (纸本)9781467306867

multi-core processors have become common in current computing platforms. Today, most of multi-core workstations and PCs have adopted NUMA (Non-Uniform Memory Access) advanced memory architecture for high performance and scalability. In response, EDA (Electronic Design Automation) community has applied significant effort to parallelize many EDA algorithms with some success. However, event-driven simulation of designs modeled in HDL (Hardware Description Language) has not achieved meaningful progress so far. This paper proposes a highly scalable parallel, event-driven HDL simulation method, based upon accurate stimulus prediction. The paper presents the basic idea of this approach and discusses why this new method is ideally positioned for achieving high parallelism with NUMA architecture. © 2012 ieee.

关键词： Computer hardware description languages

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