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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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multi-level Layout Optimization for Efficient Spatio-temporal Queries on ISABELA-compressed Data

Multi-level Layout Optimization for Efficient Spatio-tempora...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Gong, Zhenhuan Lakshminarasimhan, Sriram Jenkins, John Kolla, Hemanth Ethier, Stephane Chen, Jackie Ross, Robert Klasky, Scott Samatova, Nagiza F. North Carolina State Univ Raleigh NC 27695 USA Oak Ridge Natl Lab Oak Ridge TN 37831 USA Sandia Natl Labs Livermore CA 94551 USA Princeton Univ Princeton Plasma Phys Lab POB 451 Princeton NJ 08543 USA Argonne Natl Lab 9700 S Cass Ave Argonne IL 60439 USA

ISBN: (纸本)9780769546759

The size and scope of cutting-edge scientific simulations are growing much faster than the I/O subsystems of their runtime environments, not only making I/O the primary bottleneck, but also consuming space that pushes the storage capacities of many computing facilities. These problems are exacerbated by the need to perform data-intensive analytics applications, such as querying the dataset by variable and spatio-temporal constraints, for what current database technologies commonly build query indices of size greater than that of the raw data. To help solve these problems, we present a parallel query-processing engine that can handle both range queries and queries with spatio-temporal constraints, on B-spline compressed data with user-controlled accuracy. Our method adapts to widening gaps between computation and I/O performance by querying on compressed metadata separated into bins by variable values, utilizing Hilbert space-filling curves to optimize for spatial constraints and aggregating data access to improve locality of per-bin stored data, reducing the false positive rate and latency-bound I/O operations (such as seek) substantially. We show our method to be efficient with respect to storage, computation, and I/O compared to existing database technologies optimized for query processing on scientific data.

关键词： IO Operating Environment Storage capacity Range searching Hilbert space query analysis Bins False-positives synthetic data

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A RTRM proposal for multi/many-core platforms and reconfigurable applications

A RTRM proposal for multi/many-core platforms and reconfigur...

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international workshop on Reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Patrick Bellasi Giuseppe Massari William Fornaciari DEI Politecnico di Milano Milano Italy

Emerging multi/many-core architectures, targeting both High Performance computing (HPC) and mobile devices, increase the interest for self-adaptive systems, where both applications and computational resources could smoothly adapt to the changing of the working conditions. In these scenarios, an efficient Run-Time Resource Manager (RTRM) framework can provide a valuable support to identify the optimal tradeoff between the Quality-of-Service (QoS) requirements of the applications and the time varying resources availability. This paper introduces a new approach to the development of a system-wide RTRM featuring: a) a hierarchical and distributed control, b) the exploitation of design-time information, c) a rich multi-objective optimization strategy and d) a portable and modular design based on a set of tunable policies. The framework is already available as an Open Source project, targeting a NUMA architecture and a new generation multi/many-core research platform. First tests show benefits for the execution of parallel applications, the scalability of the proposed multi-objective resources partitioning strategy, and the sustainability of the overheads introduced by the framework.

关键词： Optimization Resource management Computer architecture Quality of service Availability Processor scheduling Embedded systems

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Active Cells: A computing Model for Rapid Construction of On-Chip multi-core systems

Active Cells: A Computing Model for Rapid Construction of On...

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international Conference on Computer and Information Science (ACIS)

作者： Felix Friedrich Ling Liu Jurg Gutknecht Computer Systems Institute ETH Zürich Zurich Switzerland

We present a novel computing model that allows to conveniently construct multi-core systems with different computer architectures, ranging from homogeneous many-core architectures to networks of heterogeneous general purpose processor cores or signal processing engines. A hardware library implemented on Field Programmable Gate Arrays (FPGAs) and a compiler provide a platform for prototyping and constructing distributed systems on a chip. A number of case studies have been carried out to prove the concept conveyed by the computing model.

关键词： Hardware Computational modeling Engines Programming Field programmable gate arrays Computer architecture Vectors

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IDAMC: A many-core Platform with Run-Time Monitoring for Mixed-Criticality

IDAMC: A Many-Core Platform with Run-Time Monitoring for Mix...

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ieee international Symposim on High Assurance systems Engineering

作者： Boris Motruk Jonas Diemer Rainer Buchty Rolf Ernst Mladen Berekovic Institute of Computer and Network Engineering Technische Universitäat Braunschweig Germany Chair of Chip Design for Embedded Computing Technische Universitäat Braunschweig Germany

On a multi- or many-core platform that runs applications of different safety criticality (mixed-criticality), all applications have to be certified to the highest level of criticality, unless they are sufficiently isolated. Isolation enables individual certification of applications and cost-efficient re-certification of single applications after an update. We introduce a parameterizable and synthesizable many-core platform with a fast and scalable monitoring and control mechanism that supports safe sharing of resources. Our contribution is a step towards exploiting the benefits of multi- and many-core platforms for mixed-critical applications.

关键词： Tiles Monitoring Safety Control systems Nickel Network interfaces Delay

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Parallelized benchmark-driven performance evaluation of SMPs and tiled multi-core architectures for embedded systems

Parallelized benchmark-driven performance evaluation of SMPs...

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ieee international Conference on Performance, computing and Communications (IPCCC)

作者： Arslan Munir Ann Gordon-Ross Sanjay Ranka Department of Electrical and Computer Engineering Rice University Houston Texas Department of Electrical and Computer Engineering Department of Computer and Information Science and Engineering University of Florida Gainesville Florida USA

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, there exists a plethora of multi-core architectures and the suitability of these multi-core architectures for different embedded domains (e.g., distributed, real-time, reliability-constrained) requires investigation. Despite the diversity of embedded domains, one of the critical applications in many embedded domains (especially distributed embedded domains) is information fusion. Furthermore, many other applications consist of various kernels, such as Gaussian elimination (used in network coding), that dominate the execution time. In this paper, we evaluate two embedded systems multi-core architectural paradigms: symmetric multiprocessors (SMPs) and tiled multi-core architectures (TMAs). We base our evaluation on a parallelized information fusion application and benchmarks that are used as building blocks in applications for SMPs and TMAs. We compare and analyze the performance of an Intel-based SMP and Tilera's TILEPro64 TMA based on our parallelized benchmarks for the following performance metrics: runtime, speedup, efficiency, cost, scalability, and performance per watt. Results reveal that TMAs are more suitable for applications requiring integer manipulation of data with little communication between the parallelized tasks (e.g., information fusion) whereas SMPs are more suitable for applications with floating point computations and a large amount of communication between processor cores.

关键词： multicore processing Benchmark testing Tiles Embedded systems Measurement Scalability

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FutureGrid education: Using case studies to develop a curriculum for communicating parallel and distributed computing concepts

FutureGrid education: Using case studies to develop a curric...

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1st Conference of the Extreme Science and Engineering Discovery Environment: Bridging from the eXtreme to the Campus and Beyond, XSEDE12

作者： Mitchell, Jerome E. Qiu, Judy Canonio, Massimo Jha, Shantenu Hayden, Linda O'Leary, Barbara Ann Figueiredo, Renato Fox, Geoffrey Indiana University Bloomington IN United States University of Piemonte Orientale Vercelli Italy Lousiana State University Baton Rouge LA United States Elizabeth City State University Elizabeth City NC United States University of Florida Gainesville FL United States

ISBN: (纸本)9781450316026

The shift to parallel computing - including multi-core computer architectures, cloud distributed computing, and generalpurpose GPU programming - leads to fundamental changes in the design of software and systems. As a result, learning parallel, distributed, and cloud techniques in order to allow software to take advantage of the shift toward parallelism is of important significance. To this end, FutureGrid, an experimental testbed for cloud, grids, and high performance computing, provides a resource for anyone to find, share, and discuss modular teaching materials and computational platform supports. This paper presents a series of case studies for experiences in parallel and distributed education using the FutureGrid testbed. Building on previous experiences from courses, workshops, and summer schools associated with FutureGrid, we present a viable solution to developing a curriculum by leveraging collaboration with organizations. Our approach to developing a successful guide stems from the idea of anyone interested in learning parallel and distributing computing can do so with minimum assistance from a domain expert, and it addresses the educational goals and objectives to help meet many challenges, which lie ahead in the discipline. We validate our approach to developing a community driven curriculum by providing use cases and their experiences with the teaching modules. Examples of some use cases include the following: hosting a workshop for faulty members of historically black colleges and universities, courses in distributed and cloud computing at universities, such as Indiana University, Louisiana State University, and the University of Piemonte Orientale. © 2012 ACM.

关键词： Curricula

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Optimizing MPI Communication on multi-GPU systems using CUDA Inter-Process Communication

Optimizing MPI Communication on Multi-GPU Systems using CUDA...

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26th ieee international Parallel and Distributed Processing Symposium (IPDPS) / workshop on High Performance Data Intensive computing

作者： Potluri, S. Wang, H. Bureddy, D. Singh, A. K. Rosales, C. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Texas Adv Comp Ctr Austin TX 78758 USA

ISBN: (纸本)9780769546766

many modern clusters are being equipped with multiple GPUs per node to achieve better compute density and power efficiency. However, moving data in/out of GPUs continues to remain a major performance bottleneck. With CUDA 4.1, NVIDIA has introduced Inter-Process Communication (IPC) to address data movement overheads between processes using different GPUs connected to the same node. State-of-the-art MPI libraries like MVAPICH2 are being modified to allow application developers to use MPI calls directly over GPU device memory. This improves the programmability for application developers by removing the burden of dealing with complex data movement optimizations. In this paper, we propose efficient designs for intra-node MPI communication on multi-GPU nodes, taking advantage of IPC capabilities provided in CUDA. We also demonstrate how MPI one-sided communication semantics can provide better performance and overlap by taking advantage of IPC and the Direct Memory Access (DMA) engine on a GPU. We demonstrate the effectiveness of our designs using microbenchmarks and an application. The proposed designs improve GPU-to-GPU MPI Send/Receive latency for 4MByte messages by 79% and achieve 4 times the bandwidth for the same message size. One-sided communication using Put and Active synchronization shows 74% improvement in latency for 4MByte message, compared to the existing Send/Receive based implementation. Our benchmark using Get and Passive Synchronization demonstrates that true asynchronous progress can be achieved using IPC and the GPU DMA engine. Our designs for two-sided and one-sided communication improve the performance of GPULBM, a CUDA implementation of Lattice Boltzmann Method for multiphase flows, by 16%, compared to the performance using existing designs in MVAPICH2. To the best of our knowledge, this is the first paper to provide a comprehensive solution for MPI two-sided and one-sided GPU-to-GPU communication within a node, using CUDA IPC.

关键词： integrated pollution control Communication Research application developer Line of nodes programmability GRAPPER PICK UP lattice Boltzmann methods

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Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting 5

Full system simulation of many-core heterogeneous SoCs using...

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5th workshop on General-Purpose Computation on Graphics Processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Raghav, Shivani Marongiu, Andrea Pinto, Christian Atienza, David Ruggiero, Martino Benini, Luca ESL - École Polytechnique Fédérale de Lausanne Switzerland DEIS - University of Bologna Bologna Italy

ISBN: (纸本)9781450312332

Modern system-on-chips are evolving towards complex and heterogeneous platforms with general purpose processors coupled with massively parallel manycore accelerator fabrics (e.g. embedded GPUs). Platform developers are looking for efficient full-system simulators capable of simulating complex applications, middleware and operating systems on these heterogeneous targets. Unfortunately current virtual platforms are not able to tackle the complexity and heterogeneity of state-of-the-art SoCs. Software emulators, such as the open-source QEMU project, cope quite well in terms of simulation speed and functional accuracy with homogeneous coarse-grained multi-cores. The main contribution of this paper is the introduction of a novel virtual prototyping technique which exploits the heterogeneous accelerators available in commodity PCs to tackle the heterogeneity challenge in full-SoC system simulation. In a nutshell, our approach makes it possible to partition simulation between the host CPU and GPU. More specifically, QEMU runs on the host CPU and the simulation of manycore accelerators is offloaded, through semi-hosting, to the host GPU. Our experimental results confirm the flexibility and efficiency of our enhanced QEMU environment. © 2012 ACM.

关键词： System-on-chip

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Smart applications on cloud infrastructure

Smart applications on cloud infrastructure

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international workshop on the Maintenance and Evolution of Service-Oriented and Cloud-Based systems (MESOCA)

作者： Marin Litoiu York University Toronto ONT Canada

This presentation introduces an extended cloud computing architecture that satisfies the requirements of several classes of applications. At its core, a cloud is a datacenter that delivers computing resources over the web and allows applications to acquire these resources on demand. However, some classes of applications have special performance and security requirements that cannot be fulfilled by current cloud architectures. Some require short delays and high bandwidth and hence resources close to the client, and an integration of network and computing resources. Some have strict privacy and security requirements and require portions of data and code to run on private infrastructure. We describe a Canadian research project, Smart Applications on Virtual Infrastructures, which proposes a two-tier cloud architecture that satisfies those requirements. The architecture has one core cloud and many smart cloud edges integrated through virtualized networks. Applications are deployed across those components and have the capability to sense their behavior, analyze it, and change it so the requirements are met. We also present an approach to partition an existing web application into edge and core components and discuss the deployment and the runtime support for meeting the security and performance requirements.

关键词： Cloud computing Educational institutions Computer architecture Security Conferences Maintenance engineering

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Optimizing Process-to-core Mappings for Application Level multi-dimensional MPI Communications

Optimizing Process-to-Core Mappings for Application Level Mu...

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ieee international Conference on Cluster computing

作者： Christer Karlsson Teresa Davies Zizhong Chen Colorado School of Mines Golden CO USA University of California Riverside Riverside CA USA

multi-dimensional MPI communications, where MPI communications have to be performed in each dimension of a Cartesian communicator, have been frequently used in many of today's high performance computing applications. While individual MPI collective communications for regular communicators with a one-dimensional linear-ranking of processes have been extensively studied and optimized, little optimizations have been performed for multi-dimensional MPI collective communications on multi-dimensional Cartesian topology. In this paper, we optimize multi-dimensional MPI collective communications for SMP and multi-core systems at the application level. We show that the default Cartesian topology built by the state-of-the-art MPI implementations produce sub-optimal performance for multi-dimensional MPI collective communications. We design optimal process-to-core mapping schemes for Cartesian communicators to minimize the total inter-node communications. The proposed technique improves the performance by up to 80% over the default Cartesian topology built by Cray's MPI implementation MPT 3.1.02 on the world's current second fastest supercomputer Jaguar at Oak Ridge National Laboratory.

关键词： Standards Topology multicore processing Pipelines Arrays Tiles Program processors

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