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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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IWMSE'11 - Proceedings of the 4th international workshop on multicore Software Engineering, Co-located with ICSE 2011

IWMSE'11 - Proceedings of the 4th International Workshop on ...

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4th international workshop on multicore Software Engineering, IWMSE 2011, Co-located with ICSE 2011

The proceedings contain 7 papers. The topics discussed include: mesa: automatic generation of lookup table optimizations;model-based generation of static schedules for safety critical multi-core systems in the avionics domain;improving programmability of heterogeneous many-core systems via explicit platform descriptions;auto-tuning skepU: a multi-backend skeleton programming framework for multi-GPU systems;lightweight parallel accumulators using C++ templates;open language implementation;and how do programs become more concurrent? a story of program transformations.

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Cooperative federated control with application to tracking control

Cooperative federated control with application to tracking c...

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13th ieee international workshop on FTDCS 2011, the 8th international Conference on ATC 2011, the 8th international Conference on UIC 2011 and the 13th ieee international Conference on HPCC 2011

作者： Ferrese, Frank Dong, Qing Bradshaw, Kristen Chaves, Stephen Biswas, Saroj Bai, Li Naval Surface Warfare Center Philadelphia PA United States Temple University Depart. of Electrical and Computing Engineering Philadelphia PA United States

ISBN: (纸本)9780769545387

Large-scale systems refer to systems that consist of many interdependent local systems. Conventional centralized control schemes are not suitable for such large-scale systems due to global dynamic behavior complexity and computational difficulties. This paper introduces a general framework of agent based federated control motivated by the political structure where partially self-governing states are united by a federal government. Likewise, a multi-agent based federated control system is composed of local autonomous subsystems that cooperate to provide an overall system behavior. Formation stability and trajectory tracking control of a group of autonomous agents is designed based on this concept. Decentralized cooperative federated controllers are developed for each individual agent. Simulations show that the overall system is globally asymptotically stable to track a time-varying trajectory with a pre-designated formation for a group of nonlinear dynamic agents. © 2011 ieee.

关键词： Large scale systems

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A high-performance and energy-efficient virtually tagged stack cache architecture for multi-core environments

A high-performance and energy-efficient virtually tagged sta...

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13th ieee international workshop on FTDCS 2011, the 8th international Conference on ATC 2011, the 8th international Conference on UIC 2011 and the 13th ieee international Conference on HPCC 2011

作者： Kang, Suk Chan Nicopoulos, Chrysostomos Lee, Hyunggyu Kim, Jongman School of Electrical and Computer Engineering Georgia Institute of Technology United States Department of Electrical and Computer Engineering University of Cyprus Cyprus

ISBN: (纸本)9780769545387

Virtually tagged caches possess a key attribute that renders them more attractive than Physically Indexed, Physically Tagged (PIPT) caches, they operate natively within the virtual address space, hence taking full advantage of the original intention of a virtual memory implementation: the illusion of a contiguous address space. Consequently, virtually tagged caches eliminate Translation Look-aside Buffer (TLB) references, yielding both energy and performance improvements. On the other hand, virtually tagged caches incur substantial overhead in resolving homonym/synonym issues, which is a fairly complicated process in contemporary multicore environments. In this paper, we aim to markedly alleviate this overhead through the use of a new virtually tagged stack cache design specifically targeting multi-core environments. It will be demonstrated that special level-one virtually tagged stack caches can significantly boost the performance of a system running a heavy, dominating, multi-threaded workload - among other applications - while actually reducing its energy consumption. This scheme is aimed at modern server environments that run a single, dedicated multi-threaded application workload per server. The proposed virtually tagged stack cache for multi-core processors minimizes the overhead incurred in resolving virtual-tag-related artifacts, by granting exclusive access to only one multi-threaded workload at a time. In other words, said virtually tagged cache filters the Virtual Address (VA) spaces and subsequently handles only the stack areas of the selected virtual address space. A cost effective way to implement the proposed stack cache for multi-core systems is also presented, yielding average performance improvements of around 20%. © 2011 ieee.

关键词： Electric power utilization

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An abstraction methodology for the evaluation of multi-core multi-threaded architectures

An abstraction methodology for the evaluation of multi-core ...

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ieee Annual international Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems

作者： Zilan, Ruken Verdú, Javier Garcia, Jorge Nemirovsky, Mario Milito, Rodolfo A. Valero, Mateo Barcelona Spain Barcelona Spain CISCO Systems San Francisco CA United States

ISBN: (纸本)9780769544304

As the evolution of multi-core multi-threaded processors continues, the complexity demanded to perform an extensive trade-off analysis, increases proportionally. Cycle-accurate or trace-driven simulators are too slow to execute the large amount of experiments required to obtain indicative results. To achieve a thorough analysis of the system, software benchmarks or traces are required. In many cases when an analysis is needed most, during the earlier stages of the processor design, benchmarks or traces are not available. Analytical models overcome these limitations but do not provide the fine grain details needed for a deep analysis of these architectures. In this work we present a new methodology to abstract processor architectures, at a level between cycle-accurate and analytical simulators. To apply our methodology we use queueing modeling techniques. Thus, we introduce Q-MAS, a queueing based tool targeting a real chip (the Ultra SPARC T2 processor) and aimed at facilitating the quanti?cation of trade-offs during the design phase of multi-core multi-threaded processor architectures. The results demonstrate that Q-MAS, the tool that we developed, provides accurate results very close to the actual hardware, with a minimal cost of running what-if scenarios. © 2011 ieee.

关键词： Simulators

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Proceedings - 17th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2011

Proceedings - 17th IEEE International Conference on Embedded...

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1st international workshop on Cyber-Physical systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2011

ISBN: (纸本)9780769545028

The proceedings contain 68 papers. The topics discussed include: reducing preemptions and migrations in real-time multiprocessor scheduling algorithms by releasing the fairness;mode transition for online scheduling of adaptive real-time systems on multiprocessors;utilization-controlled task consolidation for power optimization in multi-core real-time systems;a reliability enhancement mechanism for high-assurance MLC flash-based storage systems;limiting worst-case end-to-end latency when traffic increases in a switched avionics network;design and implementation of on-chip adaptive router with predictor for regional congestion;HW resource componentizing for addressing the mega-complexity of cyber-physical systems;Virtual Lock: a smartphone application for personal surveillance using camera sensor networks;dynamic activation timing configuration for product line development;and stabilization of projected image for wearable walking support system using Pico-projector.

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A framework for automated performance tuning and code verification on GPU computing platforms

A framework for automated performance tuning and code verifi...

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25th ieee international Parallel and Distributed Processing Symposium, workshops and Phd Forum, IPDPSW 2011

作者： Gehrke, Allison S. Ra, Ilkyeun Connors, Daniel A. Dept. of Computer Science and Engineering University of Colorado Denver Denver CO 80204 United States Dept. of Electrical Engineering University of Colorado Denver Denver CO 80204 United States

ISBN: (纸本)9780769543857

Emerging multi-core processor designs create a computing paradigm capable of advancing numerous scientific areas, including medicine, data mining, biology, physics, and earth sciences. However, the trends in multi-core hardware technology have advanced far ahead of the advances in software technology and programmer productivity. For the most part, current scientists only leverage multi-core and GPU (Graphical Processing Unit) computing platforms after painstakingly uncovering the inherent task and data-level parallelism in their application. In many cases, the development does not realize the full potential of the parallel hardware. There exists an opportunity to meet the challenges in optimally mapping scientific application domains to multi-core computer systems through the use of compile-time and link-time optimization strategies. We are exploring a code compilation framework that automatically generates and tunes numerical solver codes for optimal performance on graphical processing units. The framework advances computational simulation in kinetic modeling by significantly reducing the execution time of scientific simulations and enabling scientists to compare results to previous models and to extend, modify, and test new models without code changes. © 2011 ieee.

关键词： Graphics processing unit

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Efficient Implementation of Thermal-aware Scheduler on a Quad-core Processor

Efficient Implementation of Thermal-aware Scheduler on a Qua...

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Int Joint Conference of 10th ieee Int Conf on Trust, Security and Privacy in computing and Communications (TrustCom) / 8th ieee Int Conf on Embedded Software and systems (ICESS) / 6th Int Conf on Frontier of Computer Science and Technology (FCST)

作者： Yin, Xiaojing Zhu, Yongxin Xia, Liang Ye, Jingwei Huang, Tian Fu, Yuzhuo Qiu, Meikang Shanghai Jiao Tong Univ Sch Microelect Shanghai Peoples R China Univ Kentucky Dept Elect & Comp Engn Lexington KY USA

ISBN: (纸本)9780769546001

Due to power wall and slow performance improvement in a single core micro-architecture, multiple even many cores based processors rose as the main stream processor. Nevertheless, thermal threats regarding reliability and lifetime of processors are still among the major concerns which received much attention in terms of algorithms and hardware design to reduce processor temperature and keep application performance in recent years. In this paper, we propose and implement a thermal-aware Round-Robin scheduling algorithm for process migration in the Linux environment on a quad-core processor. Bearing designer's goals in mind, such as performance, load-balancing, and reliability, we managed to achieve much bigger temperature fall than previous results of Round-Robin scheduler on a dual-core processor as well as baseline Linux scheduler on a quad-core processor. Moreover, the performance loss due to scheduling overhead is modest in our approach. Our results indicate that thermal-aware scheduling is a valid approach to tackling thermal issues on multi-core processors. There will be increasing demand for thermal-aware scheduling as the number of cores on a single processor increases.

关键词： Scheduling

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High-performance computing model for 3D camera system

High-performance computing model for 3D camera system

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2011 ieee international Conference on Robotics and Biomimetics, ROBIO 2011

作者： Ta, Hong-Nam Lee, Sukhan School of Information and Communication Enginerring Sungkyunkwan University Suwon Korea Republic of Department of Interaction Science Sungkyunkwan University Seoul Korea Republic of

ISBN: (纸本)9781457721373

Computer vision and sensing systems have been widely applied to industry, and this includes robotics, an area requiring real-time applications. However, robust and high-accuracy systems are usually time-consuming, but high-performance devises can speed up the systems. many applications use GPU (Graphic Processing Unit) for faster computation. The greatest advantages of the GPU system include high-memory bandwidth and flexibility and ease of programming. However, this method requires transferring data between host (computer) and device (graphic card). Moreover, it only supports data parallelism or overlap copy data and kernel execution. multi-core CPU offers another approach for improving system performance. OpenMP, an API that supports multi-core CPU programming strongly, offers flexibility and simple programming using compiler directives items;in particular, the computation can be done without transferring data to the device and full task parallel execution. However, multi-core CPU is limited to several cores. Combining the advantages of GPU and multi-core CPU optimizes system performance. This paper proposes a novel high-performance computing model using combination architecture of GPU and multi-core CPU to obtain a two parallel layer system including data parallel and task parallel models. The result implements a highly accurate 3D reconstruction application using the improved HOC structured light coding algorithm. The experimental results of the proposed model reveal a speed 20 times faster than the original implementation in the single CPU. © 2011 ieee.

关键词： Graphics processing unit

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HIGH PERFORMANCE computing OF LINE OF SIGHT VIEWSHED

HIGH PERFORMANCE COMPUTING OF LINE OF SIGHT VIEWSHED

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ieee international Conference on multimedia and Expo (ICME)

作者： Lu, Ligang Paulovicks, Brent Perrone, Michael Sheinin, Vedim IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9781612843490

In this paper we present our recent research and development work for multicore computing of Line of Sight (LoS) on the Cell Broadband Engine (CBE) processors. LoS can be found in many applications where real-time high performance computing is required. We will describe an efficient LoS multi-core parallel computing algorithm, including the data partition and computation load allocation strategies to fully utilize the CBE's computational resources for efficient LoS viewshed parallel computing. In addition, we will also illustrate a successive fast transpose algorithm to prepare the input data for efficient Single-Instruction-multiple-Data (SIMD) operations. Furthermore, we describe the data input and output (I/O) management scheme to reduce the (I/O) latency in Direct-Memory-Access (DMA) data fetching and storing operations. The performance evaluation of our LoS viewshed computing scheme over an area of interest (AOI) with more than 4.19 million points has shown that our parallel computing algorithm on CBE takes less than 25.5 ms, which is several orders of magnitude faster than the available commercial systems.

关键词： Line of Sight Viewshed Parallel computing

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Scalable multi-core simulation using parallel dynamic binary translation

Scalable multi-core simulation using parallel dynamic binary...

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2011 11th international Conference on Embedded Computer systems: Architectures, Modeling and Simulation, IC-SAMOS 2011

作者： Almer, Oscar Böhm, Igor Von Koch, Tobias Edler Franke, Björn Kyle, Stephen Seeker, Volker Thompson, Christopher Topham, Nigel Institute for Computing Systems Architecture University of Edinburgh United Kingdom Software Engineering for Embedded Systems Group Technical University Berlin Germany

ISBN: (纸本)9781457708008

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc multiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core 86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead. © 2011 ieee.

关键词： Embedded systems

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