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An efficient solution for aligning huge DNA sequences

An efficient solution for aligning huge DNA sequences

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2011 international Conference on Computer Engineering and systems, ICCES'2011

作者： Hosny, Ahmad M. Shedeed, Howida A. Hussein, Ashraf S. Tolba, Mohamed F. Department of Scientific Computing Faculty of Computer and Information Sciences Ain Shams University Abbassia Cairo 11566 Egypt

ISBN: (纸本)9781457701283

Recently, many parallel solutions were proposed in order to accelerate the exact methods for optimal alignment of DNA sequences. However, most of these solutions calculate only the alignment similarity score without finding the actual alignment. This paper presents an efficient solution to find the optimal alignment of the huge DNA sequences. This solution releases the condition of the sequence size to be in megabyte-scale instead of few kilobytes. The fundamental innovation in this work is developing an efficient, linear space complexity, parallel solution to achieve the optimum alignment with relatively good performance. The shared memory parallel architecture is the focus of this work therefore;we have considered off-the-shelf systems like multi-core CPUs as well as advanced shared memory platforms. Experimental results show that the proposed solution achieved high records compared to other solutions that targeted the same goal with less hardware requirements. © 2011 ieee.

关键词： DNA sequences

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Proceedings - 6th international Symposium on Parallel computing in Electrical Engineering, PARELEC 2011

Proceedings - 6th International Symposium on Parallel Comput...

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6th international Symposium on Parallel computing in Electrical Engineering, PARELEC 2011

ISBN: (纸本)9780769543970

The proceedings contain 33 papers. The topics discussed include: static average case analysis fork-join framework programs based on MOQA method;parallelizing a coarse grain graph search problem based upon LDPC codes on a supercomputer;an approach towards automation firmware modeling for an exploration and evaluation of efficient parallelization alternatives;communication on the fly for hierarchical systems of chip multi-processors;optimizing heterogeneous 3D networks-on-chip;a dynamic core grouping approach to improve raw architecture many-core processor performance;event-driven scheduling for parallel stream processing;optimal placement of the wind generators in the medium voltage power grid;potential of general purpose graphic processing unit for energy management system;goal-oriented adaptive workload management for irregular applications;and distributed program control flow and behavior governed by global states monitoring.

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Reducing complexity in H.264/AVC motion estimation by using a GPU

Reducing complexity in H.264/AVC motion estimation by using ...

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3rd ieee international workshop on multimedia Signal Processing, MMSP 2011

作者： Rodríguez-Sánchez, R. Martínez, J.L. Fernández-Escribano, G. Claver, J.M. Sánchez, J.L. Instituto de Investigación en Informática de Albacete Universidad de Castilla-La Mancha Campus Universitario 02071 Albacete Spain Architecture and Technology of Computing Systems Group Complutense University Ciudad Universitaria 28040 Madrid Spain Dpto. de Informática Universidad de Valencia Avd. Vicente Andrés Estellés s/n 46100 Burjassot Spain

ISBN: (纸本)9781457714337

H.264/AVC applies a complex mode decision technique that has high computational complexity in order to reduce the temporal redundancies of video sequences. Several algorithms have been proposed in the literature in recent years with the aim of accelerating this part of the encoding process. Recently, with the emergence of many-core processors or accelerators, a new approach can be adopted for reducing the complexity of the H.264/AVC encoding algorithm. This paper focuses on reducing the inter prediction complexity adopted in H.264/AVC and proposes a GPU-based implementation using CUDA. Experimental results show that the proposed approach reduces the complexity by as much as 99% (100x of speedup) while maintaining the coding efficiency. © 2011 ieee.

关键词： Graphics processing unit

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Design of multi-channel wireless NoC to improve on-chip communication capacity 11

Design of multi-channel wireless NoC to improve on-chip comm...

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Proceedings of the Fifth ACM/ieee international Symposium on Networks-on-Chip

作者： Zhao, Dan Wang, Yi Li, Jian Kikkawa, Takamaro Center for Advanced Computer Studies Univ. of Louisiana at Lafayette Lafayette LA 70503 United States IBM Research - Austin 11501 Burnet Road Austin TX 78758 United States Research Center for Nanodevices Hiroshima University Hiroshima 739-8527 Japan

ISBN: (纸本)9781450307208

many-core chip design has become a popular means to sustain the exponential growth of chip-level computing performance. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. In the meantime, the introduction of Ultra-Wideband (UWB) interconnect brings in the new opportunity for giga-bps communication bandwidth, milliwatts communication power, and low cost implementation for millimeter range on-chip communication for future chip generations. In this paper, we study multi-channel wireless Network-on-Chip (McWiNoC) with ultra-short RF/wireless links for multi-hop communication. We first present the benefit of high bandwidth, low latency and flexible topology configurations provided by this new on-chip interconnection network. We then propose a distributed and deadlock-free location based routing scheme. We further design an efficient channel arbitration scheme to grant multi-channel access. With a few representative synthetic traffic patterns and SPLASH-II benchmarks, we demonstrate that McWiNoC can achieve 23.3% average performance improvement and 65.3% average end-to-end latency reduction over a baseline NoC of 8 x 8 metal wired mesh. © 2011 ACM.

关键词： Network-on-chip

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Scalable multi-cache simulation using GPUs

Scalable multi-cache simulation using GPUs

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ieee Annual international Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems

作者： Moeng, Michael Cho, Sangyeun Melhem, Rami Department of Computer Science University of Pittsburgh United States

ISBN: (纸本)9780769544304

Software simulation is the primary tool used for evaluation of processor design. Simulation offers better accuracy than analytical models and is an important evaluation step before actually fabricating a chip. Unfortunately, simulator speeds are slow - a conventional cycle-accurate simulator will be unable to keep up with increasing core counts in modern processor design. Parallel simulation is one method for improving simulation speeds. Two major areas of parallel simulation research are multithreaded simulators and FPGAs as simulation accelerators. multithreaded simulators can only extract coarse-grained parallelism and must sacrifice accuracy in order to scale well. FPGA-based simulators can extract fine-grained parallelism, but are expensive and difficult to program. We propose using GPUs for architectural simulation, which can take advantage of a high degree of fine-grained parallelism. In addition, they are inexpensive and easier to program compared to FPGAs. To demonstrate our ideas, we implement a trace-driven many-cache simulator using NVIDIA's CUDA toolkit. GPU-accelerated cache simulation displays remarkable scaling with number of simulated caches when compared to serial CPU-only simulation. © 2011 ieee.

关键词： Field programmable gate arrays (FPGA)

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Pre-computing function results in multi-core and many-core processors

Pre-computing function results in multi-core and many-core p...

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2011 international Conference on Parallel Processing workshops, ICPPW 2011

作者： Herrmann, Edward C. Janga, Prudhvi Wilsey, Philip A. Experimental Computing Laboratory School of Electronic and Computing Systems PO Box 210030 Cincinnati OH 45221-0030 United States

ISBN: (纸本)9780769545110

In recent years, the number of hardware supported threads in desktop processors has increased dramatically. All but the very lowest cost netbooks and embedded processors now have at least dual cores and soon systems supporting upwards of 8 to 16 hardware threads are likely to be commonplace. Unfortunately, it will be difficult to take full advantage of the parallelism emerging processors will be able to provide. To help address this issue, we are investigating mechanisms to pre-compute function results in separate threads running concurrently with the main program thread. The concurrent threads are forked automatically and without program modification. A critical component for the success of this idea is an ability to build a background thread that can pre-compute usable results in some effective manner. For some support functions (dynamic memory) exact arguments predictions for the function pre-computation are not necessary, for others (trigonometric functions) they are. In work with dynamic memory, we are able to pre-compute memory blocks and show modest speedup: saving approximately 25% of the dynamic memory costs. In studies with predicting argument values to trigonometric functions, we show that learning algorithms are able to successfully predict the next argument values approximately 44% of the time. © 2011 ieee.

关键词： Functions

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Engineering multi-tenant Software-as-a-Service systems

Engineering multi-tenant Software-as-a-Service systems

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3rd international workshop on Principles of Engineering Service-Oriented systems, PESOS 2011, Co-located with ICSE 2011

作者： Sengupta, Bikram Roychoudhury, Abhik IBM Research Bangalore India School of Computing National Univ. of Singapore Singapore

ISBN: (纸本)9781450305914

Increasingly, Software-as-a-Service (SaaS) is becoming a dominant mechanism for the consumption of software by end users. From a vendor's perspective, the benefits of SaaS arise from leveraging economies of scale, by serving a large number of customers ("tenants") through a shared instance of a centrally hosted software service. Consequently, a SaaS provider would, in general, try to drive commonality amongst the requirements of different tenants, and at best, offer a fixed set of customization options. However, many tenants would also come with custom requirements, which may be a pre-requisite for them to adopt the SaaS system. These requirements should then be addressed by evolving the SaaS system in a controlled manner, while still supporting the needs of existing tenants. This need to balance tenant variability and commonality, and to optimize on development and testing effort, can make the evolution of multi-tenant SaaS systems an interesting engineering challenge;this has strong economic undertones as well, given the "pay-per-use" subscription model of SaaS, and the cost of incremental development and maintenance to cater to new tenant needs. In this paper, we outline a set of research issues in the design, testing and maintenance of multi-tenant SaaS systems, and highlight some of the interesting optimization questions that arise in the process. Presenting specific technical solutions is beyond the scope of this paper - instead, our goal is to help shape a research agenda for multi-tenant SaaS that can provide stimulus for further investigation into this area by the software and service engineering research community. © 2011 ACM.

关键词： Semantics

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multi-science applications with single codebase - GAMER - for massively parallel architectures

Multi-science applications with single codebase - GAMER - fo...

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2011 international Conference for High Performance computing, Networking, Storage and Analysis, SC11

作者： Shukla, Hemant Schive, Hsi-Yu Woo, Tak-Pong Chiueh, Tzihong Lawrence Berkeley National Laboratory 1 Cyclotron Road Berkeley United States Department of Physics National Taiwan University 106 Taipe Taiwan Department of Physics Soochow University 106 Taipei Taiwan

ISBN: (纸本)9781450307710

The growing need for power efficient extreme-scale high-performance computing (HPC) coupled with plateauing clock-speeds is driving the emergence of massively parallel compute architectures. Tens to many hundreds of cores are increasingly made available as compute units, either as the integral part of the main processor or as coprocessors designed for handling massively parallel workloads. In the case of many-core graphics processing units (GPUs) hundreds of SIMD cores primarily designed for image and video rendering are used for high-performance scientific computations. The new architectures typically offer ANSI standard programming models such as CUDA (NVIDIA) and OpenCL. However, the wide-ranging adoption of these parallel architectures is steeped in difficult learning curve and requires reengineering of existing applications that mostly leads to expensive and error prone code rewrites without prior guarantee and knowledge of any speedups. Broad range of complex scientific applications across many domains use common algorithms and techniques, such as adaptive mesh refinements (AMR), advanced hydrodynamics partial differential equation (PDE) solvers, Poisson-Gravity solvers etc, that have demonstrably performed highly efficiently on GPU based systems. Taking advantage of the commonalities, we use GPU-aware AMR code, GAMER [1], to examine the unique approach of solving multi-science problems in astrophysics, hydrodynamics and particle physics with single codebase. We demonstrate significant speedups in disparate class of scientific applications on 3 separate clusters, viz., Dirac, Laohu and Mole 8.5. By extensively reusing the extendable single codebase we mitigate the impediments of significant code rewrites. We also collect performance and energy consumption benchmark metrics on 50-nodes NVIDIA C2050 GPU and Intel 8-core Nehalem CPU on Dirac cluster at the National Energy Research Supercomputing Center (NERSC). In addition, we propose a strategy and framework for

关键词： Graphics processing unit

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Flexible development of dense linear algebra algorithms on massively parallel architectures with DPLASMA

Flexible development of dense linear algebra algorithms on m...

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25th ieee international Parallel and Distributed Processing Symposium, workshops and Phd Forum, IPDPSW 2011

作者： Bosilca, George Bouteiller, Aurelien Danalis, Anthony Faverge, Mathieu Haidar, Azzam Herault, Thomas Kurzak, Jakub Langou, Julien Lemarinier, Pierre Ltaief, Hatem Luszczek, Piotr YarKhan, Asim Dongarra, Jack University of Tennessee Innovative Computing Laboratory United States Oak Ridge National Laboratory United States University Paris-XI France University of Colorado Denver United States

ISBN: (纸本)9780769543857

We present a method for developing dense linear algebra algorithms that seamlessly scales to thousands of cores. It can be done with our project called DPLASMA (Distributed PLASMA) that uses a novel generic distributed Direct Acyclic Graph Engine (DAGuE). The engine has been designed for high performance computing and thus it enables scaling of tile algorithms, originating in PLASMA, on large distributed memory systems. The underlying DAGuE framework has many appealing features when considering distributed-memory platforms with heterogeneous multicore nodes: DAG representation that is independent of the problem-size, automatic extraction of the communication from the dependencies, overlapping of communication and computation, task prioritization, and architecture-aware scheduling and management of tasks. The originality of this engine lies in its capacity to translate a sequential code with nested-loops into a concise and synthetic format which can then be interpreted and executed in a distributed environment. We present three common dense linear algebra algorithms from PLASMA (Parallel Linear Algebra for Scalable multi-core Architectures), namely: Cholesky, LU, and QR factorizations, to investigate their data driven expression and execution in a distributed system. We demonstrate through experimental results on the Cray XT5 Kraken system that our DAG-based approach has the potential to achieve sizable fraction of peak performance which is characteristic of the state-of-the-art distributed numerical software on current and emerging architectures. © 2011 ieee.

关键词： Linear systems

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Emerging applications for multi/many-core processors

Emerging applications for multi/many-core processors

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ieee international Symposium on Circuits and systems (ISCAS)

作者： Victor W. Lee Yen-Kuang Chen J. Chhugani C. Kim D. Kim C.J. Hughes N. Rajagopalan Satish M. Smelyanskiy P. Dubey Parallel Computing Lab Intel Labs Intel Corporation Santa Clara California USA Parallel Computing Lab Intel Labs Intel Corporation Santa Clara California USA

There has always been a strong relationship between computer applications and computer architectures. Advances in computer architecture enable new usage models; new usage models challenge new architectures. For many decades, the interplays between applications and architectures have resulted in significant progress in the computer technologies. Recently, the computer industry adopts the multi/many-core architecture for better performance, energy efficiency and reliability. This industry-wide movement towards multi/many-core architectures opens up many opportunities for developing new classes of applications. This paper uses a few emerging applications as examples to illustrate the interplay between applications and architecture. It further discusses the key characteristics of emerging applications and how multi/many-core architecture addresses the needs of the new applications. The paper closes with recommendations for new application developers to allow better utilization of new multi/many-core processors.

关键词： Computer architecture Synchronization Data models Computers Parallel processing Bandwidth Program processors

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