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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 976 条记录，以下是721-730 订阅

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The convergence of HPC and embedded systems in our heterogeneous computing future

The convergence of HPC and embedded systems in our heterogen...

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ieee international Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： David Kaeli David Akodes Department of Electrical and Computer Engineering Northeastern University Boston MA USA

Recently we have seen two exciting trends that have been flooding the market: 1) the movement of graphics processing units into mainstream general-purpose platforms, and 2) the movement of multi-core embedded systems into tablet computing and smartphone spaces. These trends are forcing application developers to rethink how they are going to best utilize these many-core and multi-core heterogeneous platforms to provide new levels of cost/performance/power in a range of emerging application domains. A key driver in this movement is the recognition that traditional graphics devices can play a larger role in computation than was ever considered before. The high performance computing community has fueled this development, and has demonstrated that Graphics Processing Units can be utilized in a range of general purpose and embedded systems applications. By making this class of devices programmable, a new era in heterogeneous computing has begun. We will discuss some of the catalysts behind these changes, and consider what lies ahead in the future for heterogeneous computing. We will touch on current trends in computing core architectures and programming frameworks, as well as discuss what new classes of applications will be possible as we arrive at the intersection of these two vastly different computing domains.

关键词： Graphics processing unit Embedded systems Performance evaluation Convergence Media Computer architecture Programming environments

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Evaluation of the Energy Performance of Dense Linear Algebra Kernels on multi-core and many-core Processors

Evaluation of the Energy Performance of Dense Linear Algebra...

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ieee international Symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Maribel Castillo Manel Dolz Juan C. Fern´ndez Rafael Mayo Enrique S. Quintana-Orti Vicente Roca Depto. de Ingeniería y Ciencia de Computadores Universidad Jaume I Castellón Spain

We evaluate the power consumption of three key kernels from several tuned dense linear algebra libraries on three general-purpose multi-core processors and a graphics processor, representative of the state-of-the-art in computing technology. The results of this study provide basic insights on the energy scalability of multi- and many-core designs and multi-threaded software as the building blocks of future EXAFLOPS systems.

关键词： Kernel Graphics processing unit Libraries Linear algebra multicore processing Hardware

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A Micro Threading Based Concurrency Model for Parallel computing

A Micro Threading Based Concurrency Model for Parallel Compu...

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ieee international Symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Qiang Yang C.R. Jesshope Jian Fu Institute of informatics University of Amsterdam Netherlands

The continuing launch of various multi-core processors popularizes parallel computing of gaining higher performance, however, it also exerts pressures on software developers concerning how to make full use of the multiplicity of resources to get the required benefits due to high coupling of parallel programs to specified hardware. In this paper, we propose SVP, a micro-threading based concurrency model, as an alternative to efficiently program on and manage multi-core, even many-core systems. SVP isolates programming from executing resources so that programs are compiled once and execute regardless of actual cores available, not only numbers, but also properties to achieve scalable speedup. Such lower coupling, better flexibility and portability in parallel applications are highly appreciated. To investigate SVP, tool chains and a fully functional software simulator of an SVP many-core chip have been developed for test and verification. Using this infra-structure, we are able to show how much we can gain from SVP and how speedup is scaled by running the same binary code of Game of Life on a scalable many-core platform.

关键词： Instruction sets Concurrent computing Programming Synchronization Resource management Hardware

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Parallax - A New Operating System Prototype Demonstrating Service Scaling and Service Self-Repair in multi-core Servers

Parallax - A New Operating System Prototype Demonstrating Se...

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ieee international workshop on Enabling Technologies: Infrastructure for Collaborative Enterprises (WET ICE)

作者： Rao Mikkilineni Ian Seyler Kawa Objects Inc. USA Return Infinity Canada

This paper describes a prototype demonstrating a new operating system (called Parallax) for the new generation many-core servers. The operating system is designed to address scaling, resource monitoring, dynamic configuration, and self-repair of many-core chip based servers to support distributed computational tasks. The operating system is implemented in assembler language for efficiency and supports C/C++ programming interfaces for high-level programming. The Parallax operating system is based on the DIME network computing model supporting distributed network-centric computing architecture. A parallel signaling network overlay over a network of von Neumann stored program control (SPC) computing nodes is utilized to implement dynamic fault, configuration, accounting, performance, and security management of both the nodes and the network based on business priorities, workload variations and latency constraints.

关键词： Servers Mice Hardware Security Kernel Computer architecture

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Fast and accurate thermal simulation and modelling of workloads of many-core processors

Fast and accurate thermal simulation and modelling of worklo...

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international workshop on Thermal Investigation of ICs and systems (THERMINIC)

作者： B. Wojciechowski K. S. Berezowski Piotr Patronik Janusz Biernat Institute of Computer Engineering Control and Robotics Wroclaw University of Technology Wroclaw Poland

In this work we use the Fourier expansion to characterize and model many-core processor workloads for the purpose of computing accurate predictions of individual core thermal statuses. We demonstrate, that even if the workload is modeled with only a few components of its Fourier expansion, not only we obtain improved accuracy of aggregate performance measures like throughput or power consumption, but also we obtain highly accurate thermal profiles of individual cores. In this work we present the measurement and simulation results and accuracy analysis of our proposed approach. Our experiments show that assuming average activity of threads in a multi-threaded workload run on a many-core processor may lead to as much as 25% error in the estimation of the overall throughput of the system, and even larger discrepancies in the estimates of individual core's temperature traces, while applying even a few-component Fourier expansion of the benchmark traces reduce these errors by large margins.

关键词： Computational modeling Microprocessors Instruction sets Benchmark testing Approximation methods Mathematical model

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Thermal-Aware Scheduling of Critical Applications Using Job Migration and Power-Gating on multi-core Chips

Thermal-Aware Scheduling of Critical Applications Using Job ...

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ieee international Conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Buyoung Yun Kang G. Shin Shige Wang EECS Department University of Michigan Ann Arbor MI USA General Motors Global R& D Warren MI USA

multi-core System-on-Chip (SoC) has become a popular execution platform for many embedded real-time systems. As CMOS transistors continue to shrink down to the nanoscale regime, it becomes more susceptible to various reliability threats mainly due to thermal hotspots. To improve the reliability of embedded real-time systems, dynamic thermal management (DTM) is required for mission/safety- critical applications running on a multi-core chip to avoid possible thermal hazards while meeting the applications' timing constraints. In this paper, we propose an efficient runtime thermal- aware scheduler (TAS) using job-migration and power-gating techniques to avoid the thermal hotspots on a multi-core chip. Before runtime, the TAS distributes the periodic real-time tasks to cores using the tasks' execution profiles to balance the utilization of functional units on the chip. At runtime, the TAS periodically monitors the core temperatures and triggers one of the following pre-defined thermal management schemes depending on the level of the measured core temperature: (i) migrating jobs running on hot cores to other cooler cores to reduce the workloads on the hot cores, or (ii) turning off hot cores for a certain period of time to cool them down. All tasks' timing constraints are guaranteed during the job migrations and powering cores on/off. Our in-depth evaluation has shown that the proposed TAS can effectively minimize the thermal hotspots on a multi-core chip without violating any application timing constraint.

关键词： Runtime multicore processing Temperature measurement Thermal management Timing Temperature sensors Real time systems

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Energy-Aware Partitioned Fixed-Priority Scheduling for Chip multi-processors

Energy-Aware Partitioned Fixed-Priority Scheduling for Chip ...

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ieee international Conference on Embedded and Real-Time computing systems and Applications (RTCSA)

作者： Arvind Kandhalu Junsung Kim Karthik Lakshmanan Ragunathan Rajkumar Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh USA Carnegie Mellon University Pittsburgh PA US

Energy management is becoming an increasingly important problem in application domains ranging from embedded devices to data centers. In many such systems, multi-core processors are projected as a promising technology to achieve improved performance with a lower power envelope. Managing the application power consumption under timing constraints poses significant challenges in these emerging platforms. In this paper, we study the energy-efficient scheduling of periodic real time tasks with implicit deadlines on chip multi-core processors (CMPs). We specifically consider processors with a single voltage and clock frequency domain, such as the state-of-the-art embedded multi-core NVIDIA Tegra 2processor and enterprise-class processors such as Intel'sItanium 2, i5, i7 and IBM's Power 6 and Power 7series. The major contributions of this work are (i)we prove that Worst-Fit-Decreasing (WFD) task partitioning when Rate-Monotonic Scheduling (RMS) is used has an approximation ratio of 1.71 for the problem of minimizing the schedulable operating frequency with partitioned fixed-priority scheduling, (ii) we illustrate the major shortcoming of WFD with RMS resulting from not considering task periods during allocation, and(iii) we propose a Single-clock domain multi-processor Frequency Assignment Algorithm (SFAA) that determines a globally energy-efficient frequency while including task period relationships. Our evaluation results show that SFAA provides significant energy gains when compared to WFD. In fact SFAA is shown to save up to 55% more power compared to WFD for an octa-core processor.

关键词： Program processors Partitioning algorithms multicore processing Real time systems Processor scheduling Clocks Energy consumption

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Leveraging on-chip DRAM stacking in an embedded 3D multi-core DSP system

Leveraging on-chip DRAM stacking in an embedded 3D multi-cor...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Tao Zhang Po-Yang Hsu Wei-Heng Lo Shau-Yin Tseng Yi-Ta Wu Chuan-Nan Liu Jen-Chieh Yeh Tingting Hwang Yuan Xie Department of Computer Science and Engineering The Pennsylvania State University PA USA Department of Computer Science National Tsing Hua University Hsinchu Taiwan Industrial Technology Research Institute (ITRI) Hsinchu Taiwan

Embedded multi-core systems are gaining popularity for many embedded applications. Compared to the multi-core design for general purpose high performance computing, the memory design for an embedded multi-core processor should be customized and adapt to embedded application's characteristics, because it usually has significant impact on the system performance. In this paper, we study a 3D embedded multi-core DSP processor called 3D-iSPA, which is targeted for multimedia applications with two unique design features and leverages 3D DRAM stacking to improve performance. many memory controller and wider memory data bus are proposed to make better use of the vertical through-silicon-via (TSV). The experimental results shows that duplicating memory controller can provide 10X speedup. The pure wider memory bus, however, has weak impact on the performance due to the limitation of on-chip interconnect.

关键词： Random access memory Three dimensional displays multimedia communication Stacking Vehicles Through-silicon vias Encoding

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High-performance computing model for 3D camera system

High-performance computing model for 3D camera system

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ieee international Conference on Robotics and Biomimetics

作者： Hong-Nam Ta Sukhan Lee School of Information and Communication Engineering Sungkyunkwan University Suwon South Korea Department of Interaction Science Sungkyunkwan University Suwon South Korea

ISBN: (纸本)9781457721366

Computer vision and sensing systems have been widely applied to industry, and this includes robotics, an area requiring real-time applications. However, robust and high-accuracy systems are usually time-consuming, but high-performance devises can speed up the systems. many applications use GPU (Graphic Processing Unit) for faster computation. The greatest advantages of the GPU system include high-memory bandwidth and flexibility and ease of programming. However, this method requires transferring data between host (computer) and device (graphic card). Moreover, it only supports data parallelism or overlap copy data and kernel execution. multi-core CPU offers another approach for improving system performance. OpenMP, an API that supports multi-core CPU programming strongly, offers flexibility and simple programming using compiler directives items; in particular, the computation can be done without transferring data to the device and full task parallel execution. However, multi-core CPU is limited to several cores. Combining the advantages of GPU and multi-core CPU optimizes system performance. This paper proposes a novel high-performance computing model using combination architecture of GPU and multi-core CPU to obtain a two parallel layer system including data parallel and task parallel models. The result implements a highly accurate 3D reconstruction application using the improved HOC structured light coding algorithm. The experimental results of the proposed model reveal a speed 20 times faster than the original implementation in the single CPU.

关键词： Graphics processing unit Computational modeling Instruction sets Encoding Computer architecture Estimation Performance evaluation

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A Framework for Automated Performance Tuning and Code Verification on GPU computing Platforms

A Framework for Automated Performance Tuning and Code Verifi...

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ieee international Symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Allison S. Gehrke Ilkyeun Ra Daniel A. Connors Department of Computer Science and Engineering and Department of Electrical Engineering University of Colorado Denver Denver CO USA

Emerging multi-core processor designs create a computing paradigm capable of advancing numerous scientific areas, including medicine, data mining, biology, physics, and earth sciences. However, the trends in multi-core hardware technology have advanced far ahead of the advances in software technology and programmer productivity. For the most part, current scientists only leverage multi-core and GPU (Graphical Processing Unit) computing platforms after painstakingly uncovering the inherent task and data-level parallelism in their application. In many cases, the development does not realize the full potential of the parallel hardware. There exists an opportunity to meet the challenges in optimally mapping scientific application domains to multi-core computer systems through the use of compile-time and link-time optimization strategies. We are exploring a code compilation framework that automatically generates and tunes numerical solver codes for optimal performance on graphical processing units. The framework advances computational simulation in kinetic modeling by significantly reducing the execution time of scientific simulations and enabling scientists to compare results to previous models and to extend, modify, and test new models without code changes.

关键词： Computational modeling Numerical models Graphics processing unit Kinetic theory Optimization Registers Data models

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