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Automatic Parallelization of Simulink Applications

Automatic Parallelization of Simulink Applications

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8th international Symposium on Code Generation and Optimization

作者： Canedo, Arquimedes Yoshizawa, Takeo Komatsu, Hideaki IBM Res Tokyo Tokyo Japan

ISBN: (纸本)9781605586359

The parallelization of Simulink applications is currently a responsibility of the system designer and the superscalar execution of the processors. State-of-the-art Simulink compilers excel at producing reliable and production-quality embedded code, but fail to exploit the natural concurrency available in the programs and to effectively use modern multi-core architectures. The reason may be that many Simulink applications are replete with loop-carried dependencies that inhibit most parallel computing techniques and compiler transformations. In this paper, we introduce the concept of strands that allow the data dependencies to be broken while preserving the original semantics of the Simulink program. Our fully automatic compiler transformations create a concurrent representation of the program, and thread-level parallelism for multi-core systems is planned and orchestrated. To improve single processor performance, we also exploit fine grain (equation-level) parallelism by level-order scheduling inside each thread. Our strand transformation has been implemented as an automatic transformation in a proprietary compiler and with a realistic aeronautic model executed in two processors leads to an up to 1.98 times speedup over uniprocessor execution, while the existing manual parallelization method achieves a 1.75 times speedup.

关键词： Strands Simulink multi-core compilers coarse grain dataflow automatic parallelization equation-level parallelism

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Physical layer network isolation in multi-tenant clouds

Physical layer network isolation in multi-tenant clouds

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workshop on Sharing Field Data and Experiment Measurements on Resilience of Distributed computing systems

作者： Brassil, Jack HP Laboratories Princeton NJ United States

ISBN: (纸本)9780769540795

The isolation capabilities provided by conventional enterprise data center technology are inadequate for many clients of multi-tenant storage or compute clouds. To address this deficiency we propose a cloud architecture which relies on strategic deployment of physical layer network isolation. We show how improved client isolation can be realized with 'color gapping' using existing Coarse Wavelength Division multiplexing technologies, and demonstrate how in some settings isolation can be visually verified by clients. To address the challenging problem of isolating multiple clients' Virtual Machines within a single physical server, we introduce a novel application of distributed bridging based on Virtual Ethernet Port Aggregators. © 2010 ieee.

关键词： Network layers

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StageWeb: Interweaving Pipeline Stages into a Wearout and Variation Tolerant CMP Fabric

StageWeb: Interweaving Pipeline Stages into a Wearout and Va...

引用

ieee/IFIP international Conference on Dependable systems and Networks (DSN)

作者： Gupta, Shantanu Ansari, Amin Feng, Shuguang Mahlke, Scott Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9781424475018

Manufacture-time process variation and life-time failure projections have become a major industry concern. Consequently, fault tolerance, historically of interest only for mission-critical systems, is now gaining attention in the mainstream computing space. Traditionally reliability issues have been addressed at a coarse granularity, e.g., by disabling faulty cores in chip multiprocessors. However, this is not scalable to higher failure rates. In this paper, we propose StageWeb, a fine-grained wearout and variation tolerance solution, that employs a reconfigurable web of replicated processor pipeline stages to construct dependable many-core chips. The interconnection flexibility of Stage Web simultaneously tackles wearout failures (by isolating broken stages) and process variation (by selectively disabling slower stages). Our experiments show that through its wearout tolerance, a StageWeb chip performs up to 70% more cumulative work than a comparable chip multiprocessor. Further, variation mitigation in StageWeb enables it to scale supply voltage more aggressively, resulting in up to 16% energy savings.

关键词： permanent faults process variation multi-core architecture reliability

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Dynamic load balancing on single- and multi-GPU systems

Dynamic load balancing on single- and multi-GPU systems

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24th ieee international Parallel and Distributed Processing Symposium, IPDPS 2010

作者： Chen, Long Villa, Oreste Krishnamoorthy, Sriram Gao, Guang R. Department of Electrical and Computer Engineering University of Delaware Newark DE 19716 United States High Performance Computing Pacific Northwest National Laboratory Richland WA 99352 United States

ISBN: (纸本)9781424464432

The computational power provided by many-core graphics processing units (GPUs) has been exploited in many applications. The programming techniques currently employed on these GPUs are not sufficient to address problems exhibiting irregular, and unbalanced workload. The problem is exacerbated when trying to effectively exploit multiple GPUs concurrently, which are commonly available in many modern systems. In this paper, we propose a task-based dynamic load-balancing solution for single- and multi-GPU systems. The solution allows load balancing at a finer granularity than what is supported in current GPU programming APIs, such as NVIDIA's CUDA. We evaluate our approach using both micro-benchmarks and a molecular dynamics application that exhibits significant load imbalance. Experimental results with a single- GPU configuration show that our fine-grained task solution can utilize the hardware more efficiently than the CUDA scheduler for unbalanced workload. On multi- GPU systems, our solution achieves near-linear speedup, load balance, and significant performance improvement over techniques based on standard CUDA APIs. ©2010 ieee.

关键词： Graphics processing unit

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Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing

Space and Time Sharing of Reconfigurable Hardware for Accele...

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6th international workshop on Applied Reconfigurable computing

作者： El-Araby, Esam Narayana, Vikram K. El-Ghazawi, Tarek George Washington Univ NSF Ctr High Performance Reconfigurable Comp CHRE Washington DC 20052 USA

ISBN: (纸本)9783642121326

High-Performance Reconfigurable Computers (HPRCs) are parallel machines consisting of FPGAs and microprocessors, with the FPGAs used as co-processors. The execution of parallel applications on such systems has mainly followed the Single-Program multiple-Data (SPMD) model;however, overall system resources are often underutilized because of the asymmetric distribution of the reconfigurable (co-)processors relative to the (main) processors. Furthermore, with the introduction of HPRCs containing multi/many-core technologies, underutilization of system resources becomes more obvious especially for multi-tasking and multi-user usage. To address the asymmetry problem, we propose a resource virtualization solution based on Partial Run-Time Reconfiguration (PRTR). The proposed technique allows space, time, and/or space-time sharing of the reconfigurable (co-)processors among the (main) processors and thus increasing the overall system utilization. We show the effectiveness of the proposed concepts through a stochastic execution model verified with experimental implementations on the Cray XD1 platform. The results demonstrate favorable performance as well as scalability characteristics.

关键词： Dynamic Partial Reconfiguration Hardware Virtualization High Performance computing Reconfigurable computing

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Effective dynamic scheduling on heterogeneous multi/manycore desktop platforms

Effective dynamic scheduling on heterogeneous multi/manycore...

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ieee international Symposium on Computer Architecture and High Performance computing

作者： Binotto, Alécio P. D. Pedras, Bernardo M. V. Götz, Marcelo Kuijper, Arjan Pereira, Carlos E. Stork, André Fellner, Dieter W. Institute of Informatics UFRGS Federal University of Rio Grande do Sul Porto Alegre Brazil Fraunhofer IGD Technische Universität Darmstadt Darmstadt Germany

ISBN: (纸本)9780769542768

GPUs (Graphics Processing Units) have become one of the main co-processors that contributed to desktops towards high performance computing. Together with multicore CPUs and other co-processors, a powerful heterogeneous execution platform is built on a desktop for data intensive calculations. In our perspective, we see the modern desktop as a heterogeneous cluster that can deal with several applications' tasks at the same time. To improve application performance and explore such heterogeneity, a distribution of workload over the asymmetric PUs (Processing Units) plays an important role for the system. However, this problem faces challenges since the cost of a task at a PU is non-deterministic and can be influenced by several parameters not known a priori, like the problem size domain. We present a context-aware architecture that maximizes application performance on such platforms. This approach combines a model for a first scheduling based on an offline performance benchmark with a runtime model that keeps track of tasks' real performance. We carried a demonstration using a CPU-GPU platform for computing iterative SLEs (systems of Linear Equations) solvers using the number of unknowns as the main parameter for assignment decision. We achieved a gain of 38.3% in comparison to the static assignment of all tasks to the GPU (which is done by current programming models, such as OpenCL and CUDA for Nvidia). © 2010 ieee.

关键词： Graphics processing unit

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Performance evaluation of optimized implementations of finite difference method for wave propagation problems on GPU architecture

Performance evaluation of optimized implementations of finit...

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ieee international Symposium on Computer Architecture and High Performance computing

作者： Brandão, Diego Zamith, Marcelo Clua, Esteban Montenegro, Anselmo Bulcão, André Madeira, Daniel Kischinhevsky, Mauricio Leal-Toledo, Regina C.P. MediaLab. Institute for Computing Universidade Federal Fluminense Passo da Pátria Street 156 Niterói Rio de Janeiro Brazil Cenpes Petrobrás Ilha do Fundão Rio de Janeiro Brazil Institute for Computing Universidade Federal Fluminense Passo da Ṕatria Street 156 Niterói Rio de Janeiro Brazil

ISBN: (纸本)9780769542768

The scattering of acoustic waves in non-homogeneous media has been of practical interest for the petroleum industry, mainly in the determination of new oil deposits. A family of computational models that represent this phenomenon is based on finite difference methods. The simulation of these phenomena demands a high computational cost. In this work we employ GPU for the development of solvers for a 2D wave propagation problem with finite difference methods. Although there are many related works that use the same implementation presented in this paper, we propose a detailed and novel performance and memory bottleneck analysis for this hardware architecture. © 2010 ieee.

关键词： Finite difference method

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GMH: A message passing toolkit for GPU clusters

GMH: A message passing toolkit for GPU clusters

引用

16th ieee international Conference on Parallel and Distributed systems, ICPADS 2010

作者： Chen, Jie Watson III, William Mao, Weizhen Scientific Computing Group Jefferson Lab. Newport News VA 23606 United States Department of Computer Science College of William and Mary Williamsburg VA 23187 United States

ISBN: (纸本)9780769543079

Driven by the market demand for high-definition 3D graphics, commodity graphics processing units (GPUs) have evolved into highly parallel, multi-threaded, many-core processors, which are ideal for data parallel computing. many applications have been ported to run on a single GPU with tremendous speedups using general C-style programming languages such as CUDA. However, large applications require multiple GPUs and demand explicit message passing. This paper presents a message passing toolkit, called GMH (GPU Message Handler), on NVIDIA GPUs. This toolkit utilizes a data-parallel thread group as a way to map multiple GPUs on a single host to an MPI rank, and introduces a notion of virtual GPUs as a way to bind a thread to a GPU automatically. This toolkit provides high performance MPI style point-to-point and collective communication, but more importantly, facilitates event-driven APIs to allow an application to be managed and executed by the toolkit at runtime. © 2010 ieee.

关键词： Graphics processing unit

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1st workshop on fault-tolerance for HPC at extreme scale FTXS 2010

1st workshop on fault-tolerance for HPC at extreme scale FTX...

引用

2010 international Conference on Dependable systems and Networks workshops, DSN-W 2010

作者： Daly, John DeBardeleben, Nathan Department of Defense Center for Exceptional Computing United States

ISBN: (纸本)9781424477302

With the emergence of many-core processors, accelerators, and alternative/heterogeneous architectures, the HPC community faces a new challenge: a scaling in number of processing elements that supersedes the historical trend of scaling in processor frequencies. The attendant increase in system complexity has first-order implications for fault tolerance. Mounting evidence invalidates traditional assumptions of HPC fault tolerance: faults are increasingly multiple-point instead of single-point and interdependent instead of independent;silent failures and silent data corruption are no longer rare enough to discount;stabilization time consumes a larger fraction of useful system lifetime, with failure rates projected to exceed one per hour on the largest systems;and application interrupt rates are apparently diverging from system failure rates.

关键词： Fault tolerance

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Improving virtualization performance and scalability with advanced hardware accelerations

Improving virtualization performance and scalability with ad...

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2010 ieee international Symposium on Workload Characterization, IISWC'10

作者： Dong, Yaozu Zheng, Xudong Zhang, Xiantao Dai, Jinquan Li, Jianhui Li, Xin Zhai, Gang Guan, Haibing Intel China Software Center Shanghai China Shanghai Key Laboratory of Scalable Computing and Systems Shanghai Jiao Tong University China

ISBN: (纸本)9781424492978

many advanced hardware accelerations for virtualization, such as Pause Loop Exit (PLE), Extended Page Table (EPT), and Single Root I/O Virtualization (SR-IOV), have been introduced recently to improve the virtualization performance and scalability. In this paper, we share our experience with the performance and scalability issues of virtualization, especially those brought by the modern, multi-core and/or overcommitted systems. We then describe our work on the implementation and optimizations of the advanced hardware acceleration support in the latest version of Xen. Finally, we present performance evaluations and characterizations of these hardware accelerations, using both micro-benchmarks and a server consolidation benchmark (vConsolidate). The experimental results demonstrate an up to 77% improvement with these hardware accelerations, 49% of which is due to EPT and another 28% due to SR-IOV. © 2010 ieee.

关键词： Virtualization

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