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Introducing multi-level parallelism, at coarse, fine and instruction level to enhance the performance of iterative solvers for large sparse linear systems on multi- and many-core architecture 6

Introducing multi-level parallelism, at coarse, fine and ins...

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ieee/ACM 6th workshop on the LLVM Compiler Infrastructure in HPC / workshop on Hierarchical Parallelism for Exascale computing (LLVM-HPC and HiPar)

作者： Gratien, Jean-Marc IFP Energies Nouvelles Comp Sci Dept Rueil Malmaison France

ISBN: (纸本)9780738110424

With the evolution of High Performance computing, multi-core and many-core systems are now a common feature of new hardware architectures. The introduction of very large number of cores at the processor level is challenging because it requires to handle multi level parallelism at various levels either coarse or fine to fully take advantage of the offered computing power. The induced programming effort can be fixed with parallel programming models based on the data flow model and the task programming paradigm [1]. To do so many of the standard numerical algorithms must be revisited as they cannot be easily parallelized at the finest levels. Iterative linear solvers are a key part of petroleum reservoir simulation as they can represent up to 80% of the total computing time. In these algorithms, the standard preconditioning methods for large, sparse and unstructured matrices - such as Incomplete LU Factorization (ILU) or Algebraic multigrid (AMG) - fail to scale on shared-memory architectures with large number of cores. In this paper we reconsider preconditioning algorithms to better introduce multi-level parallelism at both coarse level with MPI, fine level with threads and at the instruction level to enable SIMD optimizations. This paper illustrates how we enhance the implementation of preconditioners like the multi-level domain decomposition (DDML) preconditioners [2], based on the popular Additive Schwartz Method (ASM), or the classical ILU0 preconditioner with the fine grained parallel fixed point variant presented in [3]. Our approach is validated on linear systems extracted from realistic petroleum reservoir simulations. The robustness of the preconditioners is tested with respect to the data heterogeneities of the study cases. We evaluate the extensibility of our implementation regarding the model sizes and its scalability regarding the large number of cores provided by new KNL processors or multi-nodes clusters.

关键词： HPC Task Programming many-cores multi-Level Parallelism Parallel Algorithms

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Evaluating multi-Level Checkpointing for Distributed Deep Neural Network Training

Evaluating Multi-Level Checkpointing for Distributed Deep Ne...

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ieee/ACM 7th international workshop on Heterogeneous High- Performance Reconfigurable computing (H2RC) Part of international Conference for High Performance computing, Networking, Storage and Analysis (SC)

作者： Anthony, Quentin Dai, Donglai X ScaleSolut LLC Columbus OH 43221 USA Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781665483889

Deep learning (DL) applications are becoming one of the most important applications for HPC and cloud systems. The massive datasets and deep neural networks (DNN) used by DL applications introduce many HPC challenges. Therefore, HPC checkpoint/restart tools are an attractive choice. However, most data-parallel DL training jobs use a naive scheme, called root checkpointing, which is subject to blocking semantics and straggling forward progress. In this work, we apply a multi-level checkpointing tool (SCR-Exa) to distributed DL applications. We examine the performance of two DNN models at scale on Lassen (a leading TOP500 system), while ensuring the DNN's accuracy is maintained after restart from simulated system failures. Our test results show that multi-level checkpointing schemes are able to achieve nearly constant overhead at scale. To the best our knowledge, this study presents the first evaluation to demonstrate strong scalability of a checkpointing scheme for distributed DL without making framework-specific changes.

关键词： Deep Learning Neural Networks Faulttolerance Checkpointing High Performance computing Performance Characterization MVAPICH2 MPI PyTorch Horovod

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Developing a proxy application for an industrial unstructured CFD software: preliminary results

Developing a proxy application for an industrial unstructure...

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international Conference on Parallel and Distributed systems (ICPADS)

作者： Qingsong Wang Chuanfu Xu Jian Zhang Liang Deng Zhe Dai Haozhong Qiu Weixi Dai Yongzhen Lin Yue Ding Yonggang Che Institute for Quantum Information & State Key Laboratory of High Performance Computing National University of Defense Technology Changsha China China Aerodynamic Research and Development Center Mianyang China

As programming models and architectures evolve in the exa-scale era, porting large-scale HPC applications are becoming increasingly difficult and expensive. In HPC community, mini-apps are often developed to mimic real-world applications, and it offers an easy way to benchmark new HPC platforms. In this paper, we design and implement a mini-app MiniFS as a proxy for an industry-level unstructured Computational Fluid Dynamics (CFD) software FlowStar. The main purpose of MiniFS is to evaluate different shared memory approaches on emerging multi/many-core architectures, because data conflicts and data dependencies in unstructured CFD pose tough challenges for shared memory parallelization. Results show that our mini-app can represent the performance characteristic of the original application. However, the existing approaches are unscalable on modern multi/many-cores. It is imperative to develop novel scalable shared memory approaches for unstructured CFD.

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Exploring the Potential of Error-permissive Communication in multi-FPGA-based Edge computing

Exploring the Potential of Error-permissive Communication in...

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ieee international Symposium on Embedded multicore Socs (MCSoC)

作者： Akram Ben Ahmed Ryousei Takano Takahiro Hirofuchi Digital Architecture Research Center National Institute of Advanced Industrial Sciences and Technology Koto-ku Tokyo JAPAN

ISBN: (纸本)9781665465007

In recent years, Edge computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on multi-FPGA systems which have gained significant attention in Edge computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%.

关键词： Performance evaluation Electric potential Cloud computing Power demand multicore processing Voltage Transceivers

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A Case for Second-Level Software Cache Coherency on many-core Accelerators

A Case for Second-Level Software Cache Coherency on Many-Cor...

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international workshop on Rapid System Prototyping (RSP)

作者： Arthur Vianès Frèdèric Pètrot Frèdèric Rousseau CNRS Univ. Grenoble Alpes Grenoble INP TIMA Grenoble France Benoît Dupont de Dinechin Kalray S.A. Montbonnot France

ISBN: (纸本)9798350398892

Cache and cache-coherence are major aspects of today's high performance computing. A cache stores data as cache-lines of fixed size, and coherence between caches is guaranteed by the cache-coherence protocol which operates on fixed size coherency-blocks. In such systems cache-lines and coherency-blocks are usually the same size and are relatively small, typically 64 bytes. This size choice is a trade-off selected for general-purpose computing: it minimizes false-sharing while keeping cache-maintenance traffic low. False-sharing is considered an unnecessary cache-coherence traffic and it decreases performances. However, for dedicated accelerator this trade-off may not be appropriate: hardware in charge of cache-coherence is expensive and not well exploited by most accelerator applications as by construction these applications minimize false-sharing. This paper investigates the possibility of an alternative trade-off of cache-coherency and cache-maintenance block size for many-core accelerators, by decoupling coherency-block and cache-lines sizes. Interests, advantages and difficulties are presented and discussed in this paper. Then we also discuss needs of software and hardware modifications in prototypes and the capability of such prototypes to evaluate different coherence-block sizes.

关键词： Protocols High performance computing Conferences Prototypes Coherence Hardware Software

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Developing Computer Applications without any OS or Kernel in a multi-core Architecture

Developing Computer Applications without any OS or Kernel in...

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2021 international Symposium on Networks, Computers and Communications, ISNCC 2021

作者： Ordouie, Navid Soundararajan, Nirmala Karne, Ramesh Wijesinha, Alexander L. Towson University Department Of Computer And Information Sciences Towson United States

ISBN: (纸本)9780738113166

Over the years, operating systems (OSs) have grown significantly in complexity and size providing attackers with more avenues to compromise their security. By eliminating the OS, it becomes possible to develop general-purpose non-embedded applications that are free of typical OS-related vulnerabilities. Such applications are simpler and smaller in size, making it easier secure the application code. Bare machine computing (BMC) applications run on ordinary desktops and laptops without the support of any operating system or centralized kernel. many BMC applications have been developed previously for single-core systems. We show how to build BMC applications for multicore systems by presenting the design and implementation of a novel UDP-based bare machine prototype Web server for a multicore architecture. We also include preliminary experimental results from running the server on the Internet. This work provides a foundation for building secure computer applications that run on multicore systems without the need for intermediary software. © 2021 ieee.

关键词： Web services

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Estimation Method Considering OS Overheads for Embedded many-core Platform 18

Estimation Method Considering OS Overheads for Embedded Many...

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18th ieee international Conference on Embedded and Ubiquitous computing (ieee EUC)

作者： Honda, Kentaro Fujimoto, Hiroshi Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan eSOL Co Ltd Technol Headquarters Tokyo Japan

ISBN: (纸本)9780738111186

Embedded systems such as automotive systems require high computational power and low power consumption. To meet these requirements, many-core processors have attracted attention. Compared with single-core processors, many-core processors can execute multiple processes in parallel, allowing for improved power consumption and performance. Due to their performance, many-core processors can be used in automotive systems which have strict real-time requirements. Therefore, it is important to obtain accurate hardware and software information. In this paper, we propose a method for estimating the execution time of an application supported by MATLAB/Simulink on a many-core platform. The proposed method considers operating system (OS) overheads with a real-time OS and Kalray MPPA-256 cluster structure which contains many-core processors. The effectiveness, and the experimental results demonstrate that the proposed method is more accurate than existing methods.

关键词： Mapping Model based development multi/many core

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Research Needs in Human-Autonomy Teaming: Thematic Analysis of Priority Features for Testbed Development

Research Needs in Human-Autonomy Teaming: Thematic Analysis ...

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ieee international workshop on Robot and Human Communication (ROMAN)

作者： Mason O. Smith Sunny Amatya Ashish Amresh Jamie Gorman Matthew Johnson Nancy Cooke Wenlong Zhang School of Manufacturing Systems and Networks Arizona State University Mesa AZ USA School of Informatics Computing and Cyber Systems Northern Arizona University Flagstaff AZ USA The Polytechnic School Arizona State University Mesa AZ USA Florida Institute of Human & Machine Cognition Pensacola FL USA

ISBN: (数字)9798350375022

ISBN: (纸本)9798350375039

Human-Autonomy Teaming (HAT) is a multi-disciplinary domain with a diverse set of research needs and goals stemming from fields such as computer science, robotics, and human factors. This melting pot of fields generates a unique challenge in that there exist many disjoint research methods (measures and tasks) that cause issues with knowledge transfer and comparison between researchers. One way to address this issue is by providing researchers with a testbed containing a standardized suite of analysis tools and tasks that allow direct comparison between different approaches. Therefore, this study attempts to bring the HAT community together in a collaborative discussion to collect and organize their research needs for the future development of these testbeds. Specifically, through thematic analysis, our work reveals three emergent prongs that underpin testbed needs of HAT experts: task, AI, and technical requirements. Also, we organize our thematic analysis by priority to suggest possible paths for HAT testbed development to maximize its immediate and continued utility. Our research indicates that the HAT community places significant importance on both the pre-established, standardized functions available within the testbed and the freedom to tailor and develop their unique tasks or AI solutions.

关键词： Training Technical requirements Collaboration Pressing Human factors Programming Planning Artificial intelligence Robots Knowledge transfer

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Contention-free scheduling algorithm using LET paradigm for clustered many-core processor 21

Contention-free scheduling algorithm using LET paradigm for ...

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Proceedings of the 2021 ieee/ACM 25th international Symposium on Distributed Simulation and Real Time Applications

作者： Atsushi Yano Shingo Igarashi Takuya Azumi Saitama University

ISBN: (纸本)9781665433266

Self-driving systems require multi-/many-core platforms with high computing power and low power consumption. However, for hard real-time applications, multiple demands on shared resources can impede real-time performance. Therefore, making the timing of memory access deterministic is important. The logical execution time (LET) paradigm has gained attention as a means to achieve this purpose. However, this approach lacks scalability owing to the overhead caused because the LET paradigm is set longer than the actual execution time of the task. This paper proposes a theoretical scheduling method for a model applying the LET paradigm to the directed acyclic graph (DAG) nodes for a multi-/many-core platform. The proposed method considers communication timing and generates a schedule that does not cause communication contentions. In addition, the proposed method performs a parallel calculation of tasks to deal with the overhead caused by adopting the LET paradigm.

关键词： multi-rate DAG communication contention logical execution time list-scheduling multi-/many-core

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CUDA-DClust+: Revisiting Early GPU-Accelerated DBSCAN Clustering Designs 28

CUDA-DClust+: Revisiting Early GPU-Accelerated DBSCAN Cluste...

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28th ieee international Conference on High Performance computing, Data, and Analytics, HiPC 2021

作者： Poudel, Madhav Gowanlock, Michael School Of Informatics Computing And Cyber Systems Northern Arizona University FlagstaffAZ United States

ISBN: (纸本)9781665410168

Density-based clustering algorithms are widely used unsupervised data mining techniques to find the clusters of points in dense regions that are separated by low-density regions. This algorithm is inherently sequential and has limitations in its parallel implementation. There have been several parallel algorithms presented in the literature for multi-core CPUs and many-core GPUs. One such algorithm for the GPU is CUDA-DCLUST. In this paper, we propose a new GPU-accelerated DBSCAN algorithm with several optimizations. In comparison to prior work, our algorithm, Cuda-dclust+:(i) computes the indexing structure on the GPU, (ii) uses kernel fusion to combine the index search and cluster expansion kernels, which reduces communication and synchronization overhead with the host, and (iii) seed list management control is primarily given to the GPU rather than the CPU, which further decreases CPU-GPU communication overhead. We compare our algorithm to three state-of-the-art parallel algorithms in the literature on six real-world datasets. We find that our algorithm achieves a speedup of up to 23x over the fastest GPU algorithm. © 2021 ieee.

关键词： Graphics processing unit

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