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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

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Parallel Dense Gauss-Seidel Algorithm on many-core Processors

Parallel Dense Gauss-Seidel Algorithm on Many-Core Processor...

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11th ieee international Conference on High Performance computing and Communications

作者： Courtecuisse, Hadrien Allard, Jeremie INRIA Lille Nord Europe Lille France

ISBN: (纸本)9781424446001

The Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited sparsity in the system matrix to extract parallelism. In this paper, we propose to study several parallelization schemes for fully-coupled systems, unable to be parallelized by existing methods, taking advantage of recent many-cores architectures offering fast synchronization primitives. Experimental results on both multi-core CPUs and recent GPUs show that our proposed method is able to fully exploit the available units, whereas trivial parallel algorithms often fail. This method is illustrated by an application in medical intervention planning, where it is used to solve a linear complementary problem (LCP) expressing the contacts applied to a deformable body.

关键词： parallel algorithms linear complementary problem GPGPU physically based modeling

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Phase-guided Thread-to-core Assignment for Improved Utilization of Performance-Asymmetric multi-core Processors

Phase-guided Thread-to-core Assignment for Improved Utilizat...

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2nd international workshop on multicore Software Engineering (IWMSE 2009) held at the 31st international Conference on Software Engineering

作者： Sondag, Tyler Rajan, Hridesh Iowa State Univ Dept Comp Sci Ames IA 50011 USA

ISBN: (纸本)9781424437184

CPU vendors are starting to explore trade offs between die size, number of cores on a die, and power consumption leading to performance asymmetry among cores on a single chip. For efficient utilization of these performance asymmetric multi-core processors, application threads must be assigned to cores such that the resource needs of a thread closely matches resource availability at the assigned core. This significantly complicates the task of an average programmer The contribution of this work is a technique for automatically determining the mapping between threads and performance-asymmetric cores of a processor Our approach, which we call phase-guided thread-to-core assignment, builds on a well-known insight that programs exhibit phase behavior We first take code sections and group them into clusters such that each section in a cluster is likely to exhibit similar runtime characteristics. The key, idea is that with this clustering, characteristics of a small number of representative sections in a cluster give insight into the behavior of the entire cluster Thus the exhibited characteristics of the representative sections on different types of cores can be used for automating thread-to-core assignment at a lower runtime cost. Variations of our technique show up to an average 150% improvement in throughput over the stock Linux scheduler for systems with a constant feed of jobs, while maintaining comparable fairness and efficiency.

关键词： Economic and social effects

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Power-Aware Scheduling of Virtual Machines in DVFS-enabled Clusters

Power-Aware Scheduling of Virtual Machines in DVFS-enabled C...

引用

ieee international Conference on Cluster computing (Cluster 2009)

作者： von Laszewski, Gregor Wang, Lizhe Younge, Andrew J. He, Xi Rochester Inst Technol Serv Oriented Cyberinfrastruct Lab Rochester NY 14623 USA

ISBN: (纸本)9781424450114

With the advent of Cloud computing, large-scale virtualized compute and data centers are becoming common in the computing industry. These distributed systems leverage commodity server hardware in mass quantity, similar in theory to many of the fastest Supercomputers in existence today. However these systems can consume a cities worth of power just to run idle, and require equally massive cooling systems to keep the servers within normal operating temperatures. This produces CO2 emissions and significantly contributes to the growing environmental issue of Global Warming. Green computing, a new trend for high-end computing, attempts to alleviate this problem by delivering both high performance and reduced power consumption, effectively maximizing total system efficiency. This paper focuses on scheduling virtual machines in a compute cluster to reduce power consumption via the technique of Dynamic Voltage Frequency Scaling (DVFS). Specifically, we present the design and implementation of an efficient scheduling algorithm to allocate virtual machines in a DVFS-enabled cluster by dynamically scaling the supplied voltages. The algorithm is studied via simulation And implementation in a multi-core cluster. Test results and performance discussion justify the design and implementation of the scheduling algorithm.

关键词： Dynamic Voltage and Frequency Scaling Cluster computing Virtual machine Scheduling

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Performance of Triplet based Interconnection Strategy for multi-core On-Chip Processors

Performance of Triplet based Interconnection Strategy for Mu...

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11th ieee international Conference on High Performance computing and Communications

作者： Khan, Haroon-Ur-Rashid Shi Feng Jia Xinli Bai Ziru Beijing Inst Technol Dept Comp Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781424446001

We have entered the era of many-core processors and complex SoCs, where on-chip interconnection networks play a dominant role in determining the performance, power, and ultimately cost of a system. Therefore, interconnection strategy that supports efficient communication between IP blocks is essential. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of group locality in an interconnection network, the "lower layer complete connect". Our proposed criterion depicts how completely a processing node is connected to all its neighbors. In this paper we evaluate TriBA, a class of direct interconnection network (DIN), for multi-core on-chip interconnection architecture. TriBA is compared with 2D Mesh as static interconnection networks for VLSI implementation. The criteria of evaluation are enumerated from two orthogonal view points, viz., computational speed and physical layout. We conclude that TriBA has the potential to have significantly better performance as an on-chip interconnection network for future MPSoC systems.

关键词： Topology

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Parallelization of Particle Swarm Optimization and Its Implementation on Scalable multi-core Architecture

Parallelization of Particle Swarm Optimization and Its Imple...

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ieee international Advance computing Conference

作者： Chauhan, N. C. Aggarwal, Dhruv Banga, Rohit Mittal, Ankush Kartikeyan, M. V. Indian Inst Technol Dept Elect & Comp Engn Roorkee 247667 Uttar Pradesh India

ISBN: (纸本)9781424429271

The Particle Swarm Optimization (PSO) is a stochastic, population-based algorithm for search and optimization from a multidimensional space. many engineering design problems in real life have complicated optimization functions, which require massive computational power, to solve in reasonable time when implemented sequentially. Thus, scalable parallel implementations are required to speed up these algorithms, and reduce the over-all design process time. In this paper, we present a model for parallelization of PSO algorithm, and its implementation on Cell Broadband Engine architecture.

关键词： Stochastic systems

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Zero-buffer inter-core process communication protocol for heterogeneous multi-core platforms

Zero-buffer inter-core process communication protocol for he...

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15th ieee international Conference on Embedded and Real-Time computing systems and Applications, RTCSA 2009

作者： Lin, Yu-Hsien Tu, Chiaheng Shih, Chi-Sheng Hung, Shih-Hao Department of Computer Science and Information Engineering Graduate Institute of Networking and Multimedia National Taiwan University Taipei 106 Taiwan

ISBN: (纸本)9780769537870

Executing functional components in pipeline on heterogeneous multi-core platforms can greatly improve the parallelism but require great amount of data communication among processes and threads. Our studies showed that existing inter-process/thread communication protocols consist of many unnecessary memory copies and prolong the execution of the applications on heterogeneous multi-core platforms. Our experiments also showed that the communication overhead accounts 40% to 50% of total execution time in average for H.264 video decoding applications. In this paper, we present the design and implementation of zero-buffer inter-core process communication protocol, named NTU ICPC, to shorten communication overhead for pipeline executed applications on heterogeneous multi-core platforms. NTU ICPC uses polling-base mail notification to avoid unnecessary context switches, and designs a memory subsystem to manage the input and output data between the senders and receivers. The protocol was implemented and evaluated on heterogeneous multi-core platform for several use scenario including H.264 encoding process. The evaluation results show that the communication overhead on sender side is independent of the data size and that on receiver side is greatly shortened, compared to several inter-process communication (IPC) protocols including mailbox, message queue, and shared memory. When encoding H.264 video clips, the encoding frame rates increase for more than 30%. © 2009 ieee.

关键词： Pipelines

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Scalable computing with parallel tasks

Scalable computing with parallel tasks

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2nd ACM workshop on many-Task computing on Grids and Supercomputers 2009, MTAGS '09

作者： Dümmler, Jörg Rauber, Thomas Rünger, Gudula Chemnitz University of Technology Dept. of Computer Science Straße der Nationen 62 09111 Chemnitz Germany Bayreuth University Angewandte Informatik II Universitätsstr. 30 95447 Bayreuth Germany

ISBN: (纸本)9781605587141

Recent and future parallel clusters and supercomputers use SMPs and multi-core processors as basic nodes, providing a huge amount of parallel resources. These systems often have hierarchically structured interconnection networks combining computing resources at different levels, starting with the interconnect within multi-core processors up to the interconnection network combining nodes of the cluster or supercomputer. The challenge for the programmer is that these computing resources should be utilized efficiently by exploiting the available degree of parallelism of the application programs and by structuring the application in a way which is sensitive to the heterogeneous interconnect. In this article, we present an approach to structure the computations of an application as parallel tasks which can interact with other parallel tasks in communication phases. In particular, we consider how these parallel tasks can be mapped onto the computing resources provided by parallel clusters or supercomputers. We show that the scalability can be significantly improved by a suitable task-based organization and a corresponding structuring of the communication within tasks as well as between tasks. We evaluate the impact of different mappings of tasks to cores for different application programs on a variety of parallel machines. Copyright © 2009 ACM.

关键词： Application programs

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Accurate, Scalable and Informative Design Space Exploration for Large and Sophisticated multi-core Oriented Architectures

Accurate, Scalable and Informative Design Space Exploration ...

引用

17th ieee international Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication systems

作者： Cho, Chang-Burm Poe, James Li, Tao Yuan, Jingling Univ Florida Dept ECE IDEAL Gainesville FL 32611 USA Wuhan Univ Technol Comp Sci & Technol Sch Wuhan Hubei Peoples R China

ISBN: (纸本)9781424449262

As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can he used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.

关键词： wavelet transform neural network NUCA multi-core design space exploration

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Enhanced parallel loop self-scheduling for heterogeneous multi-core cluster systems

Enhanced parallel loop self-scheduling for heterogeneous mul...

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10th international Symposium on Pervasive systems, Algorithms, and Networks, I-SPAN 2009

作者： Wu, Chao-Chin Huang, Liang-Tsung Lai, Lien-Fu Chen, Ming-Lung Department of Computer Science and Information Engineering National Changhua University of Education Taiwan Department of Information Communication MingDao University Taiwan

ISBN: (纸本)9780769539089

Recently, more and more studies investigated the issue of dealing with the heterogeneity problem on heterogeneous cluster systems consisting of multi-core computing nodes. Previously we have proposed a hybrid MPI and OpenMP based loop self-scheduling approach for this kind of system. The allocation functions of several well-known schemes have been modified for better performance. Though the previous approach can improve system performance significantly, in this paper we present how to enhance the speedup further. First, we exploit the thread-level parallelism on the multi-core master node. Second, we investigate how to design a loop self-scheduling scheme which is able to smartly assign a proper chunk size according to each node's performance. At the beginning of dispatching, we prevent the slow slaves from being assigned too many tasks. On the other hand, the master will not assign too many small chunks to slaves at the end. Experimental results show that our approach could obtain the best speedup of 1.35. © 2009 ieee.

关键词： Scheduling

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Risks and chances of many-core processors

Risks and chances of many-core processors

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2009 international Conference on High Performance computing and Simulation, HPCS '09

作者： Uhrig, Sascha University of Augsburg Augsburg Germany

ISBN: (纸本)9781424449071

The decreasing structure size of VLSI technology features a lot of chances to processor designers but it also brings many risks [1]. Most of these risks stem from the manufacturing process and lead to an increased number of chips with defects which are uniformly distributed over the wafer. Other problems arise during the uptime of the system because of thermal effects or radiation. Happily, one of the chances is to integrate many complete processor cores together with a suitable network infrastructure into one single chip. Hence, it is not required that all processor cores of a multi- or many-core design definitely work well as it is the case in the PlayStation3 [2]. Moreover, using an appropriate virtualization layer together with some hardware support enables complex many-core systems to deal with temporary malfunctions and the occurrence of persistent defects. Both problems should be handled by a hardware/software cooperation under control of the virtualization engine and, hence, transparent to the application. As a result, we could gain a more reliable system in conjunction with a higher performance in spite of the additional virtualization layer. The talk presents both, some risks and some possibilities to deal with these risks using the opportunity to build a many-core processor as well as the chances given by the high number of cores per chip. © 2009 ieee.

关键词： Virtualization

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