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Design of new hash mapping functions

Design of new hash mapping functions

引用

ieee 9th international Conference on Computer and Information Technology, CIT 2009

作者： Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflictfree. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewedassociative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme. © 2009 ieee.

关键词： Hash functions

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A framework for core-level modeling and design of reconfigurable computing algorithms

A framework for core-level modeling and design of reconfigur...

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3rd international workshop on High-Performance Reconfigurable computing Technology and Applications, HPRCTA'09, held in Conjunction with SC09

作者： Wang, Gongyu Stitt, Greg Lam, Herman George, Alan D. University of Florida Gainesville FL 32611 United States

ISBN: (纸本)9781605587219

Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-logic hardware devices, such as the FPGA, combined with the versatility of software-driven hardware configuration often boost performance while reducing power consumption. However, compared to software design tools, the relatively immature state of RC design tools significantly limits productivity and consequently limits widespread adoption of RC. Long and tedious design-translate-execute (DTE) processes for RC applications (e.g., using RTL through HDL) must be repeated in order to meet mission requirements. Novel methods for rapid virtual prototyping and performance prediction can reduce DTE repetitions by providing fast and accurate tradeoff analysis before the design stage. This paper presents a novel core-level modeling and design (CMD) framework for RC algorithms to support fast, accurate and early design-space exploration (DSE). The framework provides support for core-level modeling, performance prediction, and rapid bridging to design and translation. core-level modeling enables detailed DSE without the need for coding. Performance prediction, such as maximum clock frequency, supports core-level DSE and can help system-level modeling and design tools to achieve more accurate system-level DSE. Finally, core-level models can be used to generate code templates and design constraints that feed translation tools and to rapidly obtain predicted performance. Copyright © 2009 ACM.

关键词： Computation theory

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A memory access scheduling method for multi-core processor

A memory access scheduling method for multi-core processor

引用

2nd international workshop on Computer Science and Engineering, WCSE 2009

作者： Liu, Mengxiao Ji, Weixing Wang, Zuo Pu, Xing School of Computer Science and Technology Beijing Institute of Technology Beijing 100081 China

ISBN: (纸本)9780769538815

It is well known fact that multi-core processor architecture is the mainstream of the next-generation microprocessor architecture and actualizes by Chip multi-core Processors (CMP). As the number of cores per processor and the number of threaded applications increase, the performance of more and more applications will be limited by the processor's memory bandwidth. DRAM memory is a major resource shared among cores in a CMP system. However, shared hardware resources pose a significant resource management problem in designing CMP systems. DRAM bandwidth becomes a critical shared resource makes developers are faced with the challenges of memory wall. The on-chip and off-chip cache or memory resources are limited and in many situations, cannot hold the working set of the threads running on all these cores. Existing DRAM access management schemes provide support for enforcing bandwidth shares but have problems like starvation, complexity, and unpredictable DRAM access latency. In this paper, we analyze the structures of DRAM and the prevalent multi-core architectures, and then we propose a Fair Dynamic Pipelining (FDP) memory access scheduling to resolve the memory wall problem. The experiment result shown that FDP avoids unexpected long latencies or starvation of memory requests using the dynamic pipeline arrangement policy and it provides an alterable priority strategy to make the response of memory more fairly. So that the FDP scheduling makes the bandwidth shares to achieve desired average latencies for multi cores memory accesses. © 2009 ieee.

关键词： Memory architecture

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Autonomic energy management of multi-tier clustered applications

Autonomic energy management of multi-tier clustered applicat...

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2009 10th ieee/ACM international Conference on Grid computing, Grid 2009

作者： Gadafi, Aeiman Hagimont, Daniel Broto, Laurent Pierson, Jean-Marc Toulouse University France

ISBN: (纸本)9781424451494

Nowadays, medium or large-scale distributed infrastructures such as clusters and grids are widely used to host various kinds of applications (e.g. web servers or scientific applications). Power consumption is becoming a major challenge for most organizations that run these infrastructures. many studies show that they are not used at their full capacity and that there are therefore a huge source of wasted power. Autonomic management systems have been introduced in order to dynamically adapt software infrastructures according to runtime conditions. They provide support to deploy, configure, monitor, and repair applications in such environments. In this paper, we report our experiments in using Tune - an autonomic management system - to provide energy aware management for a clustered J2EE application. We use Tune to dynamically adapt the degree of replication of the J2EE tiers in the cluster, and to dynamically turn cluster nodes on - to handle the load when it raises up - and off - to save power under lighter load. © 2009 ieee.

关键词： Power management

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3D WLAN indoor positioning in multi-storey buildings

3D WLAN indoor positioning in multi-storey buildings

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ieee international workshop on Intelligent Data Acquisition and Advanced computing systems: Technology and Applications

作者： S. Gansemer S. Hakobyan S. Püschel U. Großmann University of Applied Sciences and Arts Dortmund Dortmund Germany University of Applied Sciences and Arts Dortmund Dortmund

many scenarios for indoor positioning require position estimation not only in two dimensions but in the third dimension as well. This paper presents the expansion of two two-dimensional WLAN fingerprinting localization algorithms based on received signal strength indication (RSSI) to the third dimension. The third dimension is regarded discretely as the floor level. Both algorithms were evaluated in two different test beds. Evaluation results will be presented and discussed.

关键词： Wireless LAN Calibration Fingerprint recognition Floors Testing Indoor environments Inference algorithms Position measurement Fuzzy logic Engines

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Coarse-to-fine particle filters for multi-object human computer interaction

Coarse-to-fine particle filters for multi-object human compu...

引用

ieee international workshop on Intelligent Data Acquisition and Advanced computing systems: Technology and Applications

作者： Matthias Rätsch Clemens Blumer Gerd Teschke Thomas Vetter University of Basel Basel Switzerland University of Applied Sciences Neubrandenburg Neubrandenburg Germany

Efficient motion tracking of faces is an important aspect for human computer interaction (HCI). In this paper we combine the condensation and the wavelet approximated reduced vector machine (W-RVM) approach. Both are joined by the core idea to spend only as much as necessary effort for easy to discriminate regions (Condensation) or vectors (W-RVM) of the feature space, but most for regions with high statistical likelihood to contain objects of interest. We adapt the W-RVM classifler for tracking by providing a probabilistic output. In this paper we utilize condensation for template based tracking of the three-dimensional camera scene. Moreover, we introduce a robust multi-object tracking by extensions to the condensation approach. The novel coarse-to-flne condensation yields a more than 10 times faster tracking than state-of-art detection methods. We demonstrate more natural HCI applications by high resolution face tracking within a large camera scene with an active dual camera system.

关键词： Particle filters Human computer interaction Face detection Object detection Cameras Application software Particle tracking Pixel Layout Conferences

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Parallel and distributed approach for processing large-scale XML datasets

Parallel and distributed approach for processing large-scale...

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international workshop on Grid computing

作者： Zacharia Fadika Michael R. Head Madhusudhan Govindaraju Computer Science Department Binghamton University Binghamton NY USA

An emerging trend is the use of XML as the data format for many distributed scientific applications, with the size of these documents ranging from tens of megabytes to hundreds of megabytes. Our earlier benchmarking results revealed that most of the widely available XML processing toolkits do not scale well for large sized XML data. A significant transformation is necessary in the design of XML processing for scientific applications so that the overall application turn-around time is not negatively affected. We present both a parallel and distributed approach to analyze how the scalability and performance requirements of large-scale XML-based data processing can be achieved. We have adapted the Hadoop implementation to determine the threshold data sizes and computation work required per node, for a distributed solution to be effective. We also present an analysis of parallelism using our Piximal toolkit for processing large-scale XML datasets that utilizes the capabilities for parallelism that are available in the emerging multi-core architectures. multi-core processors are expected to be widely available in research clusters and scientific desktops, and it is critical to harness the opportunities for parallelism in the middleware, instead of passing on the task to application programmers. Our parallelization approach for a multi-core node is to employ a DFA-based parser that recognizes a useful subset of the XML specification, and convert the DFA into an NFA that can be applied to an arbitrary subset of the input. Speculative NFAs are scheduled on available cores in a node to effectively utilize the processing capabilities and achieve overall performance gains. We evaluate the efficacy of this approach in terms of potential speedup that can be achieved for representative XML data sets.

关键词： Large-scale systems XML Parallel processing Process design Performance analysis Scalability Data processing Distributed computing Computer architecture multicore processing

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Zero-Buffer Inter-core Process Communication Protocol for Heterogeneous multi-core Platforms

Zero-Buffer Inter-core Process Communication Protocol for He...

引用

ieee international Conference on Embedded and Real-Time computing systems and Applications (RTCSA)

作者： Yu-Hsien Lin Chiaheng Tu Chi-Sheng Shih Shih-Hao Hung Department of Computer Science and Information Engineering Graduate Institute of Networking and Multimedia National Taiwan University Taipei Taiwan

ISBN: (纸本)9781424449316

Executing functional components in pipeline on heterogeneous multi-core platforms can greatly improve the parallelism but require great amount of data communication among processes and threads. Our studies showed that existing inter-process/thread communication protocols consist of many unnecessary memory copies and prolong the execution of the applications on heterogeneous multi-core platforms. NTU ICPC uses polling-base mail notification to unnecessary context switches, and designs a memory subsystem to manage the input and output data between the senders and receivers. The protocol was implemented and evaluated on heterogeneous multi-core platform for several use scenario including H.264 encoding process. The evaluation results show that the communication overhead on sender side is independent of the data size and that on receiver side is greatly shortened, compared to several inter-process Communication (IPC) protocols including mailbox, message queue, and shared memory. When encoding H.264 video clips, the encoding frame rates increase for more than 30%. Our experiments also showed that the communication overhead accounts 40% to 50% of total execution time in average for H.264 video decoding applications. In this paper, we present the design and implementation of zero-buffer inter-core process communication protocol, named NTU ICPC, to shorten communication overhead for pipeline executed applications on heterogeneous multi-core platforms.

关键词： Protocols Encoding Pipelines Yarn Video sharing Data communication Postal services Context Switches Communication switching

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Parallel Dense Gauss-Seidel Algorithm on many-core Processors

Parallel Dense Gauss-Seidel Algorithm on Many-Core Processor...

引用

ieee international Conference on High Performance computing and Communications (HPCC)

作者： Hadrien Courtecuisse Jérémie Allard INRIA Lille Nord Europe France

The Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited sparsity in the system matrix to extract parallelism. In this paper, we propose to study several parallelization schemes for fully-coupled systems, unable to be parallelized by existing methods, taking advantage of recent many-cores architectures offering fast synchronization primitives. Experimental results on both multi-core CPUs and recent GPUs show that our proposed method is able to fully exploit the available units, whereas trivial parallel algorithms often fail. This method is illustrated by an application in medical intervention planning, where it is used to solve a linear complementary problem (LCP) expressing the contacts applied to a deformable body.

关键词： Gaussian processes High performance computing Parallel processing Concurrent computing Jacobian matrices Computer architecture Equations Pervasive computing Linear systems Europe

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Efficiently migrating real-time systems to multi-cores

Efficiently migrating real-time systems to multi-cores

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international Conference on Emerging Technologies and Factory Automation (ETFA)

作者： Farhang Nemati Moris Behnam Thomas Nolte Mälardalen Real-Time Research Centre Mälardalen University Sweden

ISBN: (纸本)9781424427277

Power consumption and thermal problems limit a further increase of speed in single-core processors. multi-core architectures have therefore received significant interest. However, a shift to multi-core processors is a big challenge for developers of embedded real-time systems, especially considering existing ¿legacy¿ systems which have been developed with uniprocessor assumptions. These systems have been developed and maintained by many developers over many years, and cannot easily be replaced due to the huge development investments they represent. An important issue while migrating to multi-cores is how to distribute tasks among cores to increase performance offered by the multi-core platform. In this paper we propose a partitioning algorithm to efficiently distribute legacy system tasks along with newly developed ones onto different cores. The target of the partitioning is increasing system performance while ensuring correctness.

关键词： Real time systems Partitioning algorithms multicore processing Computer architecture Yarn Timing Resource management Concurrent computing Hardware Energy consumption

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