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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 974 条记录，以下是81-90 订阅

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Design and Implementation of Data Navigator for Heterogeneous multi-core System

Design and Implementation of Data Navigator for Heterogeneou...

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ieee international workshop on Anti-counterfeiting, Security, Identification, ASID

作者： Hu Ge Yukun Song Duoli Zhang Zhenjiao Chen Yan Ma Department of Microelectronics Hefei University of Technology Hefei China The 58th Research Institute of China Electronics Technology Group Corporation Wuxi China

ISBN: (数字)9781665490672

ISBN: (纸本)9781665490689

For a multi-core system with multiple peripherals, the usual communication between cores and data transmission between cores and peripherals is single, and the data transfer cannot be planned, shaped, or congested-controlled. In this research, a Data Navigator that is used to manage data transport in a multi-core system is studied. The Data Navigator consists of two parts: Data Manager and Data Transfer Controller. When so many devices are requested to transmit data, the data manager uses a three-level priority adjustment technique, and the data transfer controller switches to DMA mode and uses the AXI bus to convey the data. The proposed architecture may provide equitable and efficient data transmission in a certain multi-core system environment, balance response speed, complete data shaping, and improve system performance overall, according to experimental results.

关键词： Time-frequency analysis Navigation multicore processing System performance Data transfer Control systems Hardware

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Linearly extensible system based interconnection network for multi-core multi-processor systems 8

Linearly extensible system based interconnection network for...

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8th international Conference on computing for Sustainable Global Development, INDIACom 2021

作者： Gautam, Savita Umar, M. Sarosh Samad, Abdus University Women's Polytechnic F/O Engg. Tech. Aligarh Muslim University Aligarh India Z. H. College of Engg. Tech. Aligarh Muslim University Department of Computer Engineeering Aligarh India

ISBN: (纸本)9789380544434

multicore processor implementation for server, workstations and embedded multicore chips is a challenging task. The design decisions with underlying trends affect the performance of such systems. Conventionally, interconnection networks are designed to connect several nodes, each of them having different cores. However, the on-chip interconnection network between cores becomes a bottleneck as it is being shared by all the cores to cooperate while being solving a given problem. This paper presents a scalable Network-on-Chip architecture which exploits the interconnection network to connect different many core processors. The proposed architecture is designed in analogy to linearly extensible multiprocessor networks which have simple architecture and lesser cost. The introduced architecture is symmetrical in nature and exhibits the desirable properties of similar networks with lesser complexity and cost. A basic (4 x 4), 16-core architecture named as CA network is introduced which is symmetrically extendable at higher level with increasing number of cores. The topological variables such as number of cores, number of links, diameter and bisection width are evaluated for CA network and a comparative study is carried out with Mesh and Torus networks in order to validate the ascendancy of the proposed architecture. The proposed CA network has low diameter, low cost and performs better with lesser number of nodes. It is scalable and expandable easily at higher levels with lesser complexity. © 2021 Bharati Vidyapeeth, New Delhi. Copy Right in Bulk will be transferred to ieee by Bharati Vidyapeeth.

关键词： Topology

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Accelerating Computer Vision Algorithms on Heterogeneous Edge computing Platforms 34

Accelerating Computer Vision Algorithms on Heterogeneous Edg...

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34th ieee workshop on Signal Processing systems (SiPS)

作者： Prakash, Alok Ramakrishna, Nirmala Garg, Kratika Srikanthan, Thambipillai Nanyang Technol Univ Singapore Singapore

ISBN: (纸本)9781728180991

Heterogeneity has become the cornerstone of modern embedded System-on-Chips (SoCs), used in latest smartphones and edge computing platforms to achieve high performance under tight power budgets. Alongside the general purpose multi-core CPUs, such SoCs typically integrate several specialized processing elements such as GPU and DSP to ensure power-efficient execution of specific workloads. In the past, many computer vision algorithms and their kernels have been shown to benefit from execution on GPUs, both in terms of performance and power consumption. Existing work has also demonstrated the benefit of accelerating them simultaneously on multi-core CPUs and discrete as well as integrated GPUs found in PCs and workstations. Recently, authors have also focused on accelerating such applications on heterogeneous embedded SoCs with integrated CPU and GPU. In this paper, we first present an extensive literature review of such efforts and highlight their strengths and limitations. Next, we use the latest state-of-the-art edge computing platform, Odroid-N2, and the older Odroid-XU3 platform, both of which use heterogeneous embedded SoCs, to explore the acceleration of the convolution kernel with different filter sizes and its impact on the KLT tracking algorithm. Lastly, we discuss the challenges and opportunities in leveraging such SoCs for computer vision and other AI applications.

关键词： KLT heterogeneous SoC CPU-GPU

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Heuristic Contention-Free Scheduling Algorithm for multi-core Processor using LET Model 24

Heuristic Contention-Free Scheduling Algorithm for Multi-cor...

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ieee/ACM 24th international Symposium on Distributed Simulation and Real Time Applications (DS-RT)

作者： Igarashi, Shingo Ishigooka, Tasuku Horiguchi, Tatsuya Koike, Ryotaro Azumi, Takuya Saitama Univ Grad Sch Sci & Engn Saitama Japan Hitachi Ltd Ctr Technol Innovat Controls Res & Dev Grp Tokyo Japan

ISBN: (纸本)9781728173436

Embedded systems, e.g., self-driving systems and advanced driver-assistance systems (ADAS), require computing platforms with high computing power and low power consumption. multi-/many-core platforms satisfy these requirements effectively. However, for hard real-time applications, multiple demands on shared resources can impede real-time performance, and memory is one resource that can impair the desired performance significantly. Therefore, it is important that memory access timing be deterministic to facilitate predictability. To realize this, the Logical Execution Time (LET) paradigm is currently attracting attention. This paper proposes a theoretical scheduling method for a model applying the LET paradigm to directed acyclic graph (DAG) nodes for a multi-/many-core platform. The proposed method considers communication timing between nodes and generates a schedule that does not cause communication contentions. In addition, the proposed method attempts to distribute tasks and reduce LET intervals to address increased execution times due to the implementation of the LET paradigm. In the evaluation, we observed that the proposed method improved the schedule length by up to 40%.

关键词： multi-rate DAG multi-/many-core communication contention list-scheduling logical execution time

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Using Structural Similarity and Kolmogorov-Arnold Networks for Anatomical Embedding of Cortical Folding Patterns

Using Structural Similarity and Kolmogorov-Arnold Networks f...

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ieee international Symposium on Biomedical Imaging

作者： Minheng Chen Chao Cao Tong Chen Yan Zhuang Jing Zhang Yanjun Lyu Xiaowei Yu Lu Zhang Tianming Liu Dajiang Zhu Department of Computer Science and Engineering University of Texas at Arlington USA Department of Computer Science Indiana University Indianapolis USA School of Computing University of Georgia USA

ISBN: (数字)9798331520526

ISBN: (纸本)9798331520533

The 3-hinge gyrus (3HG) is a newly defined folding pattern, which is the conjunction of gyri coming from three directions in cortical folding. many studies demonstrated that 3HGs can be reliable nodes when constructing brain networks or connectome since they simultaneously possess commonality and individuality across different individual brains and populations. However, 3HGs are identified and validated within individual spaces, making it difficult to directly serve as the brain network nodes due to the absence of cross-subject correspondence. The 3HG correspondences represent the intrinsic regulation of brain organizational architecture, traditional image-based registration methods tend to fail because individual anatomical properties need to be fully respected. To address this challenge, we propose a novel self-supervised framework for anatomical feature embedding of the 3HGs to build the correspondences among different brains. The core component of this framework is to construct a structural similarity-enhanced multi-hop feature encoding strategy based on the recently developed Kolmogorov-Arnold network (KAN) for anatomical feature embedding. Extensive experiments suggest that our approach can effectively establish robust cross-subject correspondences when no one-to-one mapping exists. The code is available at ***/m1nhengChen/SSE-CortexEmbed.

关键词： Representation learning Codes Adaptive systems Spread spectrum communication Encoding Regulation Reliability Image reconstruction Biomedical imaging

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Flick: Fast and Lightweight ISA-Crossing Call for Heterogeneous-ISA Environments 20

Flick: Fast and Lightweight ISA-Crossing Call for Heterogene...

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47th ACM/ieee Annual international Symposium on Computer Architecture (ISCA)

作者： Cho, Shenghsun Chen, Han Madaminov, Sergey Ferdman, Michael Milder, Peter SUNY Stony Brook Stony Brook NY 11794 USA

ISBN: (纸本)9781728146614

Heterogeneous-ISA multi-core systems have performance and power consumption benefits. Today, numerous system components, such as NVRAMs and Smart NICs, already have built-in processor cores with ISAs different from that of the host CPUs, making many modern systems heterogeneous-ISA multi-core systems. Unfortunately, programming and using such systems efficiently is difficult and requires extensive support from the host operating systems. Existing programming solutions are complex, require dramatic changes to the systems, and often incur significant performance overheads. To address this challenge, we propose Flick: Fast and Lightweight ISA-Crossing Call, for migrating threads in heterogeneous-ISA multi-core systems. By leveraging hardware virtual memory support and standard operating system mechanisms, a software thread can transparently prototype a heterogeneous-ISA multi-core system using FPGAs with off-the-shelf hardware and software to evaluate Flick. Experiments with microbenchmarks and a BFS application show that Flick requires only minor changes to the existing OS and software, and incurs only 18 mu s round trip overhead for migrating a thread through PCIe, which is at least 23x faster than prior work.

关键词： Heterogeneous-ISA multi-core Thread Migration Virtual Memory FPGA

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Optimizing GNN on ARM multi-core Processors

Optimizing GNN on ARM Multi-Core Processors

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ieee international Conference on High Performance computing and Communications (HPCC)

作者： Chaorun Liu Huayou Su Yong Dou Kangkang Chen Yanjie Sun National University of Defense and Technology China

Graph Neural Network (GNN) has shown great success in graph learning, including physics systems, protein interfaces, disease classification, molecular fingerprints, etc. Due to the complexity of the real-world tasks and the big graph datasets, current GNN models become increasingly bigger and more complicated to enhance the learning ability and prediction accuracy. In addition, GNN contains two main major components graph operation and neural network (NN) operation, both are executed alternately during processing. The interleaved complex processing of GNN poses a challenge for many computational platforms, especially for those without accelerators. Current optimization frameworks solely for deep learning or graph computing cannot achieve good performance on GNN. In this work, we first investigate the performance bottlenecks when handling GNN over multi-core processors. Then, we perform a set of optimization strategies to leverage the capability of multi-core processors for GNN processing. Specifically, we build a set of microkernels for graph operations of GNN with assembly instructions that can exploit the capability of SIMD processing units within a core and implement a task allocator based on a greedy algorithm to balance the workloads between the cores of CPU. In addition, we use some strategies to optimize NN operation for GNN, according to the characteristics of NN operation in GNN. Experimental results show that the proposed methods can achieve a maximum of 2.88x and 4.08x performance improvements for various GNN models on Phytium 2000+ and Kunpeng 920 over the state-of-the-art GNN framework.

关键词： Proteins Program processors multicore processing Parallel programming Artificial neural networks Predictive models Graph neural networks

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A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization

A Run-time Tapered Floating-Point Adder/Subtractor Supportin...

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ieee international Symposium on Embedded multicore Socs (MCSoC)

作者： Ashish Reddy Bommana Srinivas Boppu School of Electrical Sciences Indian Institute of Technology Bhubaneswar (IITBBS) India

ISBN: (纸本)9781665465007

In this era of widespread embedded computing, energy efficiency has become the new performance criterion; as a result, accelerator-rich multi-processor system-on-chips are widely utilized in embedded computing hardware. Due to abun-dant and inexpensive computational capacity, computationally intensive machine learning applications have gained a lot of traction and are currently being used in a wide range of application domains. Furthermore, there is an increasing trend toward developing hardware accelerators for machine learning applications for embedded edge devices where performance and energy efficiency are critical. Although floating-point operations are frequently used for accuracy in these hardware accelerators, reduced width floating point formats are also used to reduce hardware complexity and thus power consumption while pre-serving accuracy. Mixed-precision DNN, vectorization techniques, and any-precision DNN concepts have also proven to boost performance, energy efficiency, and memory bandwidth. In this paper, we propose the design of a vectorized floating-point adder/subtractor that can handle arbitrary length floating-point formats with varying exponent and mantissa widths. The whole idea of this paper is to bring flexibility to each layer in a DNN model for arithmetic operations; depending on the requirement of computation of each layer, exponent width and the floating-point format are chosen dynamically. In comparison to existing designs in the literature, the proposed design is $1.69\times$ area and $1.61\times$ power-efficient, and it supports true vectorization with no restrictions on exponent and mantissa widths.

关键词： Performance evaluation Embedded computing Power demand multicore processing Memory management Machine learning Market research

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Memristive Oscillatory Networks for computing: The Chemical Wave Propagation Paradigm 17

Memristive Oscillatory Networks for Computing: The Chemical ...

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17th international workshop on Cellular Nanoscale Networks and their Applications, CNNA 2021

作者： Chatzinikolaou, Theodoros Panagiotis Fyrigos, Iosif-Angelos Ntinas, Vasileios Kitsios, Stavros Bousoulas, Panagiotis Tsompanas, Michail-Antisthenis Tsoukalas, Dimitris Sirakoulis, Georgios Ch. Democritus University of Thrace Department of Electrical and Computer Engineering Xanthi Greece Department of Applied Physics National Technical University of Athens Athens Greece Department of Electronics Engineering Universitat Politecnica de Calatunya Barcelona Spain

ISBN: (纸本)9781665439480

During the last decade, there is an ever-growing concern regarding the future of CMOS technology, as well as the emerging difficulties on handling upcoming technological issues related with silicon transistors' dimensions, electrical power, energy consumption, and last but not least reaching the physical limits of this technology. At the same time, new computing alternatives beyond the classical computing systems, namely von Neumman architectures, are heavily sought after to tackle energy and memory-wall problems. In this talk, we focus on a hybrid analogue computational circuit-level system with unipolar memristor nanodevices connected in oscillatory networks and based on wave-like propagation of information. These methods are inspired by biochemical processes occurring in nature. The proposed insightful electrochemical wave propagation is apparent in many natural and biological systems and is modelled with powerful, inherently parallel computational tools, like Cellular Automata (CAs). This framework enables us to further proceed into realising alternative types of computations executed on the designed, modelled and fabricated memristor nanodevices, which are finally employed for the design and development of wave based electronic computational units. The proposed nanoelectronic memristive oscillatory networks will be in the advantageous position to perform both classical and unconventional calculations, like multi-digit, in memory and neuromorphic, to name a few of them. Thus, we will have a powerful tool targeting beyond the existing von Neumann information processing techniques and alleviating the aforementioned disadvantages associated with them. © 2021 ieee.

关键词： Wave propagation

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CMOS-integrated nanoscale memristive crossbars for CNN and optimization acceleration

CMOS-integrated nanoscale memristive crossbars for CNN and o...

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12th ieee international Memory workshop (IMW)

作者： Li, Can Ignowski, Jim Sheng, Xia Wessel, Rob Jaffe, Bill Ingemi, Jacqui Graves, Cat Strachan, John Paul Hewlett Packard Enterprise Hewlett Packard Labs Palo Alto CA 94304 USA Hewlett Packard Enterprise Silicon Design Lab Palo Alto CA USA

ISBN: (数字)9781728163062

ISBN: (纸本)9781728163062

While memristive crossbars have been reported to offer substantial performance efficiency benefits orders of magnitude above digital processors, there remain high risks in analog computing platforms using emerging non-volatile memory technologies, primarily due to device performance, variability, yield, and interactions with peripheral circuits. We directly integrated CMOS and nanoscale (down to 25 nm) memristors for fully on-chip reading/programming/computing demonstrations. We operate in a low power regime, program with fine control, showing high yield and low variability across our memristive arrays. With the integrated chip, we successfully demonstrated a multi-layer convolutional neural network with MNIST classification accuracy of above 95.3%, demonstrating several concepts in proposed architectures for hybrid analog-digital computing. The ability to tackle NP-hard optimization problems is also experimentally demonstrated with this platform. This work derisks many of the chief concerns for an accelerator based on analog rather than purely digital computing circuits, as well as validating the core elements of a future in-memory computing architecture.

关键词： memristor non-volatile memory in-memory computing analog computing neural networks

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