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检索条件"任意字段=IEEE International Workshop on Multi-/Many-core Computing Systems"

共 974 条记录，以下是911-920 订阅

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RDM+: A New Mac Layer Real-Time Communication Protocol

RDM+: A New Mac Layer Real-Time Communication Protocol

引用

Quality of Service, 2006 14th ieee international workshop on;Princeton,NJ

作者： Mojtaba Sabeghi Mahmoud Naghibzadeh Koen Bertels Computer Engineering Laboratory Delft University of Technnology Delft Netherlands Computer Engineering Department Ferdowsi University of Mashhad Mashhad Iran

many real-time communication protocols have been studied to guarantee the communication requirements of distributed real-time systems. But, current techniques lack all or most of these requirements specially bounded message delivery time. In this paper we have proposed a Mac layer protocol called RDM+ with concepts similar to Round Data Mailer multi layer protocol [1]. Our simulation results show that this new protocol has the potential to be used in today's automotive systems.

关键词： Protocols Propagation delay Communication system control Delay effects Vehicles Radio control Control systems Real time systems Distributed computing Timing

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An Evaluation of Server Consolidation Workloads for multi-core Designs

An Evaluation of Server Consolidation Workloads for Multi-Co...

引用

ieee international workshop/Symposium on Workload Characterization

作者： Natalie Enright Jerger Dana Vantrease Mikko Lipasti Electrical and Computer Engineering Department University of Wisconsin Madison USA Computer Science Department University of Wisconsin Madison USA

While chip multiprocessors with ten or more cores will be feasible within a few years, the search for applications that fully exploit their attributes continues. In the meantime, one sure-fire application for such machines will be to serve as consolidation platforms for sets of workloads that previously occupied multiple discrete systems. Such server consolidation scenarios will simplify system administration and lead to savings in power, cost, and physical infrastructure. This paper studies the behavior of server consolidation workloads, focusing particularly on sharing of caches across a variety of configurations. Noteworthy interactions emerge within a workload, and notably across workloads, when multiple server workloads are scheduled on the same chip. These workloads present an interesting design point and will help designers better evaluate trade-offs as we push forward into the many-core era.

关键词： Costs Application software Yarn Space technology Interference Communication system control Design engineering Computer science Job shop scheduling Sun

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An Architecture for Exploiting multi-core Processors to Parallelize Network Intrusion Prevention

An Architecture for Exploiting Multi-Core Processors to Para...

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Quality of Service, 2006 14th ieee international workshop on;Princeton,NJ

作者： Vern Paxson Robin Sommer Nicholas Weaver Lawrence Berkeley National Laboratory International Computer Science Institute International Computer Science Institute

It is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of (1) the rising sophistication of attacks requiring more complex analysis to detect, (2) the relentless growth in the volume of network traffic that we must analyze, and, critically, (3) the failure in recent years for uniprocessor performance to sustain the exponential gains that for so many years CPUs enjoyed ("Moore's Law"). For commodity hardware, tomorrow's performance gains will instead come from multicore architectures in which a whole set of CPUs executes concurrently. Taking advantage of the full power of multi-core processors for network intrusion prevention requires an in-depth approach. In this work we frame an architecture customized for parallel execution of network attack analysis. At the lowest layer of the architecture is an "Active Network Interface" (ANI), a custom device based on an inexpensive FPGA platform. The ANI provides the inline interface to the network, reading in packets and forwarding them after they are approved. It also serves as the front-end for dispatching copies of the packets to a set of analysis threads. The analysis itself is structured as an event-based system, which allows us to find many opportunities for concurrent execution, since events introduce a natural, decoupled asynchrony into the flow of analysis while still maintaining good cache locality. Finally, by associating events with the packets that ultimately stimulated them, we can determine when all analysis for a given packet has completed, and thus that it is safe to forward the pending packet - providing none of the analysis elements previously signaled that the packet should instead be discarded.

关键词： multicore processing Failure analysis Performance analysis Performance gain Signal analysis Telecommunication traffic Hardware Field programmable gate arrays Dispatching Yarn

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Revisiting Deterministic multithreading Strategies

Revisiting Deterministic Multithreading Strategies

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jorg Domaschka Andreas I. Schmied Hans P. Reiser Franz J. Hauck Institute of Distributed Systems Ulm University Ulm Germany

Deterministic behaviour is a prerequisite for most approaches to object replication. In order to avoid the non-determinism of multithreading, many object replication systems are limited to using sequential method execution. In this paper, we survey existing application-level scheduling algorithms that enable deterministic concurrent execution of object methods. multithreading leads to a more efficient execution on multiple CPUs and multi-core CPUs, and it enables the object programmer to use condition variables for coordination between multiple invocations. In existing algorithms, a thread may only start or resume if there are no potentially nondeterministic conflicts with other running threads. A decision only based on past actions, without knowledge of future behaviour, must use a pessimistic strategy that can cause unnecessary restrictions to concurrency. Using a priori knowledge about future actions of a thread allows increasing the concurrency. We propose static code analysis as a way for predicting the lock acquisitions of object methods.

关键词： multithreading Yarn Scheduling algorithm Concurrent computing Middleware Resumes Java Information analysis Algorithm design and analysis Programming profession

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Domain Decomposition vs. Master-Slave in Apparently Homogeneous systems

Domain Decomposition vs. Master-Slave in Apparently Homogene...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： Cyril Banino-Rokkones Department of Computer and Information Science (IDI) Norwegian University of Science and Technology Trondheim Norway

This paper investigates the utilization of the master-slave (MS) paradigm as an alternative to domain decomposition (DD) methods for parallelizing lattice gauge theory (LGT) models within distributed memory environments. The motivations for this investigation are twofold. First, LGT models are inherently difficult to parallelize efficiently with DD methods. Second, DD methods have proven useful for homogeneous environments, but are impractical for heterogeneous and dynamic environments. Besides, many modern supercomputer architectures that look homogeneous (such as multi-core or SMP), are in fact heterogeneous and dynamic environments We highlight this issue by comparing a traditional first-come first-served MS implementation to a simple but yet efficient selective MS scheduling strategy that automatically accounts for system heterogeneity and variability. Our experimental results with the parallelization of our LGT model, reveal that the selective MS implementation achieves good efficiency, but lacks of scalability. In contrast, the DD method is highly scalable, but at the expense of a poor efficiency. These results open up for a hybrid approach, where the MS and the DD methods would be combined for achieving scalable high performance.

关键词： Master-slave Lattices Concurrent computing Supercomputers Degradation Fault tolerance Message passing Distributed computing Information science Scalability

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Extending multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications

Extending Multicore Architectures to Exploit Hybrid Parallel...

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ieee Symposium on High-Performance Computer Architecture

作者： Hongtao Zhong Steven A. Lieberman Scott A. Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of power dissipation and complexity. Current chip multiprocessors increase throughput by utilizing multiple cores to perform computation in parallel. These designs provide real benefits for server-class applications that are explicitly multi-threaded. However, for desktop and other systems where single-thread applications dominate, multicore systems have yet to offer much benefit. Chip multiprocessors are most efficient at executing coarse-grain threads that have little communication. However, general-purpose applications do not provide many opportunities for identifying such threads, due to frequent use of pointers, recursive data structures, if-then-else branches, small function bodies, and loops with small trip counts. To attack this mismatch, this paper proposes a multicore architecture, referred to as Voltron that extends traditional multicore systems in two ways. First, it provides a dual-mode scalar operand network to enable efficient inter-core communication and lightweight synchronization. Second, Voltron can organize the cores for execution in either coupled or decoupled mode. In coupled mode, the cores execute multiple instruction streams in lock-step to collectively function as a wide-issue VLIW. In decoupled mode, the cores execute a set of fine-grain communicating threads extracted by the compiler. This paper describes the Voltron architecture and associated compiler support for orchestrating bi-modal execution

关键词： multicore processing Yarn Computer architecture Parallel processing Drives Performance gain Power dissipation Throughput Concurrent computing Data structures

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2nd ieee/ACM international workshop on high performance computing for nano-science and technology

2nd IEEE/ACM international workshop on high performance comp...

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2006 ACM/ieee Conference on Supercomputing, SC'06

作者： Ni, Jun

ISBN: (纸本)0769527000

Nanotechnology is an exciting field with many potential applications. Its impact is already being felt in materials, engineering, electronics, medicine, and other disciplines. Current research in nanotechnology requires multi-disciplinary knowledge, not only in sciences and engineering but also in high performance computing (HPC) technology. many nano-science explorations rely on mature, efficient HPC and computational algorithms, practical and reliable numerical methods, and large-scale computing systems. This workshop offers academic researchers, developers, and practitioners an opportunity to discuss various aspects of HPC-related computational methods and problem solving techniques for nano-science and technology research. © 2006 ieee.

关键词： Nanotechnology

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multi-Replication with Intelligent Staging in Data-Intensive Grid Applications 06

Multi-Replication with Intelligent Staging in Data-Intensive...

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7th ieee/ACM international Conference on Grid computing

作者： Machida, Yuya Takizawa, Shin'ichiro Nakada, Hidemoto Matsuoka, Satoshi Tokyo Inst Technol 2-12-1 Ookayama Tokyo 1528550 Japan Natl Inst Adv Ind Sci & Technol Tsukuba Ibaraki 3058568 Japan Natl Inst Informat Tokyo 1018430 Japan

ISBN: (纸本)9781424403431

Existing data grid scheduling systems handle huge data I/O via replica location services coupled with simple staging, decoupled from scheduling of computing tasks. However, when the application/workflow scales, we observe considerable degradations in performance, compared to processing within a tightly-coupled cluster. For example, when numerous nodes access the same set of files simultaneously, major performance degradation occurs even if replicas are used, due to bottlenecks that manifest in the infrastructure. Instead of resorting to expensive solutions such as parallel Me systems, we propose alleviating the situation by tightly coupling replica and data transfer management with computation scheduling. In particular we propose three techniques: (1) dynamic aggregation and 0(l) replication of data-staging requests across multiple nodes using a multi-replication framework, (2) replica-centric scheduling data re-use and time-to-replication as compute scheduling metrics on the grid and (3) overlapped execution of data staging and compute bound tasks. Early benchmark results implemented in our prototype Condor-like grid scheduling system demonstrate that the techniques are quite effective in eliminating much of the overhead in data transfers in many cases.

关键词： Processor scheduling Job shop scheduling Grid computing File systems Databases Concurrent computing Degradation Dynamic scheduling Computer industry Informatics

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Redundancy in multi-core memory-rich application-specific PIM chips

Redundancy in multi-core memory-rich application-specific PI...

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international workshop on Innovative Architecture for Future Generation High Performance Processors and systems

作者： Kogge, Peter M. Brockman, Jay B. Univ Notre Dame Notre Dame IN 46556 USA

ISBN: (纸本)9780769526898

A trend of growing significance in the arena of advanced microprocessor chip design is the inclusion of multiple processor cores onto the same die with significant parts of the memory hierarchy. This is done to reduce both non-recurring design costs and power dissipation, and to get more computational capability and utilization out of the silicon. A side-effect, however is the opportunity to leverage the redundancy offered by these multiple cores to improve both die yield (and thus reduce chip costs) and the longevity of systems employing such chips. This paper discusses the key variables that go into the configuration of such multicore chips where the goal is complete integration with the memory hierarchy in a single part type. The emphasis of the study is on understanding how many cores, and of what complexity, are most appropriate.

关键词： Redundancy

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Extending instant messaging to provide pervasive personal communication

Extending instant messaging to provide pervasive personal co...

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international workshop on System Support for Future Mobile computing Applications, FUMCA 2006

作者： Wei, Li Kilander, Fredrik Jansson, Carl Gustaf Department of Computer and Systems Sciences Swedish Royal Institute of Technology

ISBN: (纸本)0769527299

This paper proposes a personal software architecture to provide a user with a pervasive communication capability. The core of this architecture is a Personal Communication Server (PCS) which bridges between different Instant Messaging networks and extends them with a unified access to the user. A SIP-based implementation of such a communication server is presented, which solves various interoperability problems, and also provides many value-added features, e.g., extended user presence with location information, adaptive communication, better privacy protection, etc. This implementation enables various existing SIP-compatible resources to be re-used and thus simplifies the construction of the proposed software architecture. © 2006 ieee.

关键词： Ubiquitous computing

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