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Introduction to the Special Section on the 2023 ieee International Solid-State circuits Conference (ISSCC)

ieee journal OF SOLID-STATE circuits 2024年第1期59卷 4-7页

作者： Chen, Mike Shuo-Wei Sathe, Visvesh S. Alioto, Massimo Seo, Jae-Sun Shiga, Hidehiro Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90089 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore Cornell Tech Sch Elect & Comp Engn New York NY 10044 USA KIOXIA Corp Yokohama Kanagawa 2478585 Japan

This special section of the ieee journal of Solidstate circuits (JSSC) highlights outstanding papers presented at the 2023 ieee International Solid-State circuits Conference (ISSCC), which was held from February 19 to 23, 2023 in San Francisco, USA, under the conference theme “Building on 70 years of Innovation in Solid-State Circuit Design.” ISSCC is the foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip (SoCs) and offers a unique opportunity for engineers working at the cutting edge of integrated circuit (IC) design and application. The conference includes several technical programs ranging from analog, digital, memory, wireline (WLN)/wireless, and power management circuits and systems with applications in various fields. This JSSC special section highlights selected papers from ISSCC, specifically on topics related to WLN circuits, digital circuit techniques (DCTs), digital architecture and systems (DASs), machine learning (ML) accelerators, and memory circuits.

关键词： Special issues and sections Meetings Solid state circuits

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Delay-Constrained GNR Routing With CNT-Via Insertion in Nano-Scale Designs

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ieee journal on emerging and selected topics in circuits and systems 2024年第3期14卷 371-383页

作者： Yan, Jin-Tai Tainan Natl Univ Arts Grad Inst Sound Technol Tainan 720005 Taiwan

It is well known that graphene nanoribbon (GNR) can be used as interconnects in nano-scale designs. In this paper, given a set of delay-constrained GNR nets in a multiple-layer routing plane, based on the construction of a combined carbon nanotube (CNT)/graphene hetero-structure for CNT-vias between two adjacent layers, an efficient routing algorithm can be proposed to minimize the number of the used layers with satisfying the non-crossing constraints between two GNR nets and the delay constraints on the GNR nets in GNR routing with CNT-via insertion. In the initial assignment, based on the definition of the delay-constrained routing pattern on a GNR net with tight delay constraint and the delay-constrained via path on a GNR net, the delay-constrained routing patterns can be firstly assigned for layer minimization and the delay-driven minimum-length routing paths and the delay-constrained via paths can be further assigned onto the available layers. In the iterative routing, the unrouted GNR nets can be further routed on the available layers and some possible new layers by using one iterative maze-routing and rip-up-and-rerouting process. Compared with the published routing algorithms with no via insertion, the experimental results show that our proposed routing algorithm with CNT-via insertion can insert some CNT-vias and use shorter wirelength to decrease 53.8% and 24.9% of the number of the used layer under reasonable CPU time on the given GNR nets with two different sets of the delay constraints for 8 tested examples on the average, respectively.

关键词： Routing Delays Metals Integrated circuit interconnections Graphene circuits and systems Minimization GNR routing delay constraint layer minimization CNT-Via insertion

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An Overview of Trustworthy AI: Advances in IP Protection, Privacy-Preserving Federated Learning, Security Verification, and GAI Safety Alignment

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ieee journal on emerging and selected topics in circuits and systems 2024年第4期14卷 582-607页

作者： Zheng, Yue Chang, Chip-Hong Huang, Shih-Hsu Chen, Pin-Yu Picek, Stjepan Chinese Univ Hong Kong Sch Sci & Engn Shenzhen 518172 Peoples R China Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Chung Yuan Christian Univ Dept Elect Engn Taoyuan 320314 Taiwan IBM Res Yorktown Hts NY 10598 USA Radboud Univ Nijmegen Inst Comp & Informat Sci NL-6525 EC Nijmegen Netherlands

AI has undergone a remarkable evolution journey marked by groundbreaking milestones. Like any powerful tool, it can be turned into a weapon for devastation in the wrong hands. Understanding that no model is perfect, trustworthy AI is initiated with an intuitive aim to mitigate the harm it can inflict on people and society by prioritizing socially responsible AI ideation, design, development, and deployment towards effecting positive changes. The scope of trustworthy AI is encompassing, covering qualities such as safety, security, privacy, transparency, explainability, fairness, impartiality, robustness, reliability, and accountability. This overview paper anchors on recent advances in four research hotspots of trustworthy AI with compelling and challenging security, privacy, and safety issues. The topics discussed include the intellectual property protection of deep learning and generative models, the trustworthiness of federated learning, verification and testing tools of AI systems, and the safety alignment of generative AI systems. Through this comprehensive review, we aim to provide readers with an overview of the most up-to-date research problems and solutions. By presenting the rapidly evolving factors and constraints that motivate the emerging attack and defense strategies throughout the AI life-cycle, we hope to inspire more research effort into guiding AI technologies towards beneficial purposes with greater robustness against malicious use intent.

关键词： Artificial intelligence Security Data models Protection Integrated circuit modeling Training circuits and systems Privacy Training data Mathematical models Federated learning deep neural network generative AI large language model formal verification safety alignment trustworthy AI model poisoning data poisoning backdoor watermarking fingerprinting security privacy-preservation

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Learned Image Compression With Efficient Cross-Platform Entropy Coding

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ieee journal on emerging and selected topics in circuits and systems 2025年第1期15卷 72-82页

作者： Yang, Runyu Liu, Dong Wu, Feng Gao, Wen Univ Sci & Technol China Key Lab Brain Inspired Intelligent Percept & Cogni MOE Hefei 230027 Peoples R China Peking Univ Sch Comp Sci Beijing 100871 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China

Learned image compression has shown remarkable compression efficiency gain over the traditional image compression solutions, which is partially attributed to the learned entropy models and the adopted entropy coding engine. However, the inference of the entropy models and the sequential nature of the entropy coding both incur high time complexity. Meanwhile, the neural network-based entropy models usually involve floating-point computations, which incur inconsistent probability estimation and decoding failure in different platforms. We address these limitations by introducing an efficient and cross-platform entropy coding method, chain coding-based latent compression (CC-LC), into learned image compression. First, we leverage the classic chain coding and carefully design a block-based entropy coding procedure, significantly reducing the number of coding symbols and thus the coding time. Second, since CC-LC is not based on neural networks, we propose a rate estimation network as a surrogate of CC-LC during the end-to-end training. Third, we alternately train the analysis/synthesis networks and the rate estimation network for the rate-distortion optimization, making the learned latent fit CC-LC. Experimental results show that our method achieves much lower time complexity than the other learned image compression methods, ensures cross-platform consistency, and has comparable compression efficiency with BPG. Our code and models are publicly available at https://***/Yang-Runyu/CC-LC.

关键词： Image coding Estimation Entropy coding Entropy Computational modeling Training Symbols Transforms circuits and systems Time complexity Block-based coding chain coding cross-platform consistency entropy coding learned image compression

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An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing

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ieee journal on emerging and selected topics in circuits and systems 2024年第3期14卷 409-424页

作者： Su, Zhe Ramini, Simone Marcolin, Demetra Coffen Veronesi, Alessandro Krstic, Milos Indiveri, Giacomo Bertozzi, Davide Nowick, Steven M. Univ Zurich Inst Neuroinformat CH-8006 Zurich Switzerland Swiss Fed Inst Technol CH-8057 Zurich Switzerland Univ Ferrara I-44121 Ferrara Italy Univ Manchester Manchester M13 9PL England IHP Leibniz Inst High Performance Microelect D-15236 Frankfurt Germany Univ Potsdam D-14469 Potsdam Germany Columbia Univ New York NY USA

Biological brains are increasingly taken as a guide toward more efficient forms of computing. The latest frontier considers the use of spiking neural-network-based neuromorphic processors for near-sensor data processing, in order to fit the tight power and resource budgets of edge computing devices. However, a prevailing focus on brain-inspired computing and storage primitives in the design of neuromorphic systems is currently bringing a fundamental bottleneck to the forefront: chip-scale communications. While communication architectures (typically, a network-on-chip) are generally inspired by, or even borrowed from, general purpose computing, neuromorphic communications exhibit unique characteristics: they consist of the event-driven routing of small amounts of information to a large number of destinations within tight area and power budgets. This article aims at an inflection point in network-on-chip design for brain-inspired communications, revolving around the combination of cost-effective and robust asynchronous design, architecture specialization for short messaging and lightweight hardware support for tree-based multicast. When validated with functional spiking neural network traffic, the proposed NoC delivers energy savings ranging from 42% to 71% over a state-of-the-art NoC used in a real multi-core neuromorphic processor for edge computing applications.

关键词： Neurons Routing Hardware Edge computing Costs circuits System recovery NoC neuromorphic asynchronous

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Generation Method of Multi-Regional Photovoltaic Output Scenarios-Set Using Conditional Generative Adversarial Networks

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ieee journal on emerging and selected topics in circuits and systems 2023年第3期13卷 861-870页

作者： Song, Ziyuan Huang, Yuehui Xie, Hongbin Li, Xiaofei China Elect Power Res Inst Natl Key Lab Renewable Energy Grid Integrat Beijing 100192 Peoples R China

The uncertainty of photovoltaic (PV) output power has an increasing impact on power balance with the increase of installed capacity. The construction of day-ahead PV output scenarios-set is an important basis for the stochastic optimal scheduling of the power system. For the uncertainty modeling of multi-regional day-ahead PV output, a scenarios-set generation method based on improved conditional generation adversarial network (CGAN) is proposed. This method learns the potential spatio-temporal characteristics of the output power of PV clusters distributed in different regions by convolutional neural networks. Moreover, a mapping relationship between the input PV prediction results and the output scenarios-set is established. Thereafter, the scenarios-set with correlation characteristics for day-ahead multi-regional PV clusters is generated simultaneously. By comparing with the traditional Latin hypercube sampling (LHS) method, the results of the proposed method show the comprehensive advantages in terms of the uncertainty range and the spatial correlation coefficient.

关键词： Training Generators Renewable energy sources Correlation circuits and systems Probability distribution Kernel Conditional generative adversarial networks photovoltaic multi-regional spatial-temporal correlation scenarios-set

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AM⁴: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

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ieee journal on emerging and selected topics in circuits and systems 2023年第1期13卷 408-421页

作者： Garzon, Esteban Lanuzza, Marco Teman, Adam Yavits, Leonid Univ Calabria UNICAL Dept Comp Engn Modeling Elect & Syst DIMES I-87036 Arcavacata Di Rende Italy Bar Ilan Univ Fac Engn EnICS Labs IL-5290002 Ramat Gan Israel

In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-situ, in the same place that the data is located. One of the key emerging technologies that promises to enable such computing-in-memory is spin-transfer torque magnetic tunnel junction (STT-MTJ). This paper proposes AM4, a combined STT-MTJ-based Content Addressable Memory (CAM), Ternary CAM (TCAM), approximate matching (similarity search) CAM (ACAM), and in-memory Associative Processor (AP) design, inspired by the recently announced Samsung MRAM crossbar. We demonstrate and evaluate the performance and energy-efficiency of the AM4-based AP using a variety of data intensive workloads. We show that an AM4-based AP outperforms state-of-the-art solutions both in performance (with the average speedup of about 10 x) and energy-efficiency (by about 60 x on average).

关键词： Associative memory Magnetic tunneling Computer architecture Arrays Writing Junctions circuits and systems Non-von Neumann computer architecture associative processor associative memories MRAM MTJ double-barrier MTJ CAM TCAM emerging memories

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Guest Editorial Memristive circuits and systems for Edge-Computing Applications

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ieee journal on emerging and selected topics in circuits and systems 2022年第4期12卷 717-722页

作者： Sirakoulis, Georgios Ch. Ascoli, Alon Tetzlaff, Ronald Yu, Shimeng Democritus Univ Thrace Dept Elect & Comp Engn Xanthi 69100 Greece Tech Univ Dresden Fac Elect & Comp Engn D-01069 Dresden Germany Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

This Special Issue of the ieee journal on emerging and selected topics in circuits and systems (JETCAS) is devoted to showcase the latest research achievements on memristive circuits and systems with special focus on edge-computing applications. Over the past few years, the field of circuits and systems has witnessed significant changes, which have inevitably accompanied the progressive approach of the CMOS technology aggressive downscaling trend to an unavoidable end, given the clear impossibility to reduce the transistor dimensions below the atomic scale, in the near future. Tremendous efforts are being made in search for novel devices and circuits toward the development of disruptive nanotechnologies, enabling the fabrication of multi-purpose devices and circuits, which would allow to foster sustainable progress in integrated circuit design, despite further shrinking in transistor sizes shall no longer be feasible soon. In this regard, memristors, exhibiting the extraordinary capability to combine, within a single miniaturized 3-D space, data sensing, processing, and storage functionalities, offer a plethora of novel opportunities for integrated circuit design, paving the way toward the conception of multi-purpose CMOS-compatible nano-circuits, which are bound to improve the performance of state-of-theart computing machines.

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Primary-Side Resonant Current-/Voltage-Clamped IPT systems Without Clamping Coil or Isolation Transformer for Inherent CC-to-CV Charging

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2025年第1期13卷 1281-1294页

作者： Ren, Sheng Wang, Xiaoqiang Xu, Jianping Yang, Ping Southwest Jiaotong Univ Sch Elect Engn Minist Educ Chengdu 611756 Peoples R China Southwest Jiaotong Univ Minist Educ Key Lab Magnet Suspens Technol & Maglev Vehicle Chengdu 611756 Peoples R China

A constant current (CC) and constant voltage (CV) inductive power transfer (IPT) charging system has become popular for battery charging applications. To achieve inherent CC-to-CV charging, the primary-side resonant current-/ voltage-clamped IPT systems are proposed in this article. Two configurations of the primary-side resonant current-/voltage-clamped IPT systems are introduced and analyzed based on the two-port network. In the proposed IPT systems, the clamping coil and isolation transformer are not required, which reduce the system cost and design difficulty of the loosely coupled transformer (LCT). By combining IPT topologies with input zero phase angle (ZPA) and load-independent CC or CV output, a family of IPT systems with inherent CC-to-CV charging can be obtained, which significantly simplifies the control complexity. The secondary-side compensation network is a first-order compensation circuit, which reduces the volume and weight of the charging device. Two primary-side resonant current-/voltage-clamped IPT systems are selected to analyze the sensitivity of the parameters to the input impedance, as well as CC and CV outputs. Soft switching and minimized reactive power can be achieved, which reduce the power rating of the power supply and minimizes the switching loss. Finally, experimental prototypes are built to verify the proposed IPT systems.

关键词： Clamps Coils Impedance circuits Voltage Transformers Power electronics Costs Battery chargers Batteries Constant current (CC) constant voltage (CV) current/voltage clamp inductive power transfer (IPT) minimal secondary design

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On Function-Coupled Watermarks for Deep Neural Networks

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ieee journal on emerging and selected topics in circuits and systems 2024年第4期14卷 608-619页

作者： Wen, Xiangyu Li, Yu Jiang, Wei Xu, Qiang Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Peoples R China Harbin Inst Technol Shenzhen Sch Comp Sci & Technol Shenzhen 518055 Guangdong Peoples R China Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu 610054 Sichuan Peoples R China

Well-performed deep neural networks (DNNs) generally require massive labeled data and computational resources for training. Various watermarking techniques are proposed to protect such intellectual properties (IPs), wherein the DNN providers can claim IP ownership by retrieving their embedded watermarks. While promising results are reported in the literature, existing solutions suffer from watermark removal attacks, such as model fine-tuning, model pruning, and model extraction. In this paper, we propose a novel DNN watermarking solution that can effectively defend against the above attacks. Our key insight is to enhance the coupling of the watermark and model functionalities such that removing the watermark would inevitably degrade the model's performance on normal inputs. Specifically, on one hand, we sample inputs from the original training dataset and fuse them as watermark images. On the other hand, we randomly mask model weights during training to distribute the watermark information in the network. Our method can successfully defend against common watermark removal attacks, watermark ambiguity attacks, and existing widely used backdoor detection methods, outperforming existing solutions as demonstrated by evaluation results on various benchmarks. Our code is available at: https://***/cure-lab/Function-Coupled-Watermark.

关键词： Watermarking Artificial neural networks Training Closed box Computational modeling Predictive models Glass box Feature extraction Data models circuits and systems Neural network watermarking backdoor function-coupling robustness

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