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An Encryption Architecture Suitable for on Chip Integration With Sensors

ieee journal on emerging and selected topics in circuits and systems 2021年第2期11卷 395-404页

作者： Hedayatipour, Ava McFarlane, Nicole Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Calif State Univ Long Beach Dept Elect Engn Long Beach CA 90840 USA

This paper demonstrates a hardware encryption algorithm that can be integrated directly with sensors on the same chip. In contrast to using power-hungry microprocessors and software implementations, the encryption algorithm was based on a Lorenz chaotic system and was implemented as time scaling chaotic shift keying (TS-CSK). The coupled differential equations of TS-CSK were implemented using low power integrators, multiplexers, switches, and passive components. Both a single-ended and differential system was developed. The single-ended based system showed no oscillation, while the differential based system demonstrated oscillation. Experimental measurements of the differential system with an integrated temperature sensor demonstrated the ability to encrypt and decrypt the transmitted signal. The differential encryption/decryption system was implemented in 180 nm technology and operated with a 1.8 V power supply and 1.5 mW of power.

关键词： Encryption Sensors Receivers Chaotic communication Transmitters Synchronization Sensor systems Hardware security encryption chaos chaotic ciphering ciphering Internet of Things IoT chaotic circuits and systems security biomedical applications next- generation biomedical devices injectables implantables ingestibles wearables

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D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros

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ieee journal on emerging and selected topics in circuits and systems 2022年第2期12卷 381-392页

作者： Lin, Ming-Guang Huang, Chi-Tse Chuang, Yu-Chuan Chen, Yi-Ta Hsu, Ying-Tuan Chen, Yu-Kai Chou, Jyun-Jhe Liu, Tsung-Te Shih, Chi-Sheng Wu, An-Yeu Natl Taiwan Univ Grad Inst Elect Engn Taipei 10617 Taiwan Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 10617 Taiwan Natl Taiwan Univ Dept Comp Sci Taipei 10617 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 10617 Taiwan

To enable energy-efficient computation for deep neural networks (DNNs) at edge, computing-in-memory (CIM) is proposed to reduce the energy costs during intense off-chip memory access. However, CIM is prone to multiply-accumulate (MAC) errors due to non-idealities of memory crossbars and peripheral circuits, which severely degrade the accuracy of DNNs. In this work, we propose a Data-Driven Non-ideality Aware Training (D-NAT) framework to compensate for the accuracy degradation. The proposed D-NAT framework has the following contributions: 1) We measured a fabricated SRAM-based CIM macro to obtain a data-driven MAC error model (D-MAC-EM). Based on the derived D-MAC-EM, we analyze the impact of the non-idealities on DNN's accuracy. 2) To make DNNs robust to the non-idealities of CIM macros, we incorporate the measured D-MAC-EM into DNN's training procedure. Moreover, we propose a statistical training mechanism to better estimate the gradients of the discrete D-MAC-EM. 3) We investigate trade-offs between quantization range and quantization errors. To mitigate the quantization errors in activations, we introduce extended PACT (E-PACT) that adaptively learns the upper and lower bounds of input activations for each layer. Simulation results show that our proposed D-NAT improves the accuracy of ResNet20, VGG8, ResNet34, and VGG16 by 78.98%, 71.8%, 72.04%, and 57.85%, respectively, which reaches the ideal upper bound of the quantized model. Lastly, the D-NAT framework is validated on an FPGA platform with the fabricated SRAM-based CIM macro chip. Based on the measurement results, D-NAT successfully recovers the accuracy under non-idealities of a real SRAM-based CIM macro.

关键词： Training Quantization (signal) Computational modeling Common Information Model (computing) circuits and systems Semiconductor device measurement Hardware Computing-in-memory (CIM) deep neural network (DNN) non-ideality aware training

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Induction Machine Emulation for Variable Frequency Drive Converter Faults

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL E...

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ieee journal OF emerging AND selected topics IN INDUSTRIAL ELECTRONICS 2023年第3期4卷 734-743页

作者： Tanuku, Gayatri Pillay, Pragasen Concordia Univ Elect & Comp Engn Montreal PQ H3G 1M8 Canada

Voltage in current out models are commonly used for induction machine (IM) emulation. This model does not provide the information of back electromotive force (EMF) and hence cannot be used for open-circuit fault emulation. A current in voltage out model (CIVO) is an alternate IM model where it provides back EMF information. However, the CIVO model cannot be used directly with the conventional emulator configuration. Hence, in this article, a new emulator configuration has been proposed to accommodate the CIVO model. The model is used in a new emulator configuration by incorporating physical emulator parameters. The article further discusses the upgrade of the model considering saturation nonlinearities. The emulator employing such a model mimics the real IM back EMF with high accuracy. The proposed emulator is tested for different gate driver faults, such as single switch and multiple switch open faults, starting and speed changing conditions. The experimental results are validated with a 5 hp machine. Different fault signatures are also identified with the help of the emulator to help with fault diagnosis and localization.

关键词： Circuit faults Integrated circuit modeling Emulation Switching circuits Mathematical models Induction machines Switches Back electromotive force (EMF) emulation fault signatures induction machine (IM) linear amplifier open-circuit switch faults

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An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing

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ieee journal on emerging and selected topics in circuits and systems 2022年第4期12卷 821-834页

作者： Liu, Dingbang Zhou, Haoxiang Mao, Wei Liu, Jun Han, Yuliang Man, Changhai Wu, Qiuping Guo, Zhiru Huang, Mingqiang Luo, Shaobo Lv, Mingsong Chen, Quan Yu, Hao Southern Univ Sci & Technol Minist Educ Sch Microelect Guangdong Prov Engn Res Ctr 3 D Integrat Shenzhen 518055 Peoples R China Southern Univ Sci & Technol Minist Educ Sch Microelect Engn Res Ctr Integrated Circuits Next Generat Comm Shenzhen 518055 Peoples R China Hong Kong Polytech Univ Dept Comp Hong Kong Peoples R China Georgia Inst Technol Dept Elect & Comp Engn Atlanta GA 30332 USA Chinese Acad Sci Shenzhen Inst Adv Technol Shenzhen 518055 Peoples R China

Computing-In-memory(CIM) accelerators have the characteristics of storage and computing integration, which has the potential to break through the limit of Moore's law and the bottleneck of Von-Neumann architecture for convolutional neural networks (CNN) implementation improvement. However, the performance of CIM accelerators is still limited by conventional CNN architectures and inefficient readouts. To increase energy-efficient performance, an optimized CNN model is required and a low-power column parallel readout is necessary for edge-computing hardware. In this work, an ReRAM-based CNN accelerator is designed. Mixed-bit operations from 1 bit to 8 bits are supported by an effective bitwidth configuration scheme to implement Neural Architecture Search (NAS)-optimized layer-wise multi-bit CNNs. Besides, column-parallel readout is achieved with excellent energy-efficient performance by a variation-reduction accumulation mechanism and low-power readout circuits. Additionally, we further explore systolic data reuse in an ReRAM-based PE array. Experiments are implemented on NAS-optimized ResNet-18. Benchmarks show that the proposed ReRAM accelerator can achieve peak energy efficiency of 2490.32 TOPS/W for 1-bit operation and average energy efficiency of 479.37 TOPS/W for 1 similar to 8-bit operations with evaluating NAS-optimized multi-bitwidth CNNs. When compared with the state-of-the-art works, the proposed accelerator shows at least 14.18x improvement on energy efficiency.

关键词： Mixed-bit CNN accelerator ReRAM CIM column parallel readout NAS energy-efficient

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An Integrated Single-Stage Single-Switch Topology With Reduced Nonlinear Components for LED

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL E...

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ieee journal OF emerging AND selected topics IN INDUSTRIAL ELECTRONICS 2023年第1期4卷 317-326页

作者： Yadav, Vinod Kumar Verma, Arun Kumar Yaragatti, Udaykumar R. Malaviya Natl Inst Technol Dept Elect Engn Jaipur 302017 India

This article presents an integrated single-stage single-switch (4S) ac-dc system for LED delivering a high input power factor (IPF) and regulated output. The proposed topology integrates a power factor correction (PFC) converter with a high-frequency dc-dc converter, driven by a modified front-end single-phase Vienna rectifier. The integration results in a single switch prototype, thus decreasing the cost and complexity of the control circuit. The use of fewer diodes in the front-end rectifier reduces the nonlinearity in the proposed topology. First-stage filter capacitors offer a better input dynamics to the PFC stage. The proposed (4S) prototype offers less component counts and minimal input current harmonics. The theoretical and mathematical analysis of the proposed topology is presented. Finally, the proposed (4S) ac-dc system analysis and simulation results have been verified with a 50 W/60 V prototype depicting an IPF of 0.997, total harmonic distortion (THD) of 3.96%, and an efficiency of 90.8%. The presented experimental results coincided with the analysis and comply with IEC61000-3-2 standards.

关键词： Light emitting diodes Topology Integrated circuits Capacitors Inductors Windings Voltage Cuk dimming flyback integrated LED power factor correction (PFC) single stage Vienna

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Online Optimization of Decision Control Variables Ensuring Loss-Minima Tracking in a TAB-Based DC-AC-DC Switching Network

IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN INDUSTRIAL E...

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ieee journal OF emerging AND selected topics IN INDUSTRIAL ELECTRONICS 2024年第3期5卷 893-907页

作者： Dey, Saikat Mallik, Ayan Darmody, Chris Akturk, Akin Arizona State Univ Power Elect & Control Engn Lab PEACE Mesa AZ 85212 USA CoolCAD Elect LLC College Pk MD 20740 USA

This article presents the formulation, implementation, and execution of the switching network loss optimal hybrid phase-duty control strategy for a three-port dc-dc-ac converter realized by triple-active-bridge (TAB) topology. Keeping energy storage integrated solar inverter in hybrid microgrid application as a design target, the converter under study has a 40 V dc input coming from a solar panel, while its dc output port is connected to a 28 V battery, and the ac port is connected to a 120 Vac 60 Hz grid. The work aims at providing an efficient and easy-to-implement solution for incorporating the dynamically varying optimal TAB bridge voltage duty cycle parameters based on the operating load and ac output phase angle condition that ensures the maximum efficiency operation of the high-frequency (HF) switching network. With this purpose, the power losses in the HF switching network (in TAB) are precisely quantified by employing a generalized-harmonic-approximation (GHA) based circuit model. Following that, a detailed mathematical framework is formulated and presented in the paper that synthesizes the polynomial regression models for the optimal duty variables as a nonlinear function of the operating load and ac voltage phase condition. These developed models are implemented inside the digital controller along with the decoupled proportional integral (PI) controllers that control the phase-shifts. With the implementation of the proposed optimal hybrid phase-duty control, the experimental result concludes an average efficiency increment up to 2% compared to the conventional phase shift modulation-oriented TAB control while maintaining an ac voltage total harmonic distortion (THD) of 1.78%.

关键词： Control systems Voltage control Switches Bridge circuits Batteries Load modeling Mathematical models DC-DC-AC three-port converter loss-optimized dc-dc-ac TAB modulation phase-duty control polynomial fitting triple active bridge (TAB) zero-voltage switching (ZVS)

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A Multistep Charge Extractions and Voltage Bias-Flip (MCEBF) Interface Circuit for Piezoelectric Energy Harvesting Enhancement

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2022年第5期10卷 6293-6303页

作者： Teng, Li Wang, Shiying Liang, Junrui Shanghai Tech Univ Sch Informat Sci & Technol Shanghai 201210 Peoples R China Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol Beijing 200050 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Shanghai Engn Res Ctr Energy Efficient & Custom A Shanghai 201210 Peoples R China

In piezoelectric energy harvesting (PEH), interface circuits using synchronous switch actions, including synchronized charge extraction (CE) and/or bias-flip (BF), can achieve much higher energy harvesting (EH) capability, compared with the standard energy harvesting (SEH) bridge rectifier. In this article, a multistep charge extraction and voltage bias-flip (MCEBF) interface circuit is proposed to further enhance the harvesting capability under weakly coupling conditions. The EH enhancement is realized by reducing the dissipation in CE with multiple CE actions and simultaneously enlarging the extracted energy with a BF action. MCEBF can also generate positive and negative voltage rails via buck-boost topology to supply power for double-rail devices. The optimal control method of MCEBF is theoretically derived. In our experiment, under constant deflection excitation, the best MCEBF case offers 487%, 95%, and 49% more harvested power, compared with SEH, synchronous electric charge extraction (SECE), and parallel synchronized switch harvesting on inductor (P-SSHI) interface circuits, respectively. MCEBF also keeps the benefit of load independence as SECE does under weakly coupling conditions.

关键词： Inductors Switches Synchronization Energy harvesting Capacitors Voltage Switching circuits Kinetic energy harvesting multistep interface circuit piezoelectric devices

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A Digital Adaptive Control Method for Optimizing Valley Current of Active Clamp Flyback Converter

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2022年第5期10卷 5749-5761页

作者： Chen, Minggang Xu, Shen Huang, Linlin Sun, Weifeng Shi, Longxing Southeast Univ Natl ASIC Syst Engn Res Ctr Nanjing 210096 Jiangsu Peoples R China

In an active clamp flyback (ACF) converter working in critical mode (CRM), the zero-voltage switching (ZVS) of the main power switch can be realized by the negative valley current, which is related to conduction loss and switching loss. Therefore, how to control the negative valley current will affect the overall efficiency of the system. This article investigates and compares the three existing technologies and summarizes their limitations in practical applications. Therefore, a digital adaptive control method is proposed to regulate the valley current according to different working conditions. Meanwhile, small-signal analysis is performed to ensure the stability of the proposed control method. The proposed control method is verified by a field-programmable gate array (FPGA)-based 12-V, 3-A ACF, and experimental results show that the proposed theoretical model should be accurate and practical and there is an average efficiency improvement of 1.34% compared to conventional control.

关键词： Zero voltage switching Switches Clamps Capacitors Mathematical models Inductance Equivalent circuits Active clamp flyback (ACF) digital adaptive control valley current control zero-voltage switching (ZVS)

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Extending Winding Function Theory to Incorporate Secondary Effects in the Design of Induction Machines and Drives

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2022年第2期10卷 1915-1924页

作者： Ge, Baoyun Liu, Wenbo Dong, Jianning Liu, Mingda C Mot Technol Inc Madison WI 53704 USA Ford Motor Co Dearborn MI 48124 USA Delft Univ Technol Dept Elect Sustainable Energy NL-2628 CD Delft Netherlands Carpenter Technol Corp Philadelphia PA 19601 USA

High-performance electric drive applications necessitate a high fidelity model to predict the terminal characteristics of machines in the design stage to fulfill a system-level evaluation together with the converters. This article interprets winding function theory (WFT) from the field perspective and incorporates secondary effects, such as slotting and iron nonlinearity into it to accurately predict the main flux linkage in induction machines. The method is centered on resolving the magnetic scalar potential on the two sides of the air gap and computes the flux linkage via a winding function. Its performance is benchmarked against 2-D finite-element analysis (FEA) and the state-of-the-art magnetic equivalent circuit (MEC) method. Flux linkage and torque results indicate that the relative error is within 3.1% even in a highly saturated region when comparing to FEA, while MEC using the same circuit network may present a 20% error.

关键词： Windings Air gaps Magnetic circuits Iron Rotors Stator windings Saturation magnetization Flux linkage magnetic circuit network saturation effect slot effect winding function theory (WFT)

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LoRaWAN ESL for Food Retail and Logistics

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ieee journal on emerging and selected topics in circuits and systems 2021年第3期11卷 493-502页

作者： Arnaud, Alfredo Marioni, Martin Ortiz, Mario Vogel, Gisselle Miguez, Matias R. Univ Catolica Uruguay Dept Ingn Montevideo 11600 Uruguay

Electronic shelf labels (ESL, or electronic price tag) are used by retailers for displaying product pricing on shelves substituting printed price tags;each ESL can display not only the price, but also text, and images, and can be remotely updated, configured, and programmed from a central server. Additionally, the emerging IoT paradigm, allows to expand the application horizon. Firstly, this work presents an analysis on how the use of Cloud-connected, intelligent, ESLs can improve food logistics in the complex scenarios of medium and large cities. Then, a low-cost ESL device, using an electronic ink (e-ink) display and the LoRaWAN protocol to communicate with the central server, aimed at price display and innovative applications in food retail and logistics, is presented. Several current consumption and communication distance measurements are shown, and the design and configuration space are explored to optimize battery life and communication reliability in the different food distribution scenarios. The proposed ESL is powered with a 500mA.h LiMnO2 battery that can last for >8 years in a typical application, considering it communicates with a central server once per hour. The developed price tag can dynamically update the price and information for the customer, which in the case of food can be used to minimize spoilage and can easily upgraded to incorporate sensors or smartphone interaction to develop innovative food logistics and marketing practices. Finally, a LoRaWAN time-slot allocation strategy is presented, to minimize collisions when thousand nodes are connected to a single gateway, with a minimum power consumption overhead.

关键词： IoT circuits and systems for food LoRa e-ink

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