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Guest Editorial Special Issue on selected Papers From the ieee Sensors 2019 Conference

ieee SENSORS journal 2021年第8期21卷 9634-9635页

作者： Vida, Rolland Budapest Univ Technol & Econ HSN Lab Budapest Hungary Budapest Univ Technol & Econ Budapest Hungary

ieee Sensors is the flagship conference of the ieee Sensors Council, attracting each year more than 800 paper submissions, on diverse topics related to sensing technologies, sensors devices, systems, and communications. The ieee Sensors 2019 Conference was held in Montreal, QC, Canada, on October 27–30, 2019, and featured a program with 13 regular tracks and three focused sessions. The regular tracks targeted areas such as sensor phenomenology, modeling and evaluation, sensor materials, processing and fabrication (including printing), chemical, electrochemical, and gas sensors, microfluidics and biosensors, optical sensors, physical sensors, temperature, mechanical, magnetic and other sensors, acoustic and ultrasonic sensors, sensor packaging (including flexible materials), sensor networks (including IoT and related areas), emerging sensor applications, sensor systems: signals, processing and interfaces, as well as actuators and sensor power systems. One track was dedicated specifically to sensors in industrial practices. The three focused sessions targeted areas such as engineering in medical diagnostics and therapeutics, biomedical sensors based on electromagnetics, and flexible and printed IoT sensors.

关键词： Special issues and sections Meetings Sensor systems Sensor phenomena and characterization Gas detectors Sensors

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A Low Power Speech Recognition Processor with Precision Recoverable CRNN 16

A Low Power Speech Recognition Processor with Precision Reco...

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16th ieee International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Xue, AnFeng Yan, Han Zhang, RenYuan Wang, XueTao Zhang, Hao Cai, Hao Liu, Bo Southeast University School of Integrated Circuits Wuxi211189 China Nanjing Research Institute of Electronics Technology Nanjing210096 China Southeast University School of Electronic Science and Engineering Nanjing210096 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, Convolutional Recurrent Neural Network (CRNN) is deployed in the speech recognition system for recognition of 5 keywords. We propose an 8-bits quantization scheme to quantize the weights and activations. Cartesian Genetic Programming (CGP) to generate approximate multipliers is proposed to drastically reduce hardware power consumption with only 1.56% loss of accuracy. The proposed partial retraining method compensates for the loss of network accuracy caused by approximate computing, and can basically restore the accuracy to the initial level. Using process library for hardware verification based on synthesis, the proposed speech recognition system can reduce power consumption by 11.6%~24.7%, and reduce area by 10.2%~25.6% with accuracy loss is 0.29%~ 0.55%. © 2022 ieee.

关键词： Recurrent neural networks

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Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography

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ieee journal on emerging and selected topics in circuits and systems 2021年第2期11卷 383-394页

作者： He, Pengzhou Guin, Ujjwal Xie, Jiafeng Villanova Univ Dept Elect & Comp Engn Villanova PA 19085 USA Auburn Univ Dept Elect & Comp Engn Auburn AL 36849 USA

Post-quantum cryptography (PQC) refers to the cryptosystem that can resist the attacks launched from mature quantum computers in the not far future and has recently gained intensive attention from the research community as most of the existing public-key cryptosystems are vulnerable to attacks from quantum computers. Ring-Learning-with-Errors (Ring-LWE)-based scheme is an essential type of the lattice-based PQC due to its strong security proof and ease of implementation. As the latest variant of the Ring-LWE, the binary Ring-LWE (BRLWE)-based scheme possesses even smaller computational complexity and thus is more suitable for resource-constrained applications. However, the existing works have not well covered various aspects related to this new scheme, especially on the low-complexity hardware implementation. In this paper, we aim to present a novel implementation of the BRLWE-based scheme on the hardware platform with very low-complexity with this point of view. To carry out the specified work in a successful manner, we have proposed mainly four layers of coherent interdependent efforts: (i) we have provided the necessary algorithmic derivation process in detail to formulate the desired algorithm for the polynomial multiplication over hybrid fields, which is the major arithmetic component of the BRLWE scheme;(ii) we have presented the corresponding hardware architecture in a thorough format with sufficient description of the internal structures;(iii) we have also provided the complexity analysis and implementation-based comparison to demonstrate the superior performance of the proposed polynomial multiplication over the state-of-the-art design;(iv) finally, we have extended the proposed low-complexity polynomial multiplication to the major operational phase of the BRLWE scheme. We have shown that the proposed BRLWE structure involves significantly lower area-time complexities over the existing design, e.g., the proposed design has at least 66.01% less area-delay pr

关键词： Hardware Complexity theory circuits and systems Computers Quantum computing Elliptic curve cryptography Standards Binary Ring-Learning-with-Errors (BRLWE) scheme field-programmable gate array (FPGA) hardware platform low-complexity polynomial multiplication post-quantum cryptography (PQC)

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Preventing DNN Model IP Theft via Hardware Obfuscation

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ieee journal on emerging and selected topics in circuits and systems 2021年第2期11卷 267-277页

作者： Goldstein, Brunno F. Patil, Vinay C. Ferreira, Victor C. Nery, Alexandre S. Franca, Felipe M. G. Kundu, Sandip Univ Fed Rio de Janeiro COPPE Syst Engn & Comp Sci Program BR-21941914 Rio De Janeiro Brazil Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01002 USA Univ Brasilia UnB Dept Elect Engn BR-70910900 Brasilia DF Brazil

Training accurate deep learning (DL) models require large amounts of training data, significant work in labeling the data, considerable computing resources, and substantial domain expertise. In short, they are expensive to develop. Hence, protecting these models, which are valuable storehouses of intellectual properties (IP), against model stealing/cloning attacks is of paramount importance. Today's mobile processors feature Neural Processing Units (NPUs) to accelerate the execution of DL models. DL models executing on NPUs are vulnerable to hyperparameter extraction via side-channel attacks and model parameter theft via bus monitoring attacks. This paper presents a novel solution to defend against DL IP theft in NPUs during model distribution and deployment/execution via lightweight, keyed model obfuscation scheme. Unauthorized use of such models results in inaccurate classification. In addition, we present an ideal end-to-end deep learning trusted system composed of: 1) model distribution via hardware root-of-trust and public-key cryptography infrastructure (PKI) and 2) model execution via low-latency memory encryption. We demonstrate that our proposed obfuscation solution achieves IP protection objectives without requiring specialized training or sacrificing the model's accuracy. In addition, the proposed obfuscation mechanism preserves the output class distribution while degrading the model's accuracy for unauthorized parties, covering any evidence of a hacked model.

关键词： Computational modeling Training Data models Load modeling Feature extraction Encryption circuits and systems IP protection model obfuscation neural processing unit deep learning

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GEMMV: An LLM-based Automated Performance-Aware Framework for GEMM Verilog Generation

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ieee journal on emerging and selected topics in circuits and systems 2025年

作者： Zhang, Gaoche Zou, Dingyang Sun, Kairui Chen, Zhihuan Wang, Meiqi Wang, Zhongfeng Nanjing University School of Electronic Science and Engineering Nanjing210023 China Shenzhen Campus of Sun Yat-sen University School of Integrated Circuits Shenzhen528406 China

Recent advancements in artificial intelligence (AI) models have intensified the need for specialized AI accelerators. The design of optimized general matrix multiplication (GEMM) module tailored for these accelerators is crucial but time-consuming and expertise-demanding, creating a demand for automating design processes. Large language models (LLMs), capable of generating high-quality designs from human instructions, show great promise in automating GEMM module creation. However, the GEMM module’s vast design space and stringent performance requirements, along with the limitations of datasets and the lack of hardware performance awareness of LLMs, have made previous LLM-based register transfer level (RTL) code generation efforts unsuitable for GEMM design. To tackle these challenges, this paper proposes an automated performance-aware LLM-based framework, GEMMV, for generating high-correctness and high-performance Verilog code for GEMM. This framework utilizes in-context learning based on GPT-4 to automatically generate high-quality and well-annotated Verilog code for different variants of the GEMM. Additionally, it leverages in-context learning to obtain performance awareness by integrating a multi-level performance model (MLPM) with fine-tuned LLMs. The Verilog code generated by this framework reduces latency by 3.1x and improves syntax correctness by 65% and functionality correctness by 70% compared to earlier efforts. © 2011 ieee.

关键词： Hardware-software codesign

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An Integrated Driver with Real-Time Predictive Dead-Time Optimization Technique for GaN-Based Synchronous Buck Converter

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ieee journal of emerging and selected topics in Power Electronics 2025年

作者： Xu, Chengzhi Fu, Peiyuan Liao, Xufeng Zhu, Zhangming Liu, Lianxi Xidian University School of Integrated Circuits Xi’an710071 China School of Integrated Circuits Xi’an710071 China

With the superior figure of merit (FOM), gallium nitride high electron mobility transistors (GaN HEMTs) currently play a critical role in the switched-mode power supplies (SMPS) application with megahertz switching frequency, high power density and efficiency. However, the frequency-dependent dead-time losses during the reverse conduction significantly degrade the conversion efficiency. Reverse conduction can also increase the risk of the bootstrap voltage overcharge. This paper proposes a dead-time optimization technique (DOT) based on predictive VSW detection that can effectively eliminate the reverse conduction. Unlike conventional methods that require multiple cycles to determine the optimal dead-time, the proposed DOT can achieve the optimal dead-time in real-time across a wide range of VIN (24-48 V) and load current (0.1-6 A). A test chip was fabricated in a 0.18 μm BCD process. The experimental results demonstrate that the reverse conduction has been eliminated through zero voltage switching (ZVS) or partial ZVS with a negligible switching node voltage. Furthermore, a 4.3% efficiency improvement in 48 V to 5 V buck converter (IL = 6 A) is achieved with the proposed DOT. © 2013 ieee.

关键词： High electron mobility transistors

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Coupled-Inductor-Based Dual Active Bridge Converter With Soft Switching Capability and Low Component Count

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2022年第4期10卷 4771-4782页

作者： Xu, Guo Wang, Jialei Wang, Hui Liu, Yonglu Liu, Dong Su, Mei Cent South Univ Sch Automat Changsha 410083 Peoples R China Hunan Prov Key Lab Power Elect Equipment & Grid Changsha 410083 Peoples R China Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD S Yorkshire England

A coupled-inductor-based dual active bridge (DAB) converter with soft switching capability and low component count is proposed in this article. Under wide-input voltage range application, it only utilizes four active switches to achieve voltage regulation and can behave like the current-fed DAB (CF-DAB) converter. In addition, three magnetic components, including the input dc inductor, the transformer, and the leakage inductor, can all be integrated into one coupled inductor, thus reducing the magnetic component count. With the coupled-inductor structure, the voltage of the half bridge capacitor at the output side can be automatically changed according to different duty cycle. Consequently, the voltage matching at the two ports of the equivalent leakage inductor will always be satisfied by controlling the input capacitor voltage with the adopted pulsewidth modulation (PWM). Based on the detailed analysis of the working modes, power transfer characteristics, and zero-voltage switching (ZVS) conditions, full load range ZVS can be mathematically obtained, which shows that the full load range ZVS capability is an intrinsic feature of the proposed converter and is not related to the converter inductance values. Furthermore, the magnetic integration and parameter design are analyzed in detail. Finally, experimental results are provided to demonstrate the effectiveness of the proposed solution.

关键词： Inductors Bridge circuits Zero voltage switching Pulse width modulation Capacitors Voltage control Topology Coupled inductor dual active bridge (DAB) low component count zero-voltage switching (ZVS)

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Two-Stage Factorized Power Architecture DC-DC Converter for Spacecraft Secondary Power Supply System

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2022年第5期10卷 5392-5413页

作者： Wang, Lei Zhang, Donglai Yang, Yungang Li, Hongzhu Harbin Inst Technol Shenzhen Power Elect & Mot Control Res Ctr Shenzhen 518055 Peoples R China Liaoning Tech Univ Fac Elect & Control Engn Huludao 125105 Peoples R China

In this article, we propose a two-stage factorized power architecture (FPA) dc-dc converter, which caters to applications that require high efficiency, high power density, low ripple, and high dynamic response of space-borne low-voltage and high-current power supply. The first-stage 48 V intermediate bus converter (IBC) adopts the six-phase interleaving magnetic integration buck converter (IMIBC). A new array high symmetry multi-phase coupled inductor (CI) is constructed, and a general zero-voltage switching (ZVS) control strategy is proposed. The designed IBC provides 2.4 kW power with a density of up to 1400 W/in3 and efficiency up to 97.15%. The second-stage point of load converter (POLC) adopts the four-phase interleaving magnetic integration LLC dc/dc transformer (DCX). A new method of current sharing, which is based on the inverse coupling resonant inductor, is proposed. This method yields good current sharing under a 15% mismatch of resonance parameters. A highly symmetrical four-phase resonant CI and a four-phase magnetic integration transformer are developed;the design of magnetic components is optimized by constructing a high-precision magnetic circuit mode. The designed POLC has a power density of up to 700 W/in3 and an efficiency of up to 97.1%. Finally, the experimental prototype is fully tested against a similar type of Vicor's products. According to the results, the power supply designed in this article has several benefits with regard to efficiency, power density, transient response speed, and ripple.

关键词： Magnetic resonance Inductors Transformers Power supplies Magnetic circuits Power system measurements Magnetic switching Current sharing high efficiency and high-power density interleaving magnetic integration low-voltage and high-current satellite power supply

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Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security

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ieee journal on emerging and selected topics in circuits and systems 2021年第2期11卷 228-251页

作者： Liu, Wenye Chang, Chip-Hong Wang, Xueyang Liu, Chen Fung, Jason M. Ebrahimabadi, Mohammad Karimi, Naghmeh Meng, Xingyu Basu, Kanad Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Intel Corp Hillsboro OR 97124 USA Univ Maryland Baltimore Cty Dept Comp Sci & Elect Engn Baltimore MD 21250 USA Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

The last decade has witnessed remarkable research advances at the intersection of machine learning (ML) and hardware security. The confluence of the two technologies has created many interesting and unique opportunities, but also left some issues in their wake. ML schemes have been extensively used to enhance the security and trust of embedded systems like hardware Trojans and malware detection. On the other hand, ML-based approaches have also been adopted by adversaries to assist side-channel attacks, reverse engineer integrated circuits and break hardware security primitives like Physically Unclonable Functions (PUFs). Deep learning is a subfield of ML. It can continuously learn from a large amount of labeled data with a layered structure. Despite the impressive outcomes demonstrated by deep learning in many application scenarios, the dark side of it has not been fully exposed yet. The inability to fully understand and explain what has been done within the super-intelligence can turn an inherently benevolent system into malevolent. Recent research has revealed that the outputs of Deep Neural Networks (DNNs) can be easily corrupted by imperceptibly small input perturbations. As computations are brought nearer to the source of data creation, the attack surface of DNN has also been extended from the input data to the edge devices. Accordingly, due to the opportunities of ML-assisted security and the vulnerabilities of ML implementation, in this paper, we will survey the applications, vulnerabilities and fortification of ML from the perspective of hardware security. We will discuss the possible future research directions, and thereby, sharing a roadmap for the hardware security community in general.

关键词： Integrated circuits Hardware Security Integrated circuit modeling Trojan horses Support vector machines Computational modeling Machine learning deep learning hardware security hardware Trojan counterfeit IC physically unclonable functions malware detection edge AI cloud FPGA physical attacks side-channel attacks adversarial examples

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Comparative Study of Small-Signal Stability Under Weak AC System Integration for Different VSCs

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2021年第4期9卷 4482-4499页

作者： Lu, Xiaojun Xiang, Wang Lin, Weixing Wen, Jinyu Huazhong Univ Sci & Technol State Key Lab Adv Electromagnet Engn & Technol Wuhan 430074 Peoples R China Univ Strathclyde Dept Elect & Elect Engn Glasgow G1 1XW Lanark Scotland TBEA Sunoasis Co Ltd Urumqi 830011 Peoples R China

Voltage source converters (VSCs) with self-commutation ability are suitable for interconnecting weak ac systems. This article conducts a comparative study of the small-signal stability characteristics for three typical VSCs, namely, the two-level VSCs (TL-VSCs), the half-bridge modular multilevel converters (HB-MMCs), and the hybrid MMCs (HY-MMCs), under weak ac system integration with special consideration on both inverter and rectifier operation. The frequency responses based on impedance models are compared using the frequency-domain analysis. The oscillation frequencies and mainly participated state variables of the unstable modes are compared using root locus and participation factor analysis in the time domain. Proper parameter retuning approaches for stability enhancement are proposed. The above analysis is adequately validated by electromagnetic simulations.

关键词： Stability analysis Power conversion Voltage control Equivalent circuits Voltage measurement Power system stability HVDC transmission modular multilevel converter (MMC) small-signal model small-signal stability weak ac system

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