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A Single Voltage-Balancing Gate Driver Combined With Limiting Snubber circuits for Series-Connected SiC MOSFETs

ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2020年第1期8卷 465-474页

作者： Wang, Rui Liang, Lin Chen, Yu Kang, Yong Huazhong Univ Sci & Technol Sch Elect & Elect Engn Wuhan 430074 Peoples R China

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are required to be connected in series to meet the high-voltage requirement since the blocking voltage of a single device is limited. In order to solve the voltage unbalancing problem in such a series-connection application, a single voltage-balancing gate driver combined with limiting Snubber circuits is proposed in this article. This gate driver only requires one standard driver circuit to drive two series-connected SiC MOSFETs by adding simple coupling circuits, and limiting Snubber circuits are applied for voltage balancing, and thus, low-cost, simple structure and high reliability are acquired. The analysis is given to demonstrate the working process of such a circuit structure, and the key parameters' design and setting are focused on. In the LTspice simulation of two SiC MOSFETs in series, the proposed gate driver shows good voltage balancing performance as the power loop current increasing. Besides, the branch of series-connected SiC MOSFETs is in reliable ON- or OFF-state during steady process. Finally, the experimental results further verify the performance of proposed single voltage-balancing gate driver.

关键词： Series connected silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) single gate driver voltage balancing

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ieee circuits and systems Society Information

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ieee journal on emerging and selected topics in circuits and systems 2023年第2期13卷 C3-C3页

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Introduction to the Special Issue on the 1st ieee International Conference on Artificial Intelligence circuits and systems (AICAS 2019)

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ieee journal on emerging and selected topics in circuits and systems 2019年第4期9卷 595-597页

作者： Chang, Robert Chen-Hao Lee, Gwo Giun (Chris) Delbruck, Tobi Valle, Maurizio Natl Chung Hsing Univ Taichung 40227 Taiwan Natl Cheng Kung Univ Tainan 70101 Taiwan Univ Zurich CH-8057 Zurich Switzerland Swiss Fed Inst Technol CH-8057 Zurich Switzerland Univ Genoa I-16145 Genoa Italy

This issue of the ieee journal on emerging and selected topics in circuits and systems (JETCAS) includes some of the highlights of the best articles from the 1st ieee International Conference on Artificial Intelligence circuits and systems (AICAS 2019), which was held at the Ambassador Hotel Hsinchu, Taiwan, on March 18-20, 2019. Artificial Intelligence (AI) is driving the new revolution of not only information technology but also all other industries. New algorithms and application systems are introduced with the power of AI. New computing platforms are required to support the emerging AI algorithms and applications, from cloud servers to edge devices, from system level to circuit level. Facing this new challenge and opportunity, the first AICAS was launched and fully sponsored by ieee circuits and systems Society (CASS). It is established to facilitate the state-of-the-art research, innovation, and development activities at the frontiers of AI circuits and systems. It is an ideal forum for allowing academia and industry from international communities to exchange experiences, demonstrate their results and further advance AI technologies on circuits and systems.

关键词： Special issues and sections Meetings Artificial intelligence

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Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations

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ieee journal on emerging and selected topics in circuits and systems 2020年第2期10卷 149-163页

作者： Zhang, Chuan Ueng, Yeong-Luh Studer, Christoph Burg, Andreas Southeast Univ LEADS Nanjing 211189 Peoples R China Southeast Univ Natl Mobile Commun Res Lab Nanjing 211189 Peoples R China Southeast Univ Quantum Informat Ctr Nanjing 211189 Peoples R China Purple Mt Labs Nanjing 211189 Peoples R China Natl Tsing Hua Univ Dept Elect Engn Hsinchu 300 Taiwan Cornell Tech Sch Elect & Comp Engn New York NY 10044 USA Cornell Univ Dept Elect & Comp Engn Ithaca NY 14850 USA Swiss Fed Inst Technol Dept Informat Technol & Elect Engn D ITET CH-8092 Zurich Switzerland Ecole Polytech Fed Lausanne Telecommun Circuits Lab CH-1015 Lausanne Switzerland

The communication industry is rapidly advancing towards 5G and beyond 5G (B5G) wireless technologies in order to fulfill the ever-growing needs for higher data rates and improved quality-of-service (QoS). emerging applications require wireless connectivity with tremendously increased data rates, substantially reduced latency, and growing support for a large number of devices. These requirements pose new challenges that can no longer be efficiently addressed by conventional approaches. Artificial intelligence (AI) is considered as one of the most promising solutions to improve the performance and robustness of 5G and B5G systems, fueled by the massive amount of data generated in 5G and B5G networks and the availability of powerful data processing fabrics. As a consequence, a plethora of research on AI-based communication technologies has emerged recently, promising higher data rates and improved QoS with affordable implementation overhead. In this overview paper, we summarize the state-of-the-art of AI-based 5G and B5G techniques on the algorithm, implementation, and optimization levels. We shed light on the advantages and limitations of AI-based solutions, and we provide a summary of emerging techniques and open research problems.

关键词： Artificial intelligence fifth-generation (5G) and beyond 5G (B5G) detection and precoding channel coding baseband processing model uncertainties localization

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An Estimation Method for Lateral Temperature Gradient on Chip Surface of Power Semiconductor Devices

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ieee journal of emerging and selected topics in Power Electronics 2025年

作者： Pan, Maoyang Deng, Erping Wang, Xia Zhao, Yushan Sun, Hongyu Yan, Yuxing Dong, Yunxia Huang, Yongzhang North China Electric Power University State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources Beijing102206 China Hefei University of Technology State Key Laboratory of High-Efficiency and High-Quality Conversion for Electric Power Hefei230009 China Nanjing NARI Semiconductor Co. Ltd Nanjing211100 China

Nowadays, serious lateral temperature gradient across the chip surface can significantly reduce the lifetime of the power semiconductor devices. Currently, the primary methods for extracting lateral temperature gradient on chip surface include infrared camera and finite element simulation. However, the former requires destroying the package, while the latter can be time-consuming and labor-intensive, with challenges in ensuring accuracy. In this paper, the expression of lateral temperature gradient is derived. Then influencing factors and their implications are also investigated. Finally, taking the common three types of wire-bonded power semiconductor devices for example, a method for estimating lateral temperature gradient is proposed. The effectiveness and accuracy of the method is validated by experiment, showing agreement within 13% for discrete devices and 1% for modules. Despite validation requires destructive package for infrared measurements, subsequent applications enable nondestructive estimation through pre-calibrated effectiveness factors that depend on power and device type. In practical applications, this method helps facilitate the effective prevention or mitigation of failure risks associated with lateral temperature gradient without decapsulation. Theoretically, it contributes to advancing failure mechanism analysis and helps manufacturers improve the device reliability. © 2013 ieee.

关键词： Power integrated circuits

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A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS

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ieee journal on emerging and selected topics in circuits and systems 2020年第3期10卷 283-294页

作者： Zhu, Haozhe Chen, Chixiao Liu, Shiwei Zou, Qiaosha Wang, Mingyu Zhang, Lihua Zeng, Xiaoyang Richard Shi, C. -J. Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China Fudan Univ Shanghai Engn Res Ctr AI & Robot Shanghai 200433 Peoples R China Fudan Univ Inst Brain Inspired Circuits & Syst Shanghai 201203 Peoples R China Univ Washington Dept Elect & Comp Engn Seattle WA 98195 USA

This article presents a communication-aware processing-in-memory deep neural network accelerator, which implements an in-memory entry-counting scheme for low bit-width quantized multiplication-and-accumulations (MACs). To maintain good accuracy on ImageNet, the proposed design adopts a full-stack co-design methodology, from algorithms, circuits to architectures. In the algorithm level, an entry-counting based MAC is proposed to fit the learned step-sized quantization scheme, and exploit the sparsity of both activations and weights intrinsically. In the circuit level, content addressable memory cells and multiplexed arrays are developed in the processing-in-memory macro. In the architecture level, the proposed design is compatible with different stationary dataflow mappings, further reducing the memory access. An in-memory entry-counting silicon prototype and its entire peripheral circuits are fabricated in 65nm LP CMOS technology with an active area of 0.76 x times 0.66 mm(2). The 7.36-Kb processing-in-memory macro with 128 search entries can reduce the multiplication number by 12.8x . The peak throughput is 3.58 GOPS, achieved at a clock rate of 143MHz and a power supply of 1.23V. The peak energy efficiency of the processing-in-memory macro is 11.6 TOPS/W, achieved at a clock rate of 40MHz and a power supply of 1.01V. Note that the physical design of the entry-counting memory is completed in a standard digital placement and routing flow by augmenting the library with two dedicated memory cells. A 3-bit quantized ResNet-18 on the ImageNet dataset is performed, where the top-1 accuracy is 64.4%.

关键词： Neural network accelerator processing-in-memory dataflow CAM algorithm-circuit codesign

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Libraries of Approximate circuits: Automated Design and Application in CNN Accelerators

Libraries of Approximate Circuits: Automated Design and Appl...

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2nd ieee International Conference on Artificial Intelligence circuits and systems (AICAS)

作者： Mrazek, Vojtech Sekanina, Lukas Vasicek, Zdenek Brno Univ Technol Fac Informat Technol Innovat Ctr Excellence IT4 Brno 60190 Czech Republic

Libraries of approximate circuits are composed of fully characterized digital circuits that can be used as building blocks of energy-efficient implementations of hardware accelerators. They can be employed not only to speed up the accelerator development but also to analyze how an accelerator responds to introducing various approximate operations. In this paper, we present a methodology that automatically builds comprehensive libraries of approximate circuits with desired properties. Target approximate circuits are generated using Cartesian genetic programming. In addition to extending the EvoApprox8b library that contains common approximate arithmetic circuits, we show how to generate more specific approximate circuits;in particular, MxN-bit approximate multipliers that exhibit promising results when deployed in convolutional neural networks. By means of the evolved approximate multipliers, we perform a detailed error resilience analysis of five different ResNet networks. We identify the convolutional layers that are good candidates for adopting the approximate multipliers and suggest particular approximate multipliers whose application can lead to the best trade-offs between the classification accuracy and energy requirements. Experiments are reported for CIFAR-10 and CIFAR-100 data sets.

关键词： Optimization Hardware acceleration Error analysis Genetic programming Convolutional neural networks Libraries Circuit synthesis Approximate circuit genetic programming convolutional neural network hardware accelerator optimization

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Multibranch Inductance Extraction Procedure for Multichip Power Modules

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2020年第1期8卷 272-285页

作者： Shahabi, Ali Lemmon, Andrew N. Univ Alabama Dept Elect & Comp Engn Tuscaloosa AL 35401 USA

This article presents a measurement-based technique for estimating the parasitic inductances associated with the interconnection structures of a multichip power module (MCPM) at a finer granularity than has been previously demonstrated. The technique introduced here makes it possible to determine an estimate of the interconnect inductances at each individual die position within the module geometry. For this purpose, this technique leverages the measured input impedance of an MCPM in the frequency domain, which has been carefully shaped by employing discrete capacitors in place of a semiconductor die. An example of the proposed technique is provided for an MCPM with four die positions per switch position. The provided theoretical formulation is verified by its application to a physical test subject, which is designed to represent a generic MCPM. Owing to the efficiency of this extraction technique and the possibility of providing direct empirical validation for FEA-obtained estimates, the proposed approach is expected to be of particular interest to MCPM designers for use in design optimization.

关键词： Inductance Switches Equivalent circuits Semiconductor device measurement MOSFET Geometry Integrated circuit interconnections Interconnection inductance multichip power module (MCPM) parasitic inductance extraction

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Introducing ieee Collabratec

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ieee journal on emerging and selected topics in circuits and systems 2023年第2期13卷 640-640页

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Monolithic Integration of SiC Power BJT and Small-Signal BJTs for Power ICs

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2020年第1期8卷 24-30页

作者： Liang, Shiwei Wang, Jun Deng, Linfeng Fang, Fang Shen, Z. John Hunan Univ Coll Elect & Informat Engn Changsha 410082 Hunan Peoples R China Illinois Inst Technol Dept Elect & Comp Engn Chicago IL 60616 USA

Monolithic integration of power transistor and specific functional integrated circuits (power ICs) offers unique advantages for wide bandgap power devices. However, few publications have reported the power ICs based on SiC because of several challenging problems such as fabrication process and cost. This paper explores the monolithic integration possibility of 4H-SiC lateral small-signal bipolar junction transistors (BJTs) and vertical power BJT without extra mask or processing step other than Vanadium isolation implantation. A new monolithic power integration architecture is proposed and optimized using TCAD simulations first, and then both the vertical and lateral SiC BJT types are fabricated on the same wafer using the standard power BJT process to experimentally verify the feasibility of the monolithic integration method. The SiC power BJT demonstrates a breakdown voltage of 1320 V and a peak common-emitter current gain of 13.1 while the lateral SiC BJT demonstrated a breakdown voltage of 25 V and a peak common-emitter current gain of 3.8 at room temperature. While the device performance can be further improved, the fact that they can be successfully fabricated on the same wafer without much process modification shows a great promise of realizing monolithic SiC power ICs, which will greatly benefit the next-generation power electronics systems.

关键词： Silicon carbide Monolithic integrated circuits Electric fields Vanadium Numerical models Power transistors Bipolar junction transistor (BJT) functional integration (FI) power integration silicon carbide smart power devices

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