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Toward Remote Sensing Image Retrieval Under a Deep Image Captioning Perspective

ieee journal OF selected topics IN APPLIED EARTH OBSERVATIONS AND REMOTE SENSING 2020年 13卷 4462-4475页

作者： Hoxha, Genc Melgani, Farid Demir, Begum Univ Trento Dept Informat Engn & Comp Sci I-38123 Trento Italy Tech Univ Berlin Fac Elect Engn & Comp Sci D-10623 Berlin Germany

The performance of remote sensing image retrieval (RSIR) systems depends on the capability of the extracted features in characterizing the semantic content of images. Existing RSIR systems describe images by visual descriptors that model the primitives (such as different land-cover classes) present in the images. However, the visual descriptors may not be sufficient to describe the high-level complex content of RS images (e.g., attributes and relationships among different land-cover classes). To address this issue, in this article, we present an RSIR system that aims at generating and exploiting textual descriptions to accurately describe the relationships between the objects and their attributes present in RS images with captions (i.e., sentences). To this end, the proposed retrieval system consists of three main steps. The first step aims to encode the image visual features and then translate the encoded features into a textual description that summarizes the content of the image with captions. This is achieved based on the combination of a convolutional neural network with a recurrent neural network. The second step aims to convert the generated textual descriptions into semantically meaningful feature vectors. This is achieved by using the recent word embedding techniques. Finally, the last step estimates the similarity between the vectors of the textual descriptions of the query image and those of the archive images, and then retrieve the most similar images to the query image. Experimental results obtained on two different datasets show that the description of the image content with captions in the framework of RSIR leads to an accurate retrieval performance.

关键词： Visualization Image retrieval Feature extraction Semantics Integrated circuits Recurrent neural networks Remote sensing Convolutional neural network deep learning image captioning image retrieval recurrent neural network remote sensing semantic gap

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GEMMV: An LLM-based Automated Performance-Aware Framework for GEMM Verilog Generation

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ieee journal on emerging and selected topics in circuits and systems 2025年

作者： Zhang, Gaoche Zou, Dingyang Sun, Kairui Chen, Zhihuan Wang, Meiqi Wang, Zhongfeng Nanjing University School of Electronic Science and Engineering Nanjing210023 China Shenzhen Campus of Sun Yat-sen University School of Integrated Circuits Shenzhen528406 China

Recent advancements in artificial intelligence (AI) models have intensified the need for specialized AI accelerators. The design of optimized general matrix multiplication (GEMM) module tailored for these accelerators is crucial but time-consuming and expertise-demanding, creating a demand for automating design processes. Large language models (LLMs), capable of generating high-quality designs from human instructions, show great promise in automating GEMM module creation. However, the GEMM module’s vast design space and stringent performance requirements, along with the limitations of datasets and the lack of hardware performance awareness of LLMs, have made previous LLM-based register transfer level (RTL) code generation efforts unsuitable for GEMM design. To tackle these challenges, this paper proposes an automated performance-aware LLM-based framework, GEMMV, for generating high-correctness and high-performance Verilog code for GEMM. This framework utilizes in-context learning based on GPT-4 to automatically generate high-quality and well-annotated Verilog code for different variants of the GEMM. Additionally, it leverages in-context learning to obtain performance awareness by integrating a multi-level performance model (MLPM) with fine-tuned LLMs. The Verilog code generated by this framework reduces latency by 3.1x and improves syntax correctness by 65% and functionality correctness by 70% compared to earlier efforts. © 2011 ieee.

关键词： Hardware-software codesign

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Topology and Control Method of a Single-Cell Matrix-Type Solid-State Transformer

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2020年第3期8卷 2302-2312页

作者： Wang, Hui Zhang, Yichun Sun, Yao Zheng, Minghui Liang, Xiao Zhang, Guanguan Tan, Kaiyuan Feng, Jianghua Cent South Univ Sch Automat Changsha 410083 Peoples R China Wasion Grp Co Ltd Dept New Technol Res Changsha 410205 Peoples R China SUNY Buffalo Dept Mech & Aerosp Engn Buffalo NY 14260 USA SUNY Buffalo Dept Civil Struct & Environm Engn Buffalo NY 14260 USA Shandong Univ Sch Control Sci & Engn Jinan 250013 Peoples R China CRRC Zhuzhou Inst Co Ltd Zhuzhou 412001 Peoples R China

Aiming at fulfilling the desirable features of compact structure, high efficiency, high reliability, and multifunctionality for the solid state transformers (SSTs), a single-cell matrix-type SST as well as its control method is proposed as the interface between the medium-voltage (MV) and the low-voltage (LV) levels for direct MV AC to LV AC conversion. To achieve zero voltage switching (ZVS) at both the MV and LV sides, a modulation scheme to construct the special resonant currents during the dead time by actively controlling the MV and LV side gate signals is implemented. Furthermore, the ZVS conditions of the MV and LV side bridges are analyzed, and system parameters are properly designed to ensure full range ZVS operation. A 1-kW SST prototype is developed to verify the functionality and effectiveness of the proposed methods. The experiments show that sinusoidal input and output, bidirectional power flow capability, and ZVS at both sides over wide input voltage and load ranges are achieved with the nominal efficiency of 96.1%. The experimental results match the theoretical analysis and the simulation results well.

关键词： Zero voltage switching Topology Bridge circuits Reliability Voltage control Density measurement Power system measurements Direct ac-ac power conversion matrix-type SST series resonant converter (SRC) solid state transformer (SST) zero voltage switching (ZVS)

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Eyeriss v2: A Flexible Accelerator for emerging Deep Neural Networks on Mobile Devices

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ieee journal on emerging and selected topics in circuits and systems 2019年第2期9卷 292-308页

作者： Chen, Yu-Hsin Yange, Tien-Ju Emer, Joel S. Sze, Vivienne MIT Cambridge MA 02139 USA Nvidia Westford MA 01886 USA

A recent trend in deep neural network (DNN) development is to extend the reach of deep learning applications to platforms that are more resource and energy-constrained, e.g., mobile devices. These endeavors aim to reduce the DNN model size and improve the hardware processing efficiency and have resulted in DNNs that are much more compact in their structures and/or have high data sparsity. These compact or sparse models are different from the traditional large ones in that there is much more variation in their layer shapes and sizes and often require specialized hardware to exploit sparsity for performance improvement. Therefore, many DNN accelerators designed for large DNNs do not perform well on these models. In this paper, we present Eyeriss v2, a DNN accelerator architecture designed for running compact and sparse DNNs. To deal with the widely varying layer shapes and sizes, it introduces a highly flexible on-chip network, called hierarchical mesh, that can adapt to the different amounts of data reuse and bandwidth requirements of different data types, which improves the utilization of the computation resources. Furthermore, Eyeriss v2 can process sparse data directly in the compressed domain for both weights and activations and therefore is able to improve both processing speed and energy efficiency with sparse models. Overall, with sparse MobileNet, Eyeriss v2 in a 65-nm CMOS process achieves a throughput of 1470.6 inferences/s and 25603 inferences/J at a batch size of 1, which is 12.6x faster and 2.5x more energy-efficient than the original Eyeriss running MobileNet.

关键词： Deep neural network accelerators deep learning energy-efficient accelerators dataflow processing spatial architecture

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Multi-Level Encoding and Decoding in a Scalable Photonic Tensor Processor With a Photonic General Matrix Multiply (GeMM) Compiler

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ieee journal OF selected topics IN QUANTUM ELECTRONICS 2022年第6期28卷 1页

作者： Guo, Zhimu Tait, Alexander N. Marquez, Bicky A. Filipovich, Matthew Morison, Hugh Prucnal, Paul R. Chrostowski, Lukas Shekhar, Sudip Shastri, Bhavin J. Queens Univ Dept Phys Engn Phys & Astron Kingston ON K7L 3N6 Canada Queens Univ Dept Elect & Comp Engn Kingston ON K7L 3N6 Canada Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Univ British Columbia Dept Elect & Comp Engn Vancouver BC V6T 1Z4 Canada Vector Inst Toronto ON M5G 1M Canada

The resurgence of artificial intelligence enabled by deep learning and high performance computing has seen a dramatic increase of demand in the accuracy of deep learning model which has come at the cost of computational complexity. The fundamental operations in deep learning models are matrix multiplications, and large scale matrix operations and data-centric tasks have experienced bottlenecks from current digital electronic hardware in terms of performance and scalability. Recent research on photonic processors have found solutions to enable applications in machine learning, neuromorphic computing and high performance computing using basic photonic processing elements on integrated silicon photonic platform. However, efficient and scalable photonic computing requires an information encoding/decoding scheme. Here, we propose a multi-level encoding and decoding scheme, and experimentally demonstrate it with a wavelength-multiplexed silicon photonic processor. We also discuss the scalability of our proposed scheme by introducing a photonic general matrix multiply compiler, and consider the effects of speed, bit precision, and noise. Our proposed scheme could be adapted to a variety of photonic information processing architectures for photonic neural networks, photonics tensor cores, and programmable photonic.

关键词： Photonics Optical attenuators Encoding Heating systems Tensors Optical waveguides Transmission line matrix methods Integrated optics matrix decomposition matrix multiplication optical computing optical neural networks programmable circuits

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Fault Detection and Identification of PMSM Current Sensor Based on Attention Mechanism and Bidirectional Long Short-term Memory Network

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ieee journal of emerging and selected topics in Power Electronics 2025年

作者： Chen, Bin Li, Hongmei Yang, Liguo Yang, Jingyao Zhao, Haonan Hefei University of Technology Electrical Engineering and Automation Hefei230009 China

This study proposes a novel fault detection and identification (FDI) method for permanent magnet synchronous motor (PMSM) current sensors. Specifically, the method integrates an attention mechanism (AM) with a bidirectional long short-term memory (BiLSTM) network to effectively capture temporal dependencies in fault signals and emphasize key features, thereby enhancing the accuracy and robustness of FDI. Furthermore, an early stopping mechanism is employed to prevent overfitting and reduce training time. Experimental comparisons with traditional FDI methods highlight the advantages of the proposed method, including its superior robustness and generalization ability under complex operating conditions. Notably, the method can detect and identify up to five common faults (gain, zero-offset, broken-line, stuck, and intermittent faults) with an accuracy rate of over 99%. © 2013 ieee.

关键词： Timing circuits

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Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine

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ieee journal on emerging and selected topics in circuits and systems 2019年第2期9卷 309-322页

作者： Andri, Renzo Cavigelli, Lukas Rossi, Davide Benini, Luca Swiss Fed Inst Technol Integrated Syst Lab CH-8092 Zurich Switzerland Univ Bologna Dept Elect Elect & Informat Engn I-40126 Bologna Italy

Deep neural networks have achieved impressive results in computer vision and machine learning. Unfortunately, state-of-the-art networks are extremely compute and memory intensive, which makes them unsuitable for mW-devices such as loT end-nodes. Aggressive quantization of these networks dramatically reduces the computation and memory footprint. Binary-weight neural networks (BWNs) follow this trend, pushing weight quantization to the limit. Hardware accelerators for BWNs presented up to now have focused on core efficiency, disregarding I/O bandwidth, and system-level efficiency that are crucial for the deployment of accelerators in ultra-low power devices. We present Hyperdrive: a BWN accelerator dramatically reducing the I/O bandwidth exploiting a novel binary-weight streaming approach, which can he used for an arbitrarily sized convolutional neural network architecture and input resolution by exploiting the natural scalability of the compute units both at chip-level and system-level by arranging Hyperdrive chips systolically in a 2D mesh while processing the entire feature map together in parallel. Hyperdrive achieves 4.3 TOp/s/W system-level efficiency (i.e., including I/Os)-3.1 x higher than state-of-the-art BWN accelerators, even if its core uses resource-intensive FP16 arithmetic for increased robustness.

关键词： Hardware accelerator neural network hardware binary-weight neural networks Internet of Things systolic arrays application specific integrated circuits

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Generalized Topology of a Hybrid Switched- Capacitor Multilevel Inverter for High- Frequency AC Power Distribution

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ieee journal OF emerging AND selected topics IN POWER ELECTRONICS 2020年第3期8卷 2886-2897页

作者： Fong, Yat Chi Raman, S. Raghu Ye, Yuanmao Cheng, Ka Wai Eric Hong Kong Polytech Univ Dept Elect Engn Hong Kong Peoples R China Guangdong Univ Technol Sch Automat Guangzhou 510006 Peoples R China

The generalized topology of a hybrid switched-capacitor multilevel inverter (SCMLI) for high-frequency ac (HFAC) power distribution system is presented. By employing the series-parallel conversion technique, the proposed SCMLI can achieve self-balancing of capacitor voltages and voltage step-up with arbitrary numbers of SC cells. The output power quality is improved by the intermediate voltage levels provided by the bidirectional switched converter connected to the dc source string. Besides, several active switches can be replaced with diodes if the large phase difference between output current and voltage is not required. Since the voltage ripple magnitude of the SC units is inversely proportional to the fundamental output frequency, the proposed SCMLI is more preferable for HFac applications. This paper elucidates the working principle of the proposed inverter with the detailed circuit and switching states' description under staircase modulation. The mathematical analyses associated with the capacitor voltage ripples, sizing, and power loss are also provided. A 19-level MLI with a voltage gain of three was realized by cooperating two SC units with a voltage source string consisting of three symmetric dc sources. The operation and performance of the proposed inverter have been validated by the simulation and experiment on the inverter. The results showed that the inverter performed better at HFac condition and the power quality was satisfactory with the 19-level staircase output modulated at the fundamental frequency.

关键词： Inverters Capacitors Switches Topology Frequency modulation High-frequency dc ac inverter multilevel inverter (MLI) series-parallel conversion switched-capacitor (SC) circuits

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Research From the ieee IBM AI Compute and emerging Technology Symposia

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ieee journal on emerging and selected topics in circuits and systems 2019年第3期9卷 435-438页

作者： Ziegler, Matthew M. Kailas, Krishnan Zhang, Xin Joshi, Rajiv V. IBM Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

In recent years, interest in machine learning, deep learning, and more broadly AI has taken the computing industry by storm. Advancements in AI compute acceleration, along with algorithmic innovations and availability of training data, are widely credited as the catalysts to the resurgence of AI. The potential of AI has caught the interest of researchers spanning various disciplines, e.g., across the hardware and software computing stack, and career stages, e.g., from students to seasoned researchers. This interest has led to a staggering rate of advancement in the field. With the goal of bringing together researchers from various disciplines, career stages, and from industry and academia, the ieee and IBM organized the $1^{\mathrm {st}}$ AI Compute Symposium (AICS18) [items [1] – [4] in the Appendix].

关键词： Special issues and sections Artificial intelligence Machine learning Circuit synthesis Neural networks Computer architecture Machine learning algorithms Nonvolatile memory

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Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing

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ieee journal on emerging and selected topics in circuits and systems 2019年第4期9卷 697-711页

作者： Camusy, Vincent Meiy, Linyan Enz, Christian Verhelst, Marian Ecole Polytech Fed Lausanne ICLAB CH-1015 Lausanne Switzerland Katholieke Univ Leuven ESAT MICAS Lab B-3001 Leuven Belgium

The current trend for deep learning has come with an enormous computational need for billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced precision has demonstrated large benefits with low impact on accuracy, paving the way towards processing in mobile devices and IoT nodes. To this end, various precision-scalable MAC architectures optimized for neural networks have recently been proposed. Yet, it has been hard to comprehend their differences and make a fair judgment of their relative benefits as they have been implemented with different technologies and performance targets. To overcome this, this work exhaustively reviews the state-of-the-art precision-scalable MAC architectures and unifies them in a new taxonomy. Subsequently, these different topologies are thoroughly benchmarked in a 28nm commercial CMOS process, across a wide range of performance targets, and with precision ranging from 2 to 8 bits. circuits are analyzed for each precision as well as jointly in practical use cases, highlighting the impact of architectures and scalability in terms of energy, throughput, area and bandwidth, aiming to understand the key trends to reduce computation costs in neural-network processing.

关键词： Computer architecture Scalability Neural networks Deep learning Application specific integrated circuits Taxonomy ASIC deep neural networks precision-scalable circuits configurable circuits MAC multiply-accumulate units

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