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Photonic Multiply-Accumulate Operations for Neural Networks

ieee journal OF selected topics IN QUANTUM ELECTRONICS 2020年第1期26卷

作者： Nahmias, Mitchell A. de Lima, Thomas Ferreira Tait, Alexander N. Peng, Hsuan-Tung Shastri, Bhavin J. Prucnal, Paul R. Princeton Univ Dept Elect Engn Princeton NJ 08544 USA Queens Univ Dept Phys Engn Phys & Astron Kingston ON K7L 3N6 Canada

It has long been known that photonic communication can alleviate the data movement bottlenecks that plague conventional microelectronic processors. More recently, there has also been interest in its capabilities to implement low precision linear operations, such as matrix multiplications, fast and efficiently. We characterize the performance of photonic and electronic hardware underlying neural network models using multiply-accumulate operations. First, we investigate the limits of analog electronic crossbar arrays and on-chip photonic linear computing systems. Photonic processors are shown to have advantages in the limit of large processor sizes (>100 mu m), large vector sizes (N > 500), and low noise precision (<= 4 bits). We discuss several proposed tunable photonic MAC systems, and provide a concrete comparison between deep learning and photonic hardware using several empiricallyvalidated device and system models. We show significant potential improvements over digital electronics in energy (>10(2)), speed (>10(3)), and compute density (>10(2)).

关键词： Photonics Neural networks Program processors Computational modeling Deep learning Training Metals Artificial intelligence neural networks analog computers analog processing circuits optical computing

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WDM-Compatible Polarization-Diverse OAM Generator and Multiplexer in Silicon Photonics

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ieee journal OF selected topics IN QUANTUM ELECTRONICS 2020年第2期26卷 1页

作者： Chen, Yuxuan Lin, Zhongjin Belanger-de Villers, Simon Rusch, Leslie A. Shi, Wei Univ Laval Ctr Opt Photon & Lasers Univ Dept Elect & Comp Engn Quebec City PQ G1V 0A6 Canada

Spatial multiplexing using orbital angular momentum (OAM) modes is an efficient means of scaling up the capacity of fiber-optic communications systems;integrated multiplexers are crucial enablers of this approach. OAM modes are circularly polarized when propagating in a fiber, however, OAM generators previously demonstrated in silicon photonics use locally linearly polarized emitters. Coupling from multiplexers to fibers in those solutions results in extra loss and complexity. Moreover, many of those solutions are based on resonator structures with strong wavelength dependence, and are thus incompatible with wavelength-division multiplexing (WDM). We experimentally demonstrate on-chip generation and multiplexing of OAM modes using an array of circularly polarized 2-D antennas with wide wavelength coverage. The proposed device was implemented on the standard 220-nm silicon-on-insulator platform. Optical vortex beams with OAM orders ranging from -3 to +3 in both left and right circular polarization states were generated from the same aperture across a wavelength range of 1540 to 1557 nm. This device could serve as a multiplexer or demultiplexer for up to 12 information bearing channels coupling into an OAM fiber, and is compatible with WDM multiplexing as well.

关键词： Crosstalk Two dimensional displays Multiplexing Couplings Polarization Heating systems Silicon Silicon photonics orbital angular momentum space division multiplexing wavelength-division multiplexing integrated photonic circuits

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Guest Editorial Wireless Sensing circuits and systems for Healthcare and Biomedical Applications

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ieee journal on emerging and selected topics in circuits and systems 2018年第2期8卷 161-164页

作者： Li, Changzhi Mak, Pui-In Gomez-Garcia, Roberto Chen, Ying Texas Tech Univ Lubbock TX 79409 USA Univ Macau Fac Sci & Technol ECE Taipa 999078 Macao Peoples R China Univ Macau Res State Key Lab Analog & Mixed Signal VLSI Taipa 999078 Macao Peoples R China Univ Alcala Dept Signal Theory & Commun Madrid 28801 Spain NXP Semicond Chandler AZ 85224 USA

The rapid advancement of radio-frequency (RF), infrared, and optical technologies has enabled many wireless-sensing approaches for novel biomedical applications, such as implantable medical devices, characterization of biological materials, wireless neural prostheses, non-contact health monitoring, and remote-human-motion classification. Some applications entered human daily life shortly after their invention, significantly improving the productivity and life quality in our society. Some emerging applications have shown great potential to benefit the wellbeing of humans but are still under development to overcome technical challenges and incorporate human-factor considerations. With solutions ranging from sensor-on-chip to bench top systems, biomedical wireless sensing has drawn enormous interests from researchers and practitioners in private organizations, academic institutions, and industrial research centers.

关键词： Special issues and sections Wireless sensor networks Biomedical monitoring Implants Biological materials Wireless communication circuits and systems Doppler radar

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Memristive Mixed-Signal Neuromorphic systems: Energy-Efficient Learning at the Circuit-Level

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ieee journal on emerging and selected topics in circuits and systems 2018年第1期8卷 125-136页

作者： Chakma, Gangotree Adnan, Md Musabbir Wyer, Austin R. Weiss, Ryan Schuman, Catherine D. Rose, Garrett S. Univ Tennessee Dept Elect & Comp Engn Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN 37830 USA

Neuromorphic computing is non-von Neumann computer architecture for the post Moore's law era of computing. Since a main focus of the post Moore's law era is energy-efficient computing with fewer resources and less area, neuromorphic computing contributes effectively in this research. In this paper, we present a memristive neuromorphic system for improved power and area efficiency. Our particular mixed-signal approach implements neural networks with spiking events in a synchronous way. Moreover, the use of nano-scale memristive devices saves both area and power in the system. We also provide device-level considerations that make the system more energy-efficient. The proposed system additionally includes synchronous digital long term plasticity, an online learning methodology that helps the system train the neural networks during the operation phase and improves the efficiency in learning considering the power consumption and area overhead.

关键词： Memristor simulator emerging technology neuromorphic computing

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Low-Power, Adaptive Neuromorphic systems: Recent Progress and Future Directions

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ieee journal on emerging and selected topics in circuits and systems 2018年第1期8卷 6-27页

作者： Basu, Arindam Acharya, Jyotibdha Karnik, Tanay Liu, Huichu Li, Hai Seo, Jae-Sun Song, Chang Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore Intel Corp Microarchitecture Res Lab Hillsboro OR 97124 USA Intel Corp Microarchitecture Res Lab Santa Clara CA 95054 USA Duke Univ Durham NC 27519 USA Arizona State Univ Tempe AZ 85287 USA

In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as back-propagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain-machine interfaces, robotics, etc., and identify future research trends in the field.

关键词： Neuromorphics machine learning learning systems adaptive systems low-power electronics artificial neural networks neural network hardware MOS integrated circuits

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Energy-Quality Scalable Integrated circuits and systems: Continuing Energy Scaling in the Twilight of Moore's Law

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ieee journal on emerging and selected topics in circuits and systems 2018年第4期8卷 653-678页

作者： Alioto, Massimo De, Vivek Marongiu, Andrea Natl Univ Singapore Dept Elect & Comp Engn Singapore 117583 Singapore Intel Labs Circuit Technol Res Grp Hillsboro OR 97124 USA Univ Bologna Dept Comp Sci & Engn I-40126 Bologna Italy

This paper aims to take stock of recent advances in the field of energy-quality (EQ) scalable circuits and systems, as promising direction to continue the historical exponential energy downscaling under diminished returns from technology and voltage scaling. EQ-scalable systems explicitly trade off energy and quality at different levels of abstraction and sub-systems, dealing with "quality" as an explicit design requirement, and reducing energy whenever the application, the task, or the dataset allow quality degradation (e.g., vision and machine learning). A general framework for EQ-scalable systems based on the concept of quality slack is presented along with scalable architectures. A taxonomy of techniques to trade off energy and quality, a VLSI perspective, and possible quality control strategies are then discussed. The state of the art is surveyed to put the advances in its different sub-fields into a unitary perspective, emphasizing the on-going and prospective trends. At the component level, the generality of the EQ-scaling concept is shown through several examples, ranging from logic to analog circuits, to memories, data converters, and accelerators. Interesting implications of the joint adoption of EQ scaling and machine learning are also discussed, suggesting that their synergy gives ample room for further energy and performance improvements. From a level of abstraction viewpoint, EQ scaling is discussed from the circuit level to architectures, the hardware-software interface, the programming language, the compiler level, and run-time adaptation. Several case studies are discussed to put EQ scaling in the context of real-world applications.

关键词： Energy-efficient integrated circuits VLSI machine learning signal processing architectures software

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High-Performance Beamforming Network Based on Si-Photonics Phase Shifters for Wideband Communications and Radar Applications

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ieee journal OF selected topics IN QUANTUM ELECTRONICS 2020年第5期26卷

作者： Serafino, Giovanni Porzi, Claudio Hussain, Bilal Scotti, Filippo Falconi, Fabio Chiesa, Marco Toccafondo, Veronica Bogoni, Antonella Ghelfi, Paolo Univ Perfezionamento St Anna Scuola Super I-56124 Pisa Italy Consorzio Nazl Interuniv Telecomunicaz CNIT I-56124 Pisa Italy INPHOTEC Fdn I-56124 Pisa Italy

The evolution of microwave and mm-wave systems for communication and remote sensing is heading towards a massive deployment of phased-array antennas with beamforming capabilities. 5G wireless access networks are expected to employ beamforming to optimize resources allocation, whereas radars will benefit from precise and fast-scanning antennas. Moreover, in the next future, those systems are expected to widely employ photonic technologies for signal generation, acquisition, and distribution. In this scenario, photonics can allow for the development of high-performance beamforming networks, which can easily be integrated in photonics-assisted RF systems, combining broad operational bandwidth, low signal distortion, and high pointing precision with unprecedented flexibility. In this paper, a phase shift-based beamforming network for microwave applications is presented and its performance analyzed. The Si-photonics integrated phase shifters exhibit large phase shift (>360 degrees) and limited amplitude fluctuations (similar to 2.5 dB). The packaged beamforming network elements show extremely low signal distortion, low steering error (<3 degrees), and fast switching time (<5 ns), demonstrated by the transmission with beam-steering of a 2-Gb/s communication signal and of a 1-GHz chirped radar waveform. A comparison with commercial RF devices shows that the photonics-assisted beamforming network is well-suited for high bit-rate 5G communications and for wideband radar applications.

关键词： Microwave photonics Array signal processing Microwave communication Integrated optics Optical filters Phase shifters Optical Phase Shifters Beam steering Phased arrays Photonic Integrated circuits

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Energy-Quality Scalable circuits and systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based

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ieee journal on emerging and selected topics in circuits and systems 2018年第3期8卷 361-368页

作者： Alioto, Massimo De, Vivek Marongiu, Andrea Natl Univ Singapore Dept Elect & Comp Engn Singapore Singapore Intel Corp Portland OR USA Swiss Fed Inst Technol Dept Informat Technol & Elect Engn CH-8006 Zurich Switzerland

Sustained energy efficiency improvements have been instrumental for the vertiginous evolution of electronic systems with computing, sensing, communication and storage capabilities. Energy efficiency improvements are indeed crucial for continued increase in the performance under a limited power budget, reduced operating cost, as well as for untethering traditionally wired systems. This is indeed true for high-performance systems subject to heat removal limitations (e.g., server blades), as well as for operational cost considerations when the cost of electricity is a major fraction of the total cost, as in the case of datacenters [1] , or the more recent crypto-currency mining endeavors [2] . Energy reductions are also critical in portable electronics, due to the limited thermal budget and battery energy availability. Similarly, energy reductions are essential in miniaturized energy-autonomous systems such as sensor nodes, hearables, wearables and others, due to their tightly constrained energy source [3] . Overall, energy efficiency improvements have historically permitted the continuous size down-scaling and lifetime extension of electronic systems (see, [4] ).

关键词： Special issues and sections Scalability Energy efficiency Approximate computing

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Design of Approximate circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

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ieee journal on emerging and selected topics in circuits and systems 2018年第4期8卷 746-757页

作者： Camus, Vincent Cacciotti, Mattia Schlachter, Jeremy Enz, Christian Ecole Polytech Fed Lausanne Integrated Circuits Lab CH-1015 Lausanne Switzerland

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

关键词： Low-power digital circuits timing optimization false timing paths approximate circuits approximate adders speculative adders

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OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators

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ieee journal on emerging and selected topics in circuits and systems 2018年第3期8卷 519-530页

作者： Chen, Chixiao Ding, Hongwei Peng, Huwan Zhu, Haozhe Wang, Yu Shi, C-J Richard Fudan Univ Inst Brain Inspired Circuits & Syst Shanghai 200433 Peoples R China Univ Washington Dept Elect Engn Seattle WA 98195 USA

This paper presents OCEAN: an artificial neural network processor designed for accelerating gated-recurrentunit (GRU) inference and on-chip incremental learning for sequential modeling. Implemented in 65-nm CMOS with silicon area of 2.9 x 3.5 mm(2), the OCEAN processor features a 32-bit reduced instruction set computing core, 64-KB on-chip SRAM, and eight 16-bit four-cell GRU accelerators for inference and gradient computation. Each GRU accelerator is optimized and enhanced for efficient gradient computation. The processor is measured to consume 155 mW at the peak clock rate of 400 MHz and the supply of 1.2 V or 6.6 mW at 20 MHz/0.8 V. Both inference and on-chip incremental learning are accomplished on well-known AI tasks such as handwritten digit recognition, semantic natural language processing, and biomedical waveform based seizure detection.

关键词： Recurrent neural network (RNN) gated recurrent unit (GRU) inference on-chip training deep learning processor energy-efficient accelerator gradient computing

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