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Increased demand for electric power in general and emerging requirements for servicing highly dynamic loads at reduced size and weight of the overall electric power system and its associated components on board ships,...
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Increased demand for electric power in general and emerging requirements for servicing highly dynamic loads at reduced size and weight of the overall electric power system and its associated components on board ships, especially for naval surface combatants, motivates the consideration of a variety of new power systems architectures and technologies. While there are still advances in the alternating current (ac) system, the advent of wide bandgap (WBG) power electronics for high-power applications specifically drives the development of medium-voltage direct current (MVDC) power systems. Those are expected to provide significant operational and economic benefits for future ships. However, several technical challenges arise with MVDC systems. The main objective of this Special Edition is to collect the latest developments from industry and academia to address these technical challenges from different aspects.
Recently, high-speed switching circuits using SiC and GaN power devices have been developed for next-generation power electronics circuits and applied to actual traction systems in Japan. Stray inductance caused by th...
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This paper explores generalized output impedance models and develops a new performance-limit figure of merit (FOM) for switched-capacitor (SC) dc-dc converters that can be resonated or soft-charged with a single induc...
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This paper explores generalized output impedance models and develops a new performance-limit figure of merit (FOM) for switched-capacitor (SC) dc-dc converters that can be resonated or soft-charged with a single inductor. Compared to past work, the output impedance model is greatly simplified through a two-port charge multiplier treatment, yet it maintains accuracy across conversion ratios and is valid in both slow- and fast-switching operation. Building on previous analytical treatments of SC and ReSC converters, the model is expanded to derive optimizations that include both conduction and switching losses. The process is used to identify a new FOM for hybrid-resonant SC converters that can be used to identify the most suitable architectures for a given conversion ratio and relevant (energy or area) constraints on flying capacitors. This is used to highlight the active-device and capacitance utilizations of common topologies, as well as which are most favorable for hybrid-resonant operation.
This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Depar...
This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.
Fast increasing dc fault currents in dc shipboard distribution systems require fast dc protective devices and protection methods. Solid-state circuit breakers (SSCBs) inherently have fast protection speed and thus are...
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Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decodi...
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Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explicit construction. Their recent inclusion in a 5G communication standard will only spur more research. However, only a couple of ASICs featuring decoders for polar codes were fabricated, and none of them implements a list-based decoding algorithm. In this paper, we present ASIC measurement results for a fabricated 28-nm CMOS chip that implements two different decoders: the first decoder is tailored toward error-correction performance and flexibility. It supports any code rate as well as three different decoding algorithms: successive cancellation (SC), SC flip, and SC list (SCL). The flexible decoder can also decode both non-systematic and systematic polar codes. The second decoder targets speed and energy efficiency. We present measurement results for the first silicon-proven SCL decoder, where its coded throughput is shown to be of 306.8 Mbps with a latency of 3.34 us and an energy per bit of 418.3 pJ/b at a clock frequency of 721 MHz for a supply of 1.3 V. The energy per bit drops down to 178.1 pJ/b with a more modest clock frequency of 308 MHz, lower throughput of 130.9 Mbps and a reduced supply voltage of 0.9 V. For the other two operating modes, the energy per bit is shown to be of approximately 95 pJ/b. The less flexible high-throughput unrolled decoder can achieve a coded throughput of 9.2 Gbps and a latency of 628 ns for a measured energy per bit of 1.15 pJ/b at 451 MHz.
In this paper, a formalized common-mode (CM) modeling approach is proposed to transform mixed-mode power system models into their CM equivalent circuits. The approach is first validated through comparison of time-doma...
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In this paper, a formalized common-mode (CM) modeling approach is proposed to transform mixed-mode power system models into their CM equivalent circuits. The approach is first validated through comparison of time-domain waveforms predicted by detailed mixed-mode and CM equivalent models of a representative ship power system. Subsequently, the approach is validated using hardware measurements of the Purdue reducedscale naval dc microgrid. The experimental studies highlight the utility of the proposed modeling approach to assess design questions regarding placement and impedance of system grounds.
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