The emerging spin transfer torque magnetic random access memory (STT-MRAM) promises many attractive features, such as nonvolatile, high speed and low power etc, which enable it to be a promising candidate for the next...
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The emerging spin transfer torque magnetic random access memory (STT-MRAM) promises many attractive features, such as nonvolatile, high speed and low power etc, which enable it to be a promising candidate for the next-generation logic and memory circuits. However with the continuous scaling technology process, the chip yield and reliability of STT-MRAM face severe challenges due to the increasing permanent and transient faults. Due to the intrinsic fault features and the targeted application requirements of STT-MRAM, traditional fault tolerant design solutions, such as error correction code (ECC), redundancy repair (RR), and fault masking (FM) techniques, cannot be employed straightforwardly for STT-MRAM. In this paper, we propose a synergistic technique framework, named sECC, that integrates both the ECC and FM techniques to address simultaneously the permanent and transient faults. With such approach, permanent faults are masked while transient faults are corrected with the same codeword. Moreover taking into consideration the fact that most permanent faults are sparse [about 60%-70% single isolated faults (SIFs)], we propose further integrating the RR and sECC (named iRRsECC) to optimize the system performance. In this scenario, all the SIFs are masked and the transient faults are corrected with the proposed sECC, while other permanent faulty types (e.g., faulty rows or columns) are repaired with redundant rows or columns. A simulation tool is developed to evaluate the proposed techniques and the evaluation results show their good performance in terms of repair rate and hardware overhead.
A fast and efficient system-level design methodology is developed and validated to evaluate and optimize processors using emerging technologies at the early design stage. It includes an updated empirical cycle per ins...
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A fast and efficient system-level design methodology is developed and validated to evaluate and optimize processors using emerging technologies at the early design stage. It includes an updated empirical cycle per instruction model, a hierarchical memory model, and several multi-level interconnection network models. Multiple device-and system-level design parameters are simultaneously optimized to maximize the chip throughput for a given device technology and an architecture family under certain power, thermal and die size budgets. In the single-core processor analysis, a high-performance (HP) 25 mm FinFET processor can provide 26% more throughput than its planar HP complementary metal-oxide-semiconductor (CMOS) counterpart, and a low-power (LP) tunnel field-effect transistor (TFET) processor can offer more than 2X improvement in throughput compared with its LP FinFET counterpart at the 16 nm technology node. For various technology nodes, an accurate power-law relation is observed between the throughput and the die size area for a relatively small processor. In the multi-core processor analyses, multiple device-and system-level design parameters are obtained for both HP and LP applications with symmetric and asymmetric configurations. For a heterogeneous CMOS-TFET multi-core processor, about 45% throughput improvement and 50% energy reduction are observed compared with a FinFET processor at a 5 W power budget.
The cascading of logic gates is a critical challenge for the development of spintronic logic circuits. Here we propose the first logic family exploiting magnetoresistive bipolar spin-transistors to achieve a complete ...
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The cascading of logic gates is a critical challenge for the development of spintronic logic circuits. Here we propose the first logic family exploiting magnetoresistive bipolar spin-transistors to achieve a complete spintronic logic family in which logic gates can be cascaded. This logic family, emitter-coupled spin-transistor logic (ECSTL), is an extension of emitter-coupled logic (ECL) that leverages the advanced features of spintronic devices. The current through the ECL differential amplifier is routed to create a magnetic field that modulates the magnetoamplification of the spin-transistors. This cascading mechanism supplements the voltage cascading available in conventional ECL, providing additional inputs to each logic stage. Each gate therefore has increased logical functionality, leading to logic minimization and compact circuits. No additional current is required to employ this added spintronic switching, resulting in improved speed, area, and power characteristics. This logic family achieves a power-delay product 10-25 times smaller than conventional ECL, inspiring a pathway for high-performance spintronic computing beyond 10 GHz.
This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic portable power generator. The design, implemented in 0.35-mu m CMOS technology, consists of a low-power control s...
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This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic portable power generator. The design, implemented in 0.35-mu m CMOS technology, consists of a low-power control stage and a dc-dc boost power stage with soft-switching capability. With a nominal input voltage of 1 V, and an output voltage of 4 V, we demonstrate a peak conversion efficiency under nominal conditions of over 94% (overall peak efficiency over 95%), at a power level of 300 mW. The control stage uses lossless current sensing together with a custom low-power time-based analogto- digital converter to minimize control losses. The converter employs a fully integrated digital implementation of a peak power-tracking algorithm, and achieves a measured tracking efficiency above 98%. A detailed study of achievable efficiency versus inductor size is also presented, with the calculated and measured results.
RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (Delta Sigma) modulation to transcend the traditional divide between receiver RF...
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RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (Delta Sigma) modulation to transcend the traditional divide between receiver RF front-ends and baseband analog-to-digital converters (ADC). Research on the direct delta-sigma receiver (DDSR) architecture is one example of the emergence of next-generation Delta Sigma modulators. It embeds a direct conversion receiver front-end as part of a feedback-type Delta Sigma modulator structure with an active loop filter, which extends ADC operation to RF and changes the role of the low-noise amplifier (LNA) and mixing stages. RF-to-digital converters thus merge the two formerly separate design domains, requiring a paradigm shift in both RF and ADC design methods. Accordingly, this paper uses the DDSR as an example to bridge the gap between RF and ADC design, by providing a systematic understanding of the role, modeling, and design strategy of the related complete RF front-end. Most importantly, the analysis produces new design equations that link analog RF stage properties to their continuous-time (CT) Delta Sigma modulator coefficients, thus providing a useful circuit design tool.
A new wave energy test site, Pacific Marine Energy Center-South Energy Test Site (PMEC-SETS)-is being proposed for construction off the coast of Newport, Oregon, U.S. The intermittent nature of wave energy presents a ...
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A new wave energy test site, Pacific Marine Energy Center-South Energy Test Site (PMEC-SETS)-is being proposed for construction off the coast of Newport, Oregon, U.S. The intermittent nature of wave energy presents a unique challenge for the transmission system operator, as the integration of a wave energy farm onto the electrical grid creates the potential for disturbance to the operation and stability of the grid. Consequently, this paper assesses the PMEC-SETS development and the impact of its connection to the Oregon (and the rest of the Western Interconnection) network, in terms of steady-state, dynamic, and transient characteristics. The electrical infrastructure analysis is implemented using two power system simulation tools: 1) PowerWorld and 2) DIgSILENT PowerFactory. Power-World is used to create an equivalent model of the transmission system, and DIgSILENT PowerFactory is used to examine the impact of the wave farm at the point of connection, under normal and faulted conditions. A case study of 20 wave energy converters is used to illustrate the results.
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