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Novel energy-efficient modulation technique and circuits for transceivers operating in body sensor networks (BSNs) are described and investigated. They are obtained as a result of the development of differential binar...
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Novel energy-efficient modulation technique and circuits for transceivers operating in body sensor networks (BSNs) are described and investigated. They are obtained as a result of the development of differential binary phase shift keying (DBPSK) and named alternating quadratures DBPSK (AQ-DBPSK). While keeping the noise immunity and simplicity of synchronization and realization of DBPSK, AQ-DBPSK increases the efficiency of the transmitter power utilization by approximate to 6dB and radically improves tolerance to frequency offsets between the receivers and corresponding transmitters. The approach used in the development of AQ-DBPSK can also be used for developing novel spreading and despreading techniques and circuits.
A time-encoding machine (TEM) based new analog-to-digital converter (ADC) architecture is presented in this paper. The main advantage of this architecture is that it relies on asynchronous process and removes an impor...
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A time-encoding machine (TEM) based new analog-to-digital converter (ADC) architecture is presented in this paper. The main advantage of this architecture is that it relies on asynchronous process and removes an important performance limiting factor in conventional ADCs: the clock jitter. Therefore, this architecture is suitable for very high speed ADCs. To expand the bandwidth coverage, the compressive sensing techniques is employed to reconstruct sparse signals with very high frequency. The system can run under two different modes: the normal mode where the signal is sampled at above Nyquist rate and the compressive sensing mode. Nonidealities in circuits and system parameter setting tradeoffs are analyzed to determine the best parameters for the system to reach optimal performance.
In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that a...
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In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that are not possible in complementary metal-oxide-semiconductor-based homogeneous 3-D NoCs. We demonstrate that the proposed 3-D hybrid architecture shows significant improvements in all network parameters including latency, power, and energy consumption compared to other practical 3-D NoCs.
THE ieee International Solid-State circuits Conference (ISSCC) is the flagship conference of the ieee Solid-State circuits Society and the foremost global forum for presenting advances in solid-state circuits and syst...
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THE ieee International Solid-State circuits Conference (ISSCC) is the flagship conference of the ieee Solid-State circuits Society and the foremost global forum for presenting advances in solid-state circuits and systems- on-a-chip. In 2010 and 2011, the ieee Transactions on Biomedical circuits and systems highlighted select papers from the ISSCC conference on topics related to biological and healthcare applications, which were well received. This special issue once again features six select papers from the ISSCC 2012. This set of papers offers a sample of the rapidly expanding developments in solid-state circuits for health monitoring, therapeutics, diagnostics, and medical research applications. The selection of these papers, whose final decision was based on peer review, was coordinated with the Editor-in-Chief of the ieeejournal OF SOLID-STATE circuits, Prof. Un-Ku Moon, to avoid overlap with its ISSCC 2012 special issue, which will include biomedical papers as well. We also acknowledge the ISSCC 2012 General Chair, Prof. Anantha Chandrakasan and the Editor-in-Chief of the ieee Transactions on Biomedical circuits and systems, Prof. Gert Cauwenberghs, for their support.
Compressed sensing (CS) is a new paradigm for the acquisition/ sampling of signals that violates the intuition behind the theorem of Shannon. In fact, CS theory states that, under surprisingly broad conditions it is p...
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Compressed sensing (CS) is a new paradigm for the acquisition/ sampling of signals that violates the intuition behind the theorem of Shannon. In fact, CS theory states that, under surprisingly broad conditions it is possible to reconstruct certain signals or images using far fewer samples or measurements than they are used with traditional methods. To enable this, compressive sensing is based on two concept/principles: 1) sparsity, which is related to the signals of interest, and 2) incoherence, which relates to the methods of measurement/acquisition/ sampling. The aim of this Issue on circuits, systems, and Algorithms for Compressive Sensing is to stimulate a further advancement in this challenging scenario by presenting both results in the exploitation of CS techniques in signals and image processing and, for the first time, by offering to the reader a comprehensive collections of contribution dealing with the design of implementation of circuits and systems exploiting compressive sensing techniques and present them in a systematic way. The response to the call for papers overpassed by far our best expectations. In factwe received 91 high quality submission that out of which 27 were finally accepted for this special issue. Of these, 4 deal with advances in applications of CS to the area of communication and channel estimation or equalization, 6 apply these techniques to image and signal processing, while the remaining 17 papers focus on the main theme of the issue, namely to offer the most recent advances in the design and implementation of circuits and systems exploiting CS.
This paper proposes a power and area efficient electrocardiogram (ECG) acquisition and signal processing application sensor node for wireless body area networks (WBAN). This sensor node can accurately record and detec...
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This paper proposes a power and area efficient electrocardiogram (ECG) acquisition and signal processing application sensor node for wireless body area networks (WBAN). This sensor node can accurately record and detect the QRS peaks of ECG waveform with high-frequency noise suppression. The proposed system is implemented in 0.18-complementary metal-oxide-semiconductor technology with two chips: analog front end integrated circuit (IC) and digital application specific integrated circuit (ASIC), where the analog IC consumes only 79.6 mu W with area of 4.25 mm(2) and digital ASIC consumes 9 mu W at 32 kHz with 1.2 mm(2). Therefore, this ECG sensor node is convenient for long-term monitoring of cardiovascular condition of patients, and is very suitable for on-body WBAN applications.
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